CN106126463B - Bidirectional transmission's low-speed signal amplitude detection circuitry - Google Patents
Bidirectional transmission's low-speed signal amplitude detection circuitry Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The invention discloses a low-speed signal amplitude detection circuit for bidirectional transmission. The invention adopts a potential translation circuit to move a DC working point of a bidirectional communication signal to a DC working point of a low-pass comparator, then the amplitude of a high-speed signal is attenuated by the low-pass comparator, the amplitude of a low-speed signal is reserved, an amplitude square comparator is used for comparing the square of the amplitude of the low-speed signal with the square of a fixed difference value, if the square of the fixed difference value is higher than the set square of the fixed difference value, the low-speed signal is judged to exist, and if the square of the fixed difference value is lower than the set square of the fixed difference value, the low-speed signal is judged to not exist, thereby completing the detection function.
Description
Technical Field
The invention relates to a low-speed signal amplitude detection circuit for bidirectional transmission.
Background
In the video transmission application, the video acquisition signal and the signal processing chip adopt serial transmission, RGB, VSNYC and HSYNC signals need not to be transmitted optically between the acquisition and the signal processing, and low-speed control signals need to be transmitted mutually. If an additional transmission line is added, the weight of the product is increased. In order to save cables, a low-speed signal generator is added at a high-speed receiver end, a low-speed signal receiver is added at a high-speed transmitting end, and high-speed and low-speed signals are superposed on the same cable to complete a bidirectional communication function. The two signals are required to exist in the two-way communication, and when the cable is not connected, the two signals cannot be communicated. Based on the importance of cable connection, the amplitude of low-speed signal detection is increased to judge whether connection is established, and a common detection circuit can only detect non-superimposed unidirectional signals, so a bidirectional signal detection circuit is required to be adopted, as shown in fig. 1.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a bidirectional-transmission low-speed signal amplitude detection circuit which can complete amplitude detection on a low-speed signal of a bidirectional signal.
The purpose of the invention is realized by the following technical scheme: a bi-directional low speed signal amplitude detection circuit, comprising:
a potential shift circuit: the low-pass comparator is used for receiving an input differential signal and converting the DC working point of the differential signal to the DC working point of the first low-pass comparator to keep small amplitude attenuation of the differential signal;
a first low-pass comparator: the input end is connected with the potential translation circuit and is used for attenuating the high-speed component on the differential signal transmitted in the two directions and reserving the component of the low-speed signal;
a second low-pass comparator: the input end of the first low-pass comparator is used for receiving an external reference signal and keeping a path consistent with an input differential signal;
amplitude square comparator: the fixed difference signal input end is connected with the second low-pass comparator, the amplitude detection signal input end is connected with the first low-pass comparator, and the amplitude detection signal input end is used for completing the square comparison of the amplitude square of the input signal and the square of the fixed difference: outputting a high level if the square of the amplitude of the input signal is greater than the square of the fixed difference, and outputting a low level if the square of the amplitude of the input signal is less than the square of the fixed difference;
differential to single-ended comparator: the input end is connected with the amplitude square comparator and is used for converting the low swing differential voltage output by the amplitude square comparator after comparison into a single-ended full swing signal for an external circuit to use.
The potential translation circuit comprises an NMOS transistor MN1, the grid electrode of the MN1 is respectively connected with a signal input Vin and a capacitor C1, the drain electrode of the MN1 is connected with VDD, the source electrode of the MN1 is connected with a resistor R1, and the other end of the resistor R1 is respectively connected with the other end of the capacitor C1, an output end Vout and a current source I SS 1, connection; the substrate of MN1 is grounded.
The first low-pass comparator and the second low-pass comparator respectively comprise NMOS tubes MN2 and MN3 and PMOS tubes MP2 and MP3; the source electrodes of the MP2 and the MP3 are connected with VDD, the grid electrodes of the MP2 and the MP3 are in butt joint, the drain electrode of the MP2 is respectively connected with the drain electrodes of the resistor R2, the load capacitor CL1 and the MN2, the drain electrode of the MP3 is respectively connected with the drain electrodes of the resistor R3, the load capacitor CL2 and the MN3, the other end of the resistor R2 is connected with the other end of the resistor R3, the other end of the resistor R2 and the other end of the resistor R3 are both connected with the grid electrode common connection point of the MP2 and the MP3, the other end of the load capacitor CL2 and the other end of the CL1 are both grounded, the grid electrode of the MN2 is connected with an input voltage Vinp, and the source electrode of the MN2 is connected with a current source I ss 2, the gate of MN3 is connected with input voltage Vinn, the source of MN3 is connected with current source I ss 2 connection, current source I ss 2, the other end is grounded; the drain of MN2 is also connected withThe output terminal Voutn is connected, and the drain of the MN3 is also connected with the output terminal Voutp.
The amplitude square comparator comprises NMOS tubes MN4, MN5, MN6 and MN7 and PMOS tubes MP4 and MP5; the source electrode of the MP4 and the source electrode of the MP5 are connected with VDD, the grid electrode of the MP4 is in butt joint with the grid electrode of the MP5, the drain electrode of the MP4 is connected with the resistor R4, the drain electrode of the MP5 is connected with the resistor R5, the other end of the resistor R4 is connected with the other end of the resistor R5, and the other end of the resistor R4 and the other end of the resistor R5 are both connected with the common connection point of the grid electrodes of the MP4 and the MP5; the grid of MN4 is connected with the positive output end of the second low-pass comparator, the grid of MN5 is connected with the negative output end of the second low-pass comparator, the drain of MN4 is connected with the drain of MP4 after being butted with the drain of MN5, and the source of MN4 is connected with the source of MN5 and then is connected with the current source I SS 3, connecting; the grid of the MN6 is connected with the positive output end of the first low-pass comparator, the grid of the MN7 is connected with the negative output end of the first low-pass comparator, the drain of the MN6 is connected with the drain of the MP5 after being butted with the drain of the MN7, and the source of the MN6 is connected with the source of the MN7 and then is connected with the current source I SS 3, connecting; current source I SS 3, the other end is grounded; the common connection point of the drains of the MN4 and the MN5 is connected to the voltage output terminal Voutn, and the common connection point of the drains of the MN6 and the MN7 is connected to the voltage output terminal Voutp.
The differential-to-single-ended comparator comprises NMOS tubes MN8, MN9, MN10 and MN11 and PMOS tubes MP6, MP7, MP8 and MP9; the source electrodes of the MP6, the MP7, the MP8 and the MP9 are all connected with VDD, the grid electrodes of the MP6 and the MP7 are in butt joint, the drain electrode of the MP6 is respectively connected with the drain electrodes of the resistors R6 and MN8, the drain electrode of the MP7 is respectively connected with the drain electrodes of the resistors R7 and MN9, the other end of the resistor R6 is connected with the other end of the resistor R7, the other end of the resistor R6 and the other end of the resistor R7 are both connected with the grid electrode common connection point of the MP6 and the MP7, the grid electrode of the MN8 is connected with the positive output end of the amplitude square comparator, and the source electrode of the MN8 is connected with the current source I ss 4, the grid of MN9 is connected with the negative output end of the amplitude square comparator, and the source of MN9 is connected with the current source I ss 4 connection, current source I ss 4, the other end is grounded; the drain of MN2 is also connected with the gate of MP8, the drain of MP7 is also connected with the gate of MP9, the drain of MP8 is connected with the drain of MN11, the gate of MN11 is connected with the gate of MN10, and MN11 is connected with the gate of MN10 in commonThe contact is connected with the drain of the MN11, the source of the MN11 and the source of the MN10 are both grounded, and the drain of the MN10 is respectively connected with the drain of the MP9 and the output end Vout.
The invention has the beneficial effects that: the invention is especially suitable for the amplitude detection situation in the two-way transmission in the video transmission application, the circuit adopts and moves the DC operating point of the signal of the two-way communication to the DC operating point of the low-pass comparator through the circuit of the potential translation, then attenuate the amplitude of the high-speed signal through the low-pass comparator, keep the amplitude of the low-speed signal, reuse the square comparator of the amplitude of the low-speed signal to compare with square of the fixed difference value and square of the lower speed signal, if higher than the square of the fixed difference value presumed, judge the low-speed signal to exist, lower than the square of the fixed difference value presumed, judge the low-speed signal does not exist, thus finish the detection function.
Drawings
FIG. 1 is a schematic diagram of a low speed signal amplitude detection circuit;
FIG. 2 is a block diagram of the circuit of the present invention;
FIG. 3 is a circuit diagram of a level shift circuit;
FIG. 4 is a circuit diagram of a low pass comparator;
FIG. 5 is a circuit diagram of a magnitude squared comparator;
fig. 6 is a circuit diagram of a differential-to-single-ended comparator.
Detailed Description
The technical scheme of the invention is further described in detail by combining the attached drawings:
as shown in fig. 2, a bidirectional low-speed signal amplitude detection circuit includes:
a potential shift circuit: the low-pass comparator is used for receiving an input differential signal and converting the DC working point of the differential signal to the DC working point of the first low-pass comparator to keep small amplitude attenuation of the differential signal;
a first low-pass comparator: the input end is connected with the potential translation circuit and is used for attenuating high-speed components on the differential signals transmitted in two directions and reserving components of low-speed signals;
a second low-pass comparator: the input end of the first low-pass comparator is used for receiving an external reference signal and keeping a path consistent with an input differential signal;
amplitude square comparator: the fixed difference signal input end is connected with the second low-pass comparator, the amplitude detection signal input end is connected with the first low-pass comparator, and the amplitude detection signal input end is used for completing the square comparison of the amplitude square of the input signal and the square of the fixed difference: outputting a high level if the square of the magnitude of the input signal is greater than the square of the fixed difference, and outputting a low level if the square of the magnitude of the input signal is less than the square of the fixed difference;
differential to single-ended comparator: the input end is connected with the amplitude square comparator and is used for converting the low swing differential voltage output by the amplitude square comparator after comparison into a single-ended full swing signal for an external circuit to use. The detected signal is directly input into the digital processing module, and the level identification of the digital processing module requires a full swing CMOS level.
As shown in fig. 3, the level shift circuit includes an NMOS transistor MN1, a gate of the NMOS transistor MN1 is connected to a signal input Vin and a capacitor C1, a drain of the NMOS transistor MN1 is connected to VDD, a source of the NMOS transistor MN1 is connected to a resistor R1, and another end of the resistor R1 is connected to another end of the capacitor C1, an output terminal Vout, and a current source I SS 1, connecting; the substrate of MN1 is grounded. The potential translation circuit belongs to a repeated calling circuit, and is called twice in potential translation comparison, namely VIN + is input to call one potential translation circuit, VIN-is input to call the other potential translation circuit, and two inputs and two outputs are formed.
Fig. 3 is a block diagram of a potential shift circuit, and a DC operating point and a transfer function can be obtained by analyzing a correlation structure.
The current of MN1 biased in the saturation region satisfies the following equation:
where Un is electron mobility, cox is gate oxide capacitance, W is channel width of the transistor, L is channel length of the transistor, vthn is threshold voltage of the N-type transistor, vin is input voltage, vout is output voltage, and R is resistance value.
The input and output DC operating voltage relationship can be deduced from (1):
from (2), iss, R, W, and L determine the DC operating point of the output.
The transfer function can be analyzed by small signals, from equivalence, to obtain the following equation:
Vbs＝O-(Vin-Vgs)＝Vgs-Vin (3)
wherein Vbs is the source-substrate voltage of the transistor, vgs is the gate-source voltage of the transistor, cgs is the gate-source capacitance of the transistor, S is the angular frequency, gm is the transconductance of the transistor, ro is the output resistance of the transistor, gmb is the transconductance of the transistor substrate, and C is the capacitance value. ro1 is the output resistance of the transistor MN1, and ro2 is the output resistance of the current source ISS 1.
By solving the three equations, since Cgs < C, ro1 and ro2 are large, the gain Av is obtained:
from (6), it can be seen that the zero point is before the pole, the transfer function is high-pass characteristic, and ω > 1/(R × C) the gain Av ≈ 1, so that the amplitude enters the low-pass comparator without attenuation.
The capacitance impedance is a frequency-dependent quantity, and the alternating current characteristic is expressed by a complex number S = j ω, ω of an imaginary part,
i.e. angular velocity and frequency conversion equationWhere ω is larger, i.e., the frequency is higher. In ohm's law of alternating current, the capacitive impedance is
The inductance impedance is L x S.
As shown in fig. 4, the first low-pass comparator and the second low-pass comparator each include NMOS transistors MN2 and MN3 and PMOS transistors MP2 and MP3; the source electrodes of the MP2 and the MP3 are connected with VDD, the grid electrodes of the MP2 and the MP3 are in butt joint, the drain electrode of the MP2 is respectively connected with the drain electrodes of the resistor R2, the load capacitor CL1 and the MN2, the drain electrode of the MP3 is respectively connected with the drain electrodes of the resistor R3, the load capacitor CL2 and the MN3, the other end of the resistor R2 is connected with the other end of the resistor R3, the other end of the resistor R2 and the other end of the resistor R3 are both connected with the grid electrode common connection point of the MP2 and the MP3, the other end of the load capacitor CL2 and the other end of the CL1 are both grounded, the grid electrode of the MN2 is connected with an input voltage Vinp, and the source electrode of the MN2 is connected with a current source I ss 2, the gate of MN3 is connected with input voltage Vinn, the source of MN3 is connected with current source I ss 2 connection, current source I ss 2, the other end is grounded; the drain of MN2 is further connected to the output terminal Voutn, and the drain of MN3 is further connected to the output terminal Voutp.
The low-pass comparator attenuates the high-speed signal on the bidirectional transmission signal, and the amplitude of the low-speed signal is preserved, so that the attenuation band is selected between two rates.
The transfer function of the low-pass comparator uses half-edge equivalence to find the gain:
the transfer function shows a low-pass characteristic, and at ω > (1 + gm3R)/(R CL), the high-speed signal is attenuated, while the low-speed signal is also attenuated by gm 1R/(1 + gm3R). Wherein gm1 is the transconductance of the MN2 transistor, and gm3 is the transconductance of the MP2 transistor.
In order to maintain a path that is identical to the input signal, the attenuation values are also matched at the fixed difference signal end via the same low-pass comparator.
As shown in fig. 5, the magnitude square comparator includes NMOS transistors MN4, MN5, MN6MN7 and PMOS tubes MP4 and MP5; the source electrode of the MP4 and the source electrode of the MP5 are connected with VDD, the grid electrode of the MP4 is in butt joint with the grid electrode of the MP5, the drain electrode of the MP4 is connected with the resistor R4, the drain electrode of the MP5 is connected with the resistor R5, the other end of the resistor R4 is connected with the other end of the resistor R5, and the other end of the resistor R4 and the other end of the resistor R5 are both connected with the common connection point of the grid electrodes of the MP4 and the MP5; the grid of MN4 is connected with the positive output end of the second low-pass comparator, the grid of MN5 is connected with the negative output end of the second low-pass comparator, the drain of MN4 is connected with the drain of MP4 after being butted with the drain of MN5, and the source of MN4 is connected with the source of MN5 and then is connected with the current source I SS 3, connecting; the grid of MN6 is connected with the positive output end of the first low-pass comparator, the grid of MN7 is connected with the negative output end of the first low-pass comparator, the drain of MN6 is connected with the drain of MP5 after being butted with the drain of MN7, and the source of MN6 is connected with the source of MN7 and then is connected with the current source I SS 3, connecting; current source I SS 3, the other end is grounded; the common connection point of the drains of the MN4 and the MN5 is connected to the voltage output terminal Voutn, and the common connection point of the drains of the MN6 and the MN7 is connected to the voltage output terminal Voutp.
When MN4, MN5, MN6, and MN7 all operate at the DC operating point of Vcm (Vcm is input common mode voltage), i.e. Vref =0, vin =0, the current flowing through MN4, MN5, MN6, M7 is:
where Vds is the drain-source voltage of the transistor.
It can be seen that the current of the current source uniformly flows through 4 NMOS transistors, the current of the branch of MN4 and MN5 is Iss/2, the current of the branch of MN6 and MN7 is Iss/2, the circuits on both sides are completely symmetrical, and the output differential voltage relationship is obtained:
it can be seen that the differential voltage Voutp-Voutn =0, i.e. the inputs on both sides are equal. In the formula, vthp is the threshold voltage of the P-type transistor, and Up is the hole mobility.
There is a fixed voltage difference Δ V between MN4 and MN5, while MN3 and MN4 are still at Vcm, i.e. Vref = Δ V, vin =0. Let the voltage of MN4 be Vcm + Δ V/2, the voltage of MN5 be Vcm- Δ V/2, the current flowing through MN4 and MN5 changes:
decomposed and added by the square of (10) and (11), and combined (8), then:
the above equation shows that the required current of the branches MN4 and MN5 increases, because the total current Iss is constant, the current of the branches MN6 and MN7 decreases to compensate for the increased current of MN4 and MN5, and the current flows through the resistor, so that the output voltage changes:
the output differential voltage is:
there is a fixed voltage difference Vref between MN4 and MN5, and a voltage difference Vin between MN6 and MN7, and the output differential voltage is:
as shown in fig. 6, the differential-to-single-ended comparator includes NMOS transistors MN8, MN9, MN10, MN11 and PMOS transistors MP6, MP7, MP8, MP9; the source electrodes of the MP6, the MP7, the MP8 and the MP9 are all connected with VDD, the grid electrodes of the MP6 and the MP7 are in butt joint, the drain electrode of the MP6 is respectively connected with the drain electrodes of the resistors R6 and MN8, the drain electrode of the MP7 is respectively connected with the drain electrodes of the resistors R7 and MN9, the other end of the resistor R6 is connected with the other end of the resistor R7, the other end of the resistor R6 and the other end of the resistor R7 are both connected with the grid electrode common connection point of the MP6 and the MP7, the grid electrode of the MN8 is connected with the positive output end of the amplitude square comparator, and the source electrode of the MN8 is connected with the current source I ss 4, the grid of MN9 is connected with the negative output end of the amplitude square comparator, and the source of MN9 is connected with the current source I ss 4 connection, current source I ss 4, the other end is grounded; the drain of the MN2 is also connected with the gate of the MP8, the drain of the MP7 is also connected with the gate of the MP9, the drain of the MP8 is connected with the drain of the MN11, the gate of the MN11 is connected with the gate of the MN10, the common connection point of the gates of the MN11 and the MN10 is connected with the drain of the MN11, the source of the MN11 and the source of the MN10 are both grounded, and the drain of the MN10 is respectively connected with the drain of the MP9 and the output end Vout.
After the comparison is completed, the output differential voltage is a low swing signal and needs to be converted into a single-ended full swing signal for use by an internal processing circuit, and fig. 6 shows a general differential-to-single-ended comparator structure.
When Vinp is greater than Vinn, the current of MN8 tends to be larger than that of MN9, the voltage of MP8 is reduced, the voltage of MP9 is increased, the voltage of MN11 is continuously increased, MN10 mirrors the current of MN11, a larger current is needed at the output end NM10, MP9 cannot provide the larger current, MN10 enters a linear region, and the output Vout is the ground voltage; similarly, when Vinp is less than Vinn, the current of MN9 tends to be greater than the current of MN8, the voltage of MP9 decreases, the voltage of MP8 increases, the voltage of MN11 continuously decreases, MN10 mirrors the current of MN11, and when the output end MP9 supplies more current than the current required by MN10, MP9 enters a linear region and outputs a high voltage.
Claims (3)
1. A bidirectional transmission low-speed signal amplitude detection circuit is characterized in that: it includes:
a potential shift circuit: the low-amplitude differential comparator comprises an NMOS tube MN1, wherein the grid electrode of the MN1 is respectively connected with a signal input Vin and a capacitor C1, the drain electrode of the MN1 is connected with a VDD, the source electrode of the MN1 is connected with a resistor R1, the other end of the resistor R1 is respectively connected with the other end of the capacitor C1, an output end Vout and a current source I SS 1 connection, current source I SS The other end of the 1 is grounded; the substrate of MN1 is grounded;
a first low-pass comparator: the input end is connected with the potential translation circuit and is used for attenuating the high-speed component on the differential signal transmitted in the two directions and reserving the component of the low-speed signal;
a second low-pass comparator: the input end of the first low-pass comparator is used for receiving an external reference signal and keeping a path consistent with an input differential signal;
the first low-pass comparator and the second low-pass comparator respectively comprise NMOS tubes MN2 and MN3 and PMOS tubes MP2 and MP3; the source electrodes of the MP2 and the MP3 are connected with VDD, the grid electrodes of the MP2 and the MP3 are in butt joint, the drain electrode of the MP2 is respectively connected with the drain electrodes of the resistor R2, the load capacitor CL1 and the MN2, the drain electrode of the MP3 is respectively connected with the drain electrodes of the resistor R3, the load capacitor CL2 and the MN3, the other end of the resistor R2 is connected with the other end of the resistor R3, the other end of the resistor R2 and the other end of the resistor R3 are both connected with the grid electrode common connection point of the MP2 and the MP3, the other end of the load capacitor CL2 and the other end of the CL1 are both grounded, the grid electrode of the MN2 is connected with an input voltage Vinp, and the source electrode of the MN2 is connected with a current source I ss 2, the gate of MN3 is connected with input voltage Vinn, the source of MN3 is connected with current source I ss 2 connection, current source I ss The other end of 2 is grounded; the drain electrode of the MN2 is also connected with the output end Voutn, and the drain electrode of the MN3 is also connected with the output end Voutp;
amplitude square comparator: the fixed difference signal input end is connected with the second low-pass comparator, the amplitude detection signal input end is connected with the first low-pass comparator, and the amplitude detection signal input end is used for completing the square comparison of the amplitude of the input signal and the square of the fixed difference: outputting a high level if the square of the magnitude of the input signal is greater than the square of the fixed difference, and outputting a low level if the square of the magnitude of the input signal is less than the square of the fixed difference;
differential-to-single-ended comparator: the input end is connected with the amplitude square comparator and is used for converting the low-swing differential voltage output by the amplitude square comparator after comparison into a single-ended full-swing signal for an external circuit to use.
2. The bi-directional low speed signal amplitude detection circuit of claim 1, wherein: the amplitude square comparator comprises NMOS tubes MN4, MN5, MN6 and MN7 and PMOS tubes MP4 and MP5; the source electrode of the MP4 and the source electrode of the MP5 are connected with VDD, the grid electrode of the MP4 is in butt joint with the grid electrode of the MP5, the drain electrode of the MP4 is connected with the resistor R4, the drain electrode of the MP5 is connected with the resistor R5, the other end of the resistor R4 is connected with the other end of the resistor R5, and the other end of the resistor R4 and the other end of the resistor R5 are both connected with the common connection point of the grid electrodes of the MP4 and the MP5; the grid of MN4 is connected with the positive output end of the second low-pass comparator, the grid of MN5 is connected with the negative output end of the second low-pass comparator, the drain of MN4 is connected with the drain of MP4 after being butted with the drain of MN5, and the source of MN4 is connected with the source of MN5 and then is connected with the current source I SS 3, connecting; the grid of MN6 is connected with the positive output end of the first low-pass comparator, the grid of MN7 is connected with the negative output end of the first low-pass comparator, the drain of MN6 is connected with the drain of MP5 after being butted with the drain of MN7, and the source of MN6 is connected with the source of MN7 and then is connected with the current source I SS 3, connecting; current source I SS 3, the other end is grounded; the common connection point of the drains of the MN4 and the MN5 is connected to the voltage output terminal Voutn, and the common connection point of the drains of the MN6 and the MN7 is connected to the voltage output terminal Voutp.
3. A bi-directional low speed signal amplitude detection circuit according to claim 1, characterized in that: the differential-to-single-ended comparator comprises NMOS tubes MN8, MN9, MN10 and MN11 and PMOS tubes MP6, MP7, MP8 and MP9; the source electrodes of the MP6, the MP7, the MP8 and the MP9 are all connected with VDD, the grid electrodes of the MP6 and the MP7 are in butt joint, the drain electrode of the MP6 is respectively connected with the drain electrodes of the resistors R6 and MN8, the drain electrode of the MP7 is respectively connected with the drain electrodes of the resistors R7 and MN9, the other end of the resistor R6 is connected with the other end of the resistor R7, and the other end of the resistor R6 is connected with the other end of the resistor R6One end of the resistor R7 and the other end of the resistor R8 are connected with the common connection point of the grids of the MP6 and the MP7, the grid of the MN8 is connected with the positive output end of the amplitude square comparator, and the source of the MN8 is connected with the current source I ss 4, the gate of MN9 is connected with the negative output end of the amplitude square comparator, and the source of MN9 is connected with the current source I ss 4 connection, current source I ss 4, the other end is grounded; the drain of the MN8 is also connected with the gate of the MP8, the drain of the MP7 is also connected with the gate of the MP9, the drain of the MP8 is connected with the drain of the MN11, the gate of the MN11 is connected with the gate of the MN10, the common connection point of the gates of the MN11 and the MN10 is connected with the drain of the MN11, the source of the MN11 and the source of the MN10 are both grounded, and the drain of the MN10 is respectively connected with the drain of the MP9 and the output end Vout.
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| CN105652070A (en) * | 2016-01-21 | 2016-06-08 | 烽火通信科技股份有限公司 | Differential signal amplitude detection circuit |
| CN206147611U (en) * | 2016-08-02 | 2017-05-03 | 成都振芯科技股份有限公司 | Bidirectional's low -speed signal amplitude detection circuitry |
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| CN1270724A (en) * | 1997-08-08 | 2000-10-18 | 埃瑞康姆公司 | Method and system for rapid initial signal detection in a wireless communications system |
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| CN102981991A (en) * | 2012-11-13 | 2013-03-20 | 四川和芯微电子股份有限公司 | Serial data transmission system and serial data transmission method |
| CN105652070A (en) * | 2016-01-21 | 2016-06-08 | 烽火通信科技股份有限公司 | Differential signal amplitude detection circuit |
| CN206147611U (en) * | 2016-08-02 | 2017-05-03 | 成都振芯科技股份有限公司 | Bidirectional's low -speed signal amplitude detection circuitry |
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