CN106294254B - A kind of low speed signal amplitude detection method of transmitted in both directions - Google Patents
A kind of low speed signal amplitude detection method of transmitted in both directions Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention discloses a kind of low speed signal amplitude detection methods of transmitted in both directions.The present invention uses the operating point DC for the operating point DC of the signal of two-way communication being moved on to by level shift circuit low pass comparator, then by low pass comparator come the amplitude for high speed signal of decaying, retain the amplitude of low speed signal, the quadratic sum consistent difference square for comparing low speed signal amplitude with amplitude square comparator again compares, determine that low speed signal exists if the consistent difference square than setting is high, it is lower than the consistent difference square of setting, determine that low speed signal is not present, to complete detection function.
Description
Technical field
The present invention relates to a kind of low speed signal amplitude detection methods of transmitted in both directions.
Background technique
In transmission of video using inner, video acquisition Signal and Signal Treatment chip uses serial transmission, needs to acquire and believe
Not optical transport RGB and VSNYC, HSYNC signal between number processing, while needing the control signal of transmission low speed between each other.Such as
Fruit additionally increases by a transmission lines again, will increase the weight of product.In order to save cable, increase low speed letter at high-speed receiver end
Number generator increases low speed signal receiver in high speed transmitting terminal, is superimposed upon at a high speed on the same cable and completes with low speed signal
Bi-directional communication function.Both need both signals that will exist in two-way communication, when cable does not connect upper, can allow
It communicates invalid.Based on the importance connected to cable, increase the amplitude of detection low speed signal, to judge whether connection is true,
And common detection circuit can only detect the one way signal not being superimposed, so must using can to two-way signaling detection circuit,
As shown in Figure 1.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of low speed signal amplitude detections of transmitted in both directions
Method can complete amplitude detection to the low speed signal of two-way signaling.
The purpose of the present invention is achieved through the following technical solutions: a kind of low speed signal amplitude detection of transmitted in both directions
Method, it the following steps are included:
S1: the differential signal of input is received by level shift circuit, and the operating point DC of differential signal is transformed into the
The operating point DC of one low pass comparator keeps the decaying by a small margin of differential signal；
S2: the high velocity component on the differential signal for the transmitted in both directions that decayed by the first low pass comparator, and retain low speed letter
Number component, the input terminal of the first low pass comparator connect with level shift circuit；Simultaneously by with the first low pass comparator knot
The identical second low pass comparator of structure, keeps the consistent path of differential signal with input, and the second low pass comparator input terminal connects
Receive external reference signal；
S3: by amplitude square comparator complete amplitude square and the consistent difference of input signal square compared with: if
The amplitude square of input signal is high level than square big then output of consistent difference, if the amplitude square of input signal is than solid
Square small then output for determining difference is low level；Wherein, the consistent difference signal input part of amplitude square comparator is low with second
Logical comparator connection, the amplitude detection signal input terminal of amplitude square comparator are connect with the first low pass comparator；
S4: turn the low swing differential voltage exported after single-ended comparators complete amplitude square comparator by difference
It is converted into single-ended full swing signal, for external circuit use；Difference turns single-ended comparators input terminal and amplitude square comparator
Connection.
The level shift circuit includes NMOS tube MN1, and the grid of MN1 inputs Vin and capacitor C1 with signal respectively
Connection, the drain electrode of MN1 meet VDD, the source electrode connecting resistance R1 of MN1, the other end of resistance R1 respectively with the other end of capacitor C1, output
Hold Vout and current source ISS1 connection；The Substrate ground of MN1.
The first low pass comparator and the second low pass comparator include NMOS tube MN2, MN3 and PMOS tube MP2 and
MP3；The source electrode of MP2 and MP3 connect VDD, MP2 and MP3 grid docking, the drain electrode of MP2 respectively with resistance R2, load capacitance CL1
It is connected with the drain electrode of MN2, the drain electrode of MP3 is connect with the drain electrode of resistance R3, load capacitance CL2 and MN3 respectively, and resistance R2's is another
End is connect with the other end of resistance R3, the other end of the other end of resistance R2 and resistance R3 with the public company of the grid of MP2 and MP3
Contact connection, the other end and the CL1 other end of load capacitance CL2 are grounded, and the grid of MN2 connects input voltage vin p, the source of MN2
Pole and current source Iss2 connections, the grid of MN3 connect input voltage vin n, the source electrode and current source I of MN3ss2 connections, current source Iss2
The other end ground connection；The drain electrode of MN2 is also connect with output end vo utn, and the drain electrode of MN3 is also connect with output end vo utp.
The amplitude square comparator includes NMOS tube MN4, MN5, MN6, MN7 and PMOS tube MP4, MP5；The source of MP4
The source electrode of pole and MP5 meet VDD, and the grid docking of the grid and MP5 of MP4, the drain electrode of MP4 is connect with resistance R4, the drain electrode of MP5 and
Resistance R5 connection, the other end of resistance R4 are connect with the other end of resistance R5, the other end of resistance R4 and the other end of resistance R5
It is connect with the grid points of common connection of MP4 and MP5；The grid of MN4 is connect with the positive output end of the second low pass comparator, MN5
Grid connect with the negative output terminal of the second low pass comparator, the drain electrode of MN4 connects after docking with the drain electrode of MN5 with the drain electrode of MP4
Connect, the source electrode of MN4 docked with the source electrode of MN5 after with current source ISS3 connections；The grid of MN6 is just defeated with the first low pass comparator
Outlet connection, the grid of MN7 connect with the negative output terminal of the first low pass comparator, after the drain electrode of MN6 is docked with the drain electrode of MN7 and
The drain electrode of MP5 connects, the source electrode of MN6 docked with the source electrode of MN7 after with current source ISS3 connections；Current source ISS3 another termination
Ground；The drain electrode points of common connection of MN4 and MN5 is connect with voltage output end Voutn, the drain electrode points of common connection and electricity of MN6 and MN7
Press output end vo utp connection.
The difference turn single-ended comparators include NMOS tube MN8, MN9, MN10, MN11 and PMOS tube MP6, MP7, MP8,
MP9；The source electrode of MP6, MP7, MP8, MP9 are connect with VDD, the docking of the grid of MP6 and MP7, the drain electrode of MP6 respectively with resistance R6
It is connected with the drain electrode of MN8, the drain electrode of MP7 is connect with the drain electrode of resistance R7 and MN9 respectively, and the other end of resistance R6 is with resistance R7's
Other end connection, the other end of resistance R6 and the other end of resistance R7 are connect with the grid points of common connection of MP6 and MP7, MN8
Grid connect with the positive output end of amplitude square comparator, the source electrode of MN8 and current source Iss4 connections, the grid and amplitude of MN9
The negative output terminal connection of square comparator, the source electrode and current source I of MN9ss4 connections, current source Iss4 other end ground connection；MN2
Drain electrode also connect with the grid of MP8, the drain electrode of MP7 is also connect with the grid of MP9, and the drain electrode of MP8 is connect with the drain electrode of MN11,
The grid of MN11 and the grid of MN10 connect, the drain electrode connection of the grid points of common connection and MN11 of MN11 and MN10, MN11's
The drain electrode of the source grounding of source electrode and MN10, MN10 is connect with the drain electrode of MP9 and output end vo ut respectively.
The beneficial effects of the present invention are: the present invention is especially suitable for the amplitude detections in transmitted in both directions in transmission of video application
Situation, the circuit use the DC work for the operating point DC of the signal of two-way communication being moved on to by level shift circuit low pass comparator
Make a little, then by low pass comparator come the amplitude for high speed signal of decaying, retain the amplitude of low speed signal, then with amplitude square ratio
The quadratic sum consistent difference square for comparing low speed signal amplitude compared with device compares, if than the consistent difference square Gao Ze of setting
Determine that low speed signal exists, it is lower than the consistent difference square of setting, determine that low speed signal is not present, to complete detection function.
Detailed description of the invention
Fig. 1 is the schematic diagram that low speed signal amplitude detection circuit generates；
Fig. 2 is the method for the present invention flow chart；
Fig. 3 be process of the invention based on circuit block diagram；
Fig. 4 is the circuit diagram of level shift circuit；
Fig. 5 is low pass comparator circuit figure；
Fig. 6 is amplitude square comparator circuit figure；
Fig. 7 is that difference turns single-ended comparators circuit diagram.
Specific embodiment
Technical solution of the present invention is described in further detail with reference to the accompanying drawing:
As shown in Fig. 2, a kind of low speed signal amplitude detection method of transmitted in both directions, it the following steps are included:
S1: the differential signal of input is received by level shift circuit, and the operating point DC of differential signal is transformed into the
The operating point DC of one low pass comparator keeps the decaying by a small margin of differential signal；
S2: the high velocity component on the differential signal for the transmitted in both directions that decayed by the first low pass comparator, and retain low speed letter
Number component: the input terminal of the first low pass comparator is connect with level shift circuit；Simultaneously by with the first low pass comparator knot
The identical second low pass comparator of structure, keeps the consistent path of differential signal with input, and the second low pass comparator input terminal connects
Receive external reference signal；
S3: by amplitude square comparator complete amplitude square and the consistent difference of input signal square compared with: if
The amplitude square of input signal is high level than square big then output of consistent difference, if the amplitude square of input signal is than solid
Square small then output for determining difference is low level；Wherein, the consistent difference signal input part of amplitude square comparator is low with second
Logical comparator connection, the amplitude detection signal input terminal of amplitude square comparator are connect with the first low pass comparator；
S4: turn the low swing differential voltage exported after single-ended comparators complete amplitude square comparator by difference
It is converted into single-ended full swing signal, for external circuit use；Difference turns single-ended comparators input terminal and amplitude square comparator
Connection.The signal that detection is completed directly inputs digital processing module, and the identification of the level of digital processing module requires as the full amplitude of oscillation
CMOS level.
As shown in figure 4, the level shift circuit includes NMOS tube MN1, the grid of MN1 inputs Vin with signal respectively
And capacitor C1 connection, the drain electrode of MN1 meet VDD, the source electrode connecting resistance R1 of MN1, the other end of resistance R1 is respectively with capacitor C1's
The other end, output end vo ut and current source ISS1 connection；The Substrate ground of MN1.Level shift circuit belongs to repetition and calls electricity
Road, current potential translation relatively in call twice, i.e., input VIN+ call a level shift circuit and input VIN- call it is another
A level shift circuit forms two inputs and two outputs.
Fig. 4 is level shift circuit block diagram, by the available operating point DC of emitter following structural analysis and transmission function.
The electric current for being biased in the MN1 of saturation region meets equation:
In formula, Un is electron mobility, and Cox is gate oxide capacitance, and W is the channel width of transistor, and L is transistor
Channel length, Vthn are the threshold voltage of N-type transistor, and Vin is input voltage, and Vout is output voltage, and R is resistance value.
It can be released by (1) and output and input DC operating voltage relationship:
Iss, R, W, L known to (2) determine the operating point DC of output.
Transmission function can obtain following equation according to equivalent by small-signal analysis:
Vbs=0- (Vin-Vgs)=Vgs-Vin (3)
In formula, Vbs is that the source of transistor serves as a contrast voltage, and Vgs is the gate source voltage of transistor, and Cgs is the grid source electricity of transistor
Hold, S is angular frequency, and gm is the mutual conductance of transistor, and ro is the output resistance of transistor, and gmb is the mutual conductance of transistor substrate, and C is
Capacitance.Ro1 is the output resistance of transistor MN1, and ro2 is the output resistance of the ISS1 of current source.
By because Cgs < < C, ro1 and ro2 is very big, obtaining gain A v to three equatioies solutions:
By zero point known to (6) before pole, transmission function is high pass characteristic, and ω > > 1/ (R*C) Shi ZengyiA v ≈
1, make amplitude close zero-decrement into low pass comparator.
Condensance is amount varying with frequency in formula, and with plural S=j* ω, the ω of imaginary part states AC characteristic,That is angular speed and frequency conversion formula, ω is bigger, i.e., frequency is higher.In the Ohm's law of exchange, condensance isInductive impedance is L*S.
As shown in figure 5, the first low pass comparator and the second low pass comparator include NMOS tube MN2, MN3 and
PMOS tube MP2 and MP3；The source electrode of MP2 and MP3 connect VDD, MP2 and MP3 grid docking, the drain electrode of MP2 respectively with resistance R2,
Load capacitance CL1 is connected with the drain electrode of MN2, and the drain electrode of MP3 is connect with the drain electrode of resistance R3, load capacitance CL2 and MN3 respectively,
The other end of resistance R2 is connect with the other end of resistance R3, the other end of the other end of resistance R2 and resistance R3 with MP2 and MP3
The connection of grid points of common connection, the other end and the CL1 other end of load capacitance CL2 be grounded, and the grid of MN2 connects input voltage
The source electrode and current source I of Vinp, MN2ss2 connections, the grid of MN3 connect input voltage vin n, the source electrode and current source I of MN3ss2 connect
It connects, current source Iss2 other end ground connection；The drain electrode of MN2 is also connect with output end vo utn, and the drain electrode of MN3 is also and output end
Voutp connection.
Low pass comparator is the high speed signal decaying on two-way transmission signals, and the amplitude of low speed signal retains, so
Attenuation band selects between two rates.
Transmission function one side of something of low pass comparator is equivalent to find out gain:
Transmission function is shown as low-pass characteristic, and in ω > > (1+gm3*R)/(R*CL), high speed signal is attenuated, while low
Fast signal also has the decaying of gm1*R/ (1+gm3*R).Wherein, gm1 be MN2 transistor mutual conductance, gm3 be MP2 transistor across
It leads.
In order to keep with the consistent path of input signal, similarly compare by the same low pass in consistent difference signal end
Device, matching attenuation value.
As shown in fig. 6, the amplitude square comparator include NMOS tube MN4, MN5, MN6, MN7 and PMOS tube MP4,
MP5；The source electrode of MP4 and the source electrode of MP5 meet VDD, the grid docking of the grid and MP5 of MP4, and the drain electrode of MP4 is connect with resistance R4,
The drain electrode of MP5 is connect with resistance R5, and the other end of resistance R4 is connect with the other end of resistance R5, the other end and resistance of resistance R4
The other end of R5 is connect with the grid points of common connection of MP4 and MP5；The positive output of the grid of MN4 and the second low pass comparator
End connection, the grid of MN5 connect with the negative output terminal of the second low pass comparator, after the drain electrode of MN4 is docked with the drain electrode of MN5 and
The drain electrode of MP4 connects, the source electrode of MN4 docked with the source electrode of MN5 after with current source ISS3 connections；The grid of MN6 and the first low pass ratio
Positive output end compared with device connects, and the grid of MN7 is connect with the negative output terminal of the first low pass comparator, the drain electrode and the leakage of MN7 of MN6
Pole docking after connect with the drain electrode of MP5, the source electrode of MN6 docked with the source electrode of MN7 after with current source ISS3 connections；Current source ISS3
The other end ground connection；The drain electrode points of common connection of MN4 and MN5 is connect with voltage output end Voutn, and the drain electrode of MN6 and MN7 are public
Tie point is connect with voltage output end Voutp.
It all works in MN4, MN5, MN6 and MN7 in the operating point DC (Vcm is common mode input) of Vcm, i.e. Vref=0,
When Vin=0, the electric current of MN4, MN5, MN6, M7 are flowed through are as follows:
In formula, Vds is the drain-source voltage of transistor.
It can be seen that the electric current of current source uniform flows 4 NMOS tubes, the electric current of this branch of MN4 and MN5 is Iss/
The electric current of this branch of 2, MN6 and MN7 is also equally Iss/2, and the circuit on both sides is full symmetric, and the differential voltage exported is closed
System:
It can be seen that differential voltage Voutp-Voutn=0, i.e. both sides input is equal.In formula, Vthp is P-type transistor
Threshold voltage, Up are hole mobility.
There is fixed voltage difference Δ V in MN4 and MN5, and MN3 and MN4 are still in Vcm, i.e. Vref=Δ V, Vin=0.Enable MN4
Voltage be the voltage of Vcm+ Δ V/2, MN5 be Vcm- Δ V/2, the electric current for flowing through MN4 and MN5 is changed:
It is decomposed and is added with square formula of (11) by (10), in conjunction with (8), then:
Above equation find out MN4 and MN5 branch need electric current increase because total electric current Iss is certain, MN6 and
The electric current of MN7 branch can reduce to make up the increased electric current of MN4 and MN5, and electric current is flowed through from resistance, to allow the voltage of output
It changes:
The differential voltage of output are as follows:
There is fixed voltage difference Vref in MN4 and MN5, and MN6 and MN7 have pressure difference Vin, the differential voltage of output are as follows:
As shown in fig. 7, it includes NMOS tube MN8, MN9, MN10, MN11 and PMOS tube that the difference, which turns single-ended comparators,
MP6,MP7,MP8,MP9；The source electrode of MP6, MP7, MP8, MP9 are connect with VDD, the grid docking of MP6 and MP7, the drain electrode of MP6
It is connect respectively with the drain electrode of resistance R6 and MN8, the drain electrode of MP7 is connect with the drain electrode of resistance R7 and MN9 respectively, and resistance R6's is another
End is connect with the other end of resistance R7, the other end of the other end of resistance R6 and resistance R7 with the public company of the grid of MP6 and MP7
Contact connection, the grid of MN8 are connect with the positive output end of amplitude square comparator, the source electrode and current source I of MN8ss4 connections, MN9
Grid connect with the negative output terminal of amplitude square comparator, the source electrode of MN9 and current source Iss4 connections, current source Iss4 it is another
One end ground connection；The drain electrode of MN2 is also connect with the grid of MP8, and the drain electrode of MP7 is also connect with the grid of MP9, the drain electrode of MP8 with
The drain electrode of MN11 connects, and the grid of MN11 and the grid of MN10 connect, the grid points of common connection and MN11 of MN11 and MN10
The drain electrode of drain electrode connection, the source electrode of MN11 and the source grounding of MN10, MN10 connects with the drain electrode of MP9 and output end vo ut respectively
It connects.
After completing relatively, the differential voltage of output is that low swing signal needs to be converted into single-ended full swing signal for interior
Portion's processing circuit uses, and Fig. 7 shows to be that general difference turns single-ended comparators structure.
As Vinp > Vinn, the electric current of MN8 has the tendency that, greater than MN9 electric current, the voltage of MP8 reduces, the voltage liter of MP9
The voltage of height, MN11 persistently increases, MN10 mirror image MN11 electric current, and in output end NM10 needs bigger electric current, MP9 is provided not
, MN10 will be low-voltage into linear zone, output Vout；With should Vinp < Vinn when, the electric current of MN9 has greater than MN8
The voltage of the trend of electric current, MP9 reduces, and the voltage of MP8 increases, and the voltage of MN11 persistently reduces, the electric current of MN10 mirror image MN11,
Electric currents more more than MN10 demand are provided in output end MP9, MP9 will enter linear zone, export as high voltage.
Claims (5)
1. a kind of low speed signal amplitude detection method of transmitted in both directions, it is characterised in that: it the following steps are included:
S1: receiving the differential signal of input by level shift circuit, and it is low that the operating point DC of differential signal is transformed into first
The operating point DC of logical comparator, keeps the decaying by a small margin of differential signal；
S2: the high velocity component on the differential signal for the transmitted in both directions that decayed by the first low pass comparator, and retain low speed signal
Component: the input terminal of the first low pass comparator is connect with level shift circuit；Simultaneously by with the first low pass comparator configuration phase
With the second low pass comparator, keep the consistent path of differential signal with input, the second low pass comparator input terminal receives outer
Portion's reference signal；
S3: by amplitude square comparator complete amplitude square and the consistent difference of input signal square compared with: if input
The amplitude square of signal is high level than square big then output of consistent difference, if the amplitude square of input signal compares fixed difference
Square small then output of value is low level；Wherein, the consistent difference signal input part of amplitude square comparator and the second low pass ratio
It is connected compared with device, the amplitude detection signal input terminal of amplitude square comparator is connect with the first low pass comparator；
S4: it is converted by the low swing differential voltage that difference turns to export after single-ended comparators complete amplitude square comparator
At single-ended full swing signal, for external circuit use；Difference turns single-ended comparators input terminal and connect with amplitude square comparator.
2. a kind of low speed signal amplitude detection method of transmitted in both directions according to claim 1, it is characterised in that: described
Level shift circuit includes NMOS tube MN1, and the grid of MN1 is connect with signal input Vin and capacitor C1 respectively, the drain electrode of MN1
Meet VDD, the source electrode connecting resistance R1 of MN1, the other end of resistance R1 respectively with the other end of capacitor C1, output end vo ut and electric current
Source ISS1 connection；The Substrate ground of MN1.
3. a kind of low speed signal amplitude detection method of transmitted in both directions according to claim 1, it is characterised in that: described
First low pass comparator and the second low pass comparator include NMOS tube MN2, MN3 and PMOS tube MP2 and MP3；MP2's and MP3
Source electrode connects the grid docking of VDD, MP2 and MP3, and the drain electrode of MP2 connects with the drain electrode of resistance R2, load capacitance CL1 and MN2 respectively
It connects, the drain electrode of MP3 is connect with the drain electrode of resistance R3, load capacitance CL2 and MN3 respectively, and the other end of resistance R2 is with resistance R3's
Other end connection, the other end of resistance R2 and the other end of resistance R3 are connect with the grid points of common connection of MP2 and MP3, are born
The other end and the CL1 other end for carrying capacitor CL2 are grounded, and the grid of MN2 connects input voltage vin p, the source electrode and current source of MN2
Iss2 connections, the grid of MN3 connect input voltage vin n, the source electrode and current source I of MN3ss2 connections, current source Iss2 another termination
Ground；The drain electrode of MN2 is also connect with output end vo utn, and the drain electrode of MN3 is also connect with output end vo utp.
4. a kind of low speed signal amplitude detection method of transmitted in both directions according to claim 1, it is characterised in that: described
Amplitude square comparator includes NMOS tube MN4, MN5, MN6, MN7 and PMOS tube MP4, MP5；The source electrode of MP4 and the source electrode of MP5 connect
The grid docking of the grid and MP5 of VDD, MP4, the drain electrode of MP4 are connect with resistance R4, and the drain electrode of MP5 is connect with resistance R5, resistance
The other end of R4 is connect with the other end of resistance R5, the grid of the other end of resistance R4 and the other end of resistance R5 with MP4 and MP5
The connection of pole points of common connection；The grid of MN4 is connect with the positive output end of the second low pass comparator, the grid of MN5 and the second low pass
The negative output terminal of comparator connects, and the drain electrode of MN4 is connect with after the drain electrode of MN5 docking with the drain electrode of MP4, the source electrode and MN5 of MN4
Source electrode docking after with current source ISS3 connections；The grid of MN6 is connect with the positive output end of the first low pass comparator, the grid of MN7
It is connect with the negative output terminal of the first low pass comparator, the drain electrode of MN6 is connect with after the drain electrode of MN7 docking with the drain electrode of MP5, MN6
Source electrode docked with the source electrode of MN7 after with current source ISS3 connections；Current source ISS3 other end ground connection；The drain electrode of MN4 and MN5
Points of common connection is connect with voltage output end Voutn, and the drain electrode points of common connection and voltage output end Voutp of MN6 and MN7 connect
It connects.
5. a kind of low speed signal amplitude detection method of transmitted in both directions according to claim 1, it is characterised in that: described
It includes NMOS tube MN8, MN9, MN10, MN11 and PMOS tube MP6, MP7, MP8, MP9 that difference, which turns single-ended comparators,；MP6,MP7,
The source electrode of MP8, MP9 are connect with VDD, the grid docking of MP6 and MP7, the drain electrode drain electrode with resistance R6 and MN8 respectively of MP6
Connection, the drain electrode of MP7 are connect with the drain electrode of resistance R7 and MN9 respectively, and the other end of resistance R6 is connect with the other end of resistance R7,
The other end of resistance R6 and the other end of resistance R7 are connect with the grid points of common connection of MP6 and MP7, the grid and width of MN8
Spend the positive output end connection of square comparator, the source electrode and current source I of MN8ss4 connections, the grid and amplitude square comparator of MN9
Negative output terminal connection, the source electrode of MN9 and current source Iss4 connections, current source Iss4 other end ground connection；The drain electrode of MN2 also with
The grid of MP8 connects, and the drain electrode of MP7 is also connect with the grid of MP9, and the drain electrode of MP8 is connect with the drain electrode of MN11, the grid of MN11
It is connect with the grid of MN10, the drain electrode of the grid points of common connection and MN11 of MN11 and MN10 connects, the source electrode and MN10 of MN11
Source grounding, the drain electrode of MN10 connect with the drain electrode of MP9 and output end vo ut respectively.
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