CN106294254A - A kind of low speed signal amplitude detection method of transmitted in both directions - Google Patents

Abstract

The invention discloses a kind of low speed signal amplitude detection method of transmitted in both directions.The present invention uses the DC operating point by level shift circuit, the DC operating point of the signal of two-way communication being moved on to low pass comparator, it is then passed through the low pass comparator amplitude to high speed signal of decaying, retain the amplitude of low speed signal, compare the quadratic sum consistent difference square of low speed signal amplitude with amplitude square comparator again to compare, if higher than the consistent difference square set, judge that low speed signal exists, lower than the consistent difference square set, judge that low speed signal does not exists, thus complete detection function.

Description

A kind of low speed signal amplitude detection method of transmitted in both directions

Technical field

The present invention relates to a kind of low speed signal amplitude detection method of transmitted in both directions.

Background technology

In transmission of video is applied, video acquisition Signal and Signal Treatment chip uses serial transmission, needs to gather and letter Not optical transport RGB and VSNYC, HSYNC signal between number processing, simultaneously need to transmit the control signal of low speed each other.As Fruit the most additionally increases by a transmission lines, can increase the weight of product.In order to save cable, increase low speed letter at high-speed receiver end Number generator, increases low speed signal receptor at high speed transmitting terminal, is superimposed upon on same cable completes with low speed signal at a high speed Bi-directional communication function.Two-way communication needs both signals will exist, cable does not connect when, can be allowed both Communication is false.Based on the importance that cable is connected, increase the amplitude of detection low speed signal, judge to connect and whether set up, And common testing circuit can only detect the one way signal not having superposition, thus must use can to two-way signaling testing circuit, As shown in Figure 1.

Summary of the invention

It is an object of the invention to overcome the deficiencies in the prior art, it is provided that the low speed signal amplitude detection of a kind of transmitted in both directions Method, can complete amplitude detection to the low speed signal of two-way signaling.

It is an object of the invention to be achieved through the following technical solutions: the low speed signal amplitude detection of a kind of transmitted in both directions Method, it comprises the following steps:

S1: received the differential signal of input by level shift circuit, and the DC operating point of differential signal is transformed into the The DC operating point of one low pass comparator, keeps the decay by a small margin of differential signal；

S2: by the high velocity component on the differential signal of the first low pass comparator decay transmitted in both directions, and retain low speed letter Number component, the input of the first low pass comparator is connected with level shift circuit；Simultaneously by tying with the first low pass comparator The second low pass comparator that structure is identical, keeps the path consistent with the differential signal of input, and the second low pass comparator input terminal connects Receive external reference signal；

S3: complete the duplicate ratio of the amplitude square of input signal and consistent difference relatively by amplitude square comparator: if The amplitude square of input signal square is then output as high level greatly than consistent difference, if the amplitude square of input signal is than solid Determine the square little of difference, be output as low level；Wherein, the consistent difference signal input part of amplitude square comparator and second low Logical comparator connects, and the amplitude detection signal input of amplitude square comparator and the first low pass comparator connect；

S4: turned the low swing differential voltage exported after amplitude square comparator is completed by single-ended comparators by difference It is converted into single-ended full swing signal, uses for external circuit；Difference turns single-ended comparators input and amplitude square comparator Connect.

Described level shift circuit includes NMOS tube MN1, and the grid of MN1 inputs Vin and electric capacity C1 with signal respectively Connecting, the drain electrode of MN1 meets the source electrode connecting resistance R1 of VDD, MN1, the other end of resistance R1 respectively with the other end, the output of electric capacity C1 End Vout and current source I_SS1 connects；The Substrate ground of MN1.

The first described low pass comparator and the second low pass comparator all include NMOS tube MN2, MN3 and PMOS MP2 and MP3；The source electrode of MP2 and MP3 connect VDD, MP2 and MP3 grid docking, the drain electrode of MP2 respectively with resistance R2, load capacitance CL1 Connecting with the drain electrode of MN2, the drain electrode of MP3 drain electrode with resistance R3, load capacitance CL2 and MN3 respectively is connected, another of resistance R2 End is connected with the other end of resistance R3, the other end of resistance R2 and the other end of resistance R3 all public companies with the grid of MP2 and MP3 Contact connects, and the other end of load capacitance CL2 and the equal ground connection of the CL1 other end, the grid of MN2 connects input voltage vin p, the source of MN2 Pole and current source I_ss2 connect, and the grid of MN3 connects input voltage vin n, the source electrode of MN3 and current source I_ss2 connect, current source I_ss2 Other end ground connection；The drain electrode of MN2 is also connected with output end vo utn, and the drain electrode of MN3 is also connected with output end vo utp.

Described amplitude square comparator includes NMOS tube MN4, MN5, MN6, MN7 and PMOS MP4, MP5；The source of MP4 The source electrode of pole and MP5 connects the grid docking of the grid of VDD, MP4 and MP5, and the drain electrode of MP4 is connected with resistance R4, the drain electrode of MP5 and Resistance R5 connects, and the other end of resistance R4 is connected with the other end of resistance R5, the other end of resistance R4 and the other end of resistance R5 All it is connected with the grid points of common connection of MP4 and MP5；The grid of MN4 and the positive output end of the second low pass comparator connect, MN5 Grid and the negative output terminal of the second low pass comparator connect, the drain electrode of MN4 dock with the drain electrode of MN5 after with the drain electrode of MP4 company Connect, the source electrode of MN4 dock with the source electrode of MN5 after with current source I_SS3 connect；The grid of MN6 and the first low pass comparator the most defeated Going out end to connect, the grid of MN7 connects with the negative output terminal of the first low pass comparator, after the drain electrode of MN6 is docked with the drain electrode of MN7 and The drain electrode of MP5 connects, the source electrode of MN6 dock with the source electrode of MN7 after with current source I_SS3 connect；Current source I_SSAnother termination of 3 Ground；The drain electrode points of common connection of MN4 and MN5 is connected with voltage output end Voutn, the drain electrode points of common connection of MN6 and MN7 and electricity Pressure output end vo utp connects.

Described difference turn single-ended comparators include NMOS tube MN8, MN9, MN10, MN11 and PMOS MP6, MP7, MP8, MP9；The source electrode of MP6, MP7, MP8, MP9 is all connected with VDD, the docking of the grid of MP6 and MP7, the drain electrode of MP6 respectively with resistance R6 Connecting with the drain electrode of MN8, the drain electrode of MP7 drain electrode with resistance R7 and MN9 respectively is connected, the other end of resistance R6 and resistance R7's The other end connects, and the other end of resistance R6 and the other end of resistance R7 are all connected with the grid points of common connection of MP6 and MP7, MN8 Grid be connected with the positive output end of amplitude square comparator, the source electrode of MN8 and current source I_ss4 connect, the grid of MN9 and amplitude The negative output terminal of square comparator connects, the source electrode of MN9 and current source I_ss4 connect, current source I_ssThe other end ground connection of 4；MN2 Drain electrode be also connected with the grid of MP8, the drain electrode of MP7 is also connected with the grid of MP9, and the drain electrode of MP8 is connected with the drain electrode of MN11, The grid of MN11 is connected with the grid of MN10, and the grid points of common connection of MN11 with MN10 is connected with the drain electrode of MN11, MN11's Source electrode and the source grounding of MN10, the drain electrode of MN10 is connected with drain electrode and the output end vo ut of MP9 respectively.

The invention has the beneficial effects as follows: the present invention is especially suitable for the amplitude detection in transmitted in both directions in transmission of video application Situation, this circuit uses the DC work by level shift circuit, the DC operating point of the signal of two-way communication being moved on to low pass comparator Make a little, be then passed through the low pass comparator amplitude to high speed signal of decaying, retain the amplitude of low speed signal, then use amplitude square ratio Relatively device compares the quadratic sum consistent difference square of low speed signal amplitude and compares, if than the consistent difference square Gao Ze set Judge that low speed signal exists, lower than the consistent difference square set, judge that low speed signal does not exists, thus complete detection function.

Accompanying drawing explanation

Fig. 1 is the schematic diagram that low speed signal amplitude detection circuit produces；

Fig. 2 is the inventive method flow chart；

Fig. 3 be the present invention flow process based on circuit block diagram；

Fig. 4 is the circuit diagram of level shift circuit；

Fig. 5 is low pass comparator circuit figure；

Fig. 6 is amplitude square comparator circuit figure；

Fig. 7 is that difference turns single-ended comparators circuit diagram.

Detailed description of the invention

Technical scheme is described in further detail below in conjunction with the accompanying drawings:

As in figure 2 it is shown, a kind of low speed signal amplitude detection method of transmitted in both directions, it comprises the following steps:

S1: received the differential signal of input by level shift circuit, and the DC operating point of differential signal is transformed into the The DC operating point of one low pass comparator, keeps the decay by a small margin of differential signal；

S2: by the high velocity component on the differential signal of the first low pass comparator decay transmitted in both directions, and retain low speed letter Number component: the input of the first low pass comparator is connected with level shift circuit；Simultaneously by tying with the first low pass comparator The second low pass comparator that structure is identical, keeps the path consistent with the differential signal of input, and the second low pass comparator input terminal connects Receive external reference signal；

S3: complete the duplicate ratio of the amplitude square of input signal and consistent difference relatively by amplitude square comparator: if The amplitude square of input signal square is then output as high level greatly than consistent difference, if the amplitude square of input signal is than solid Determine the square little of difference, be output as low level；Wherein, the consistent difference signal input part of amplitude square comparator and second low Logical comparator connects, and the amplitude detection signal input of amplitude square comparator and the first low pass comparator connect；

S4: turned the low swing differential voltage exported after amplitude square comparator is completed by single-ended comparators by difference It is converted into single-ended full swing signal, uses for external circuit；Difference turns single-ended comparators input and amplitude square comparator Connect.The signal detected directly inputs digital signal processing module, and the level identification of digital signal processing module requires as the full amplitude of oscillation CMOS level.

As shown in Figure 4, described level shift circuit includes NMOS tube MN1, and the grid of MN1 inputs Vin with signal respectively And electric capacity C1 connects, the drain electrode of MN1 meets the source electrode connecting resistance R1 of VDD, MN1, and the other end of resistance R1 is respectively with electric capacity C1's The other end, output end vo ut and current source I_SS1 connects；The Substrate ground of MN1.Level shift circuit belongs to and repeats to call electricity Road, calls twice in current potential translation relatively, i.e. input VIN+ calls a level shift circuit and inputs VIN-and call another Individual level shift circuit, defines two inputs and two outputs.

Fig. 4 is level shift circuit block diagram, can obtain DC operating point and transmission function by correlation with structural analysis.

The electric current of the MN1 being biased in saturation region meets equation:

$Iss=\frac{Un*Cox*W*{(Vin-Vout-Iss*R-Vthn)}^2}{2*L}---\left(1\right)$

In formula, Un is electron mobility, and Cox is gate oxide capacitance, and W is the channel width of transistor, and L is transistor Channel length, Vthn is the threshold voltage of N-type transistor, and Vin is input voltage, and Vout is output voltage, and R is resistance value.

Input can be released by (1) and export DC running voltage relation:

$Vout=Vin-Vthn-Iss*R-\sqrt{\frac{2*Iss*L}{Un*Cox*W}}---\left(2\right)$

Understood Iss, R, W, L by (2) and determine the DC operating point of output.

Transmission function can pass through small-signal analysis, obtains below equation according to equivalence:

Vbs=0-(Vin-Vgs)=Vgs-Vin (3)

$\frac{Vgs}{\frac{1}{Cgs*S}}+gm*Vgs+\frac{0-(Vin-Vgs)}{ro1}+gmb(0-(Vin-Vgs\left)\right)=0---\left(4\right)$

$\frac{Vin-Vout}{\frac{1}{C*S}}+\frac{Vin-Vgs-Vout}{R}+\frac{Vout}{ro2}=0---\left(5\right)$

In formula, Vbs is the source lining voltage of transistor, and Vgs is the gate source voltage of transistor, and Cgs is the grid source electricity of transistor Holding, S is angular frequency, and gm is the mutual conductance of transistor, and ro is the output resistance of transistor, and gmb is the mutual conductance of transistor substrate, and C is Capacitance.Ro1 is the output resistance of transistor MN1, and ro2 is the output resistance of the ISS1 of current source.

By three equatioies are solved, because Cgs < < C, ro1 and ro2 are very big, obtain gain A v:

$Av=\frac{Vout}{Vin}=\frac{gmb}{(gm+gmb)}*\frac{1+\frac{gm+gmb}{gmb}*R*C*S}{1+R*C*S}---\left(6\right)$

By (6) understand zero point before limit, transmission function be high pass characteristic, and ω > > 1/ (R*C) time gain A v ≈ 1, Allow the nearly zero-decrement entrance low pass comparator of amplitude.

In formula, condensance is the amount with frequency change, states AC characteristic with plural number S=j* ω, the ω of imaginary part,I.e. angular velocity and frequency conversion formula, ω is the biggest, i.e. frequency is the highest.In the Ohm's law of exchange, condensance isInductive impedance is L*S.

As it is shown in figure 5, the first described low pass comparator and the second low pass comparator all include NMOS tube MN2, MN3 and PMOS MP2 and MP3；The source electrode of MP2 and MP3 connect VDD, MP2 and MP3 grid docking, the drain electrode of MP2 respectively with resistance R2, The drain electrode of load capacitance CL1 and MN2 connects, and the drain electrode of MP3 drain electrode with resistance R3, load capacitance CL2 and MN3 respectively is connected, The other end of resistance R2 is connected with the other end of resistance R3, the other end of resistance R2 and the other end of resistance R3 all with MP2 and MP3 Grid points of common connection connect, the other end of load capacitance CL2 and the equal ground connection of the CL1 other end, the grid of MN2 connects input voltage The source electrode of Vinp, MN2 and current source I_ss2 connect, and the grid of MN3 connects input voltage vin n, the source electrode of MN3 and current source I_ss2 even Connect, current source I_ssThe other end ground connection of 2；The drain electrode of MN2 is also connected with output end vo utn, and the drain electrode of MN3 is also and outfan Voutp connects.

Low pass comparator is that the high speed signal on two-way transmission signals is decayed, and the amplitude of low speed signal retains, so Attenuation band selects between two speed.

Gain is obtained in the half of equivalence of the transmission function of low pass comparator:

$Av=\frac{Voutp-Voum}{Vinp-Vinn}=\frac{gm1*R}{(1+gm3*R)}*\frac{1}{1+\frac{R}{1+gm3*R}*CL*S}---\left(7\right)$

Transmission function is shown as low-pass characteristic, at ω > > (1+gm3*R)/(R*CL), high speed signal is attenuated, simultaneously low speed Signal also has the decay of gm1*R/ (1+gm3*R).Wherein, gm1 is the mutual conductance of MN2 transistor, and gm3 is the mutual conductance of MP2 transistor.

In order to keep the path consistent with input signal, compare through the same low pass too at consistent difference signal end Device, matching attenuation value.

As shown in Figure 6, described amplitude square comparator include NMOS tube MN4, MN5, MN6, MN7 and PMOS MP4, MP5；The source electrode of MP4 and the source electrode of MP5 connect the grid of VDD, MP4 and the grid docking of MP5, and the drain electrode of MP4 is connected with resistance R4, The drain electrode of MP5 is connected with resistance R5, and the other end of resistance R4 is connected with the other end of resistance R5, the other end of resistance R4 and resistance The other end of R5 is all connected with the grid points of common connection of MP4 and MP5；The grid of MN4 and the positive output of the second low pass comparator End connects, and the grid of MN5 connects with the negative output terminal of the second low pass comparator, after the drain electrode of MN4 is docked with the drain electrode of MN5 and The drain electrode of MP4 connects, the source electrode of MN4 dock with the source electrode of MN5 after with current source I_SS3 connect；The grid of MN6 and the first low pass ratio The positive output end of relatively device connects, and the grid of MN7 and the negative output terminal of the first low pass comparator connect, the drain electrode of MN6 and the leakage of MN7 Pole docking after be connected with the drain electrode of MP5, the source electrode of MN6 dock with the source electrode of MN7 after with current source I_SS3 connect；Current source I_SS3 Other end ground connection；The drain electrode points of common connection of MN4 and MN5 is connected with voltage output end Voutn, and the drain electrode of MN6 and MN7 is public Junction point is connected with voltage output end Voutp.

All be operated in the DC operating point (Vcm is common mode input) of Vcm at MN4, MN5, MN6 and MN7, i.e. Vref=0, The when of Vin=0, the electric current flowing through MN4, MN5, MN6, M7 is:

$I1=I2=I3=I4=\frac{Un*Cox*W*{(Vcm-Vds-Vthn)}^2}{2*L}=\frac{Iss}{4}---\left(8\right)$

In formula, Vds is the drain-source voltage of transistor.

Can be seen that the electric current of current source uniform flows 4 NMOS tube, the electric current of this branch road of MN4 and MN5 is Iss/ The electric current of 2, MN6 and MN7 these branch roads is the most also Iss/2, and the circuit on both sides is full symmetric, and the differential voltage obtaining output is closed System:

$Voutp=Voutn=Vdd-Vthp-\sqrt{\frac{2L}{Up*Cox*W}*\frac{Iss}{2}}---\left(9\right)$

Can be seen that differential voltage Voutp-Voutn=0, i.e. both sides input is equal.In formula, Vthp is P-type transistor Threshold voltage, Up is hole mobility.

There is fixed voltage difference Δ V at MN4 and MN5, and MN3 and MN4 is still at Vcm, i.e. Vref=Δ V, Vin=0.Make MN4 Voltage be Vcm+ Δ V/2, the voltage of MN5 is Vcm-Δ V/2, flows through the electric current of MN4 and MN5 and there occurs change:

$I1=\frac{Un*Cox*W*{(Vcm+\mathrm{\&Delta;}V/2-Vds-Vthn)}^2}{2*L}---\left(10\right)$

$I2=\frac{Un*Cox*W*{(Vcm-\mathrm{\&Delta;}V/2-Vds-Vthn)}^2}{2*L}---\left(11\right)$

Decomposed by a square formula for (10) and (11) and be added, in conjunction with (8), then:

$I1+I2=\frac{Iss}{2}+\frac{Un*Cox*W*{\mathrm{\&Delta;V}}^2}{4*L}---\left(12\right)$

Above equation finds out that the electric current that the branch road of MN4 and MN5 needs adds because total electric current Iss is certain, MN6 and The electric current of MN7 branch road can reduce to make up the electric current that MN4 and MN5 increases, and electric current flows through from resistance, thus allows the voltage of output Change:

$Voutn=Vdd-Vthp-\sqrt{\frac{2*L}{Up*Cox*W}*\frac{Iss}{2}}-\frac{Un*Cox*W*{\mathrm{\&Delta;V}}^2}{4*L}*R---\left(13\right)$

$Voutp=Vdd-Vthp-\sqrt{\frac{2*L}{Up*Cox*W}*\frac{Iss}{2}}+\frac{Un*Cox*W*{\mathrm{\&Delta;V}}^2}{4*L}*R---\left(14\right)$

The differential voltage of output is:

$Voutp-Voutn=\frac{Un*Cox*W*{\mathrm{\&Delta;V}}^2}{2*L}*R---\left(15\right)$

Having fixed voltage difference Vref at MN4 and MN5, and MN6 and MN7 has pressure reduction Vin, the differential voltage of output is:

$Voutp-Voutn=\frac{Un*Cox*W*({\mathrm{Vin}}^2-{\mathrm{Vref}}^2)}{2*L}*R---\left(16\right)$

As it is shown in fig. 7, described difference turns single-ended comparators includes NMOS tube MN8, MN9, MN10, MN11 and PMOS MP6、MP7、MP8、MP9；The source electrode of MP6, MP7, MP8, MP9 is all connected with VDD, the grid docking of MP6 and MP7, the drain electrode of MP6 Drain electrode with resistance R6 and MN8 is connected respectively, and the drain electrode of MP7 drain electrode with resistance R7 and MN9 respectively is connected, another of resistance R6 End is connected with the other end of resistance R7, the other end of resistance R6 and the other end of resistance R7 all public companies with the grid of MP6 and MP7 Contact connects, and the grid of MN8 is connected with the positive output end of amplitude square comparator, the source electrode of MN8 and current source I_ss4 connect, MN9 Grid be connected with the negative output terminal of amplitude square comparator, the source electrode of MN9 and current source I_ss4 connect, current source I_ss4 another One end ground connection；The drain electrode of MN2 is also connected with the grid of MP8, and the drain electrode of MP7 is also connected with the grid of MP9, the drain electrode of MP8 with The drain electrode of MN11 connects, and the grid of MN11 is connected with the grid of MN10, and the grid points of common connection of MN11 Yu MN10 is with MN11's Drain electrode connects, the source electrode of MN11 and the source grounding of MN10, and the drain electrode of MN10 is respectively with the drain electrode of MP9 and output end vo ut even Connect.

After completing comparison, the differential voltage of output is that low swing signal needs to be converted into single-ended full swing signal for interior Portion processes circuit and uses, and what Fig. 7 showed turns single-ended comparators structure for general difference.

As Vinp ＞ Vinn, the electric current of MN8 has the trend more than MN9 electric current, and the voltage of MP8 reduces, the voltage liter of MP9 Height, the voltage of MN11 persistently raises, the electric current of MN10 mirror image MN11, and at outfan NM10 needs bigger electric current, MP9 provides Not, MN10 will enter linear zone, and output Vout is ground voltage；With should Vinp ＜ Vinn time, the electric current of MN9 has and is more than The trend of MN8 electric current, the voltage of MP9 reduces, and the voltage of MP8 raises, and the voltage of MN11 persistently reduces, the electricity of MN10 mirror image MN11 Stream, provides more more electric current than MN10 demand at outfan MP9, and MP9 will enter linear zone, is output as high voltage.

Claims (5)

1. the low speed signal amplitude detection method of a transmitted in both directions, it is characterised in that: it comprises the following steps:

S1: received the differential signal of input by level shift circuit, and it is low that the DC operating point of differential signal is transformed into first The DC operating point of logical comparator, keeps the decay by a small margin of differential signal；

S2: by the high velocity component on the differential signal of the first low pass comparator decay transmitted in both directions, and retain low speed signal Component: the input of the first low pass comparator is connected with level shift circuit；Simultaneously by with the first low pass comparator configuration phase The second same low pass comparator, keeps the path consistent with the differential signal of input, outside the second low pass comparator input terminal receives Portion's reference signal；

S3: complete the duplicate ratio of the amplitude square of input signal and consistent difference relatively by amplitude square comparator: if input The amplitude square of signal square is then output as high level greatly, if the amplitude square of input signal compares fixed difference than consistent difference Value square little, is output as low level；Wherein, the consistent difference signal input part of amplitude square comparator and the second low pass ratio Relatively device connects, and the amplitude detection signal input of amplitude square comparator and the first low pass comparator connect；

S4: turned the low swing differential voltage conversion exported after amplitude square comparator is completed by single-ended comparators by difference Become single-ended full swing signal, use for external circuit；Difference turns single-ended comparators input and is connected with amplitude square comparator.

The low speed signal amplitude detection method of a kind of transmitted in both directions the most according to claim 1, it is characterised in that: described Level shift circuit includes NMOS tube MN1, and the grid of MN1 is connected with signal input Vin and electric capacity C1 respectively, the drain electrode of MN1 Meet the source electrode connecting resistance R1 of VDD, MN1, the other end of resistance R1 respectively with the other end, output end vo ut and the electric current of electric capacity C1 Source I_SS1 connects；The Substrate ground of MN1.

The low speed signal amplitude detection method of a kind of transmitted in both directions the most according to claim 1, it is characterised in that: described First low pass comparator and the second low pass comparator all include NMOS tube MN2, MN3 and PMOS MP2 and MP3；MP2's and MP3 Source electrode connects the grid docking of VDD, MP2 and MP3, and the drain electrode of MP2 is respectively with the drain electrode of resistance R2, load capacitance CL1 and MN2 even Connecing, the drain electrode of MP3 drain electrode with resistance R3, load capacitance CL2 and MN3 respectively is connected, and the other end of resistance R2 is with resistance R3's The other end connects, and the other end of resistance R2 and the other end of resistance R3 are all connected with the grid points of common connection of MP2 and MP3, negative Carrying the other end and the equal ground connection of the CL1 other end of electric capacity CL2, the grid of MN2 connects input voltage vin p, the source electrode of MN2 and current source I_ss2 connect, and the grid of MN3 connects input voltage vin n, the source electrode of MN3 and current source I_ss2 connect, current source I_ssAnother termination of 2 Ground；The drain electrode of MN2 is also connected with output end vo utn, and the drain electrode of MN3 is also connected with output end vo utp.

The low speed signal amplitude detection method of a kind of transmitted in both directions the most according to claim 1, it is characterised in that: described Amplitude square comparator includes NMOS tube MN4, MN5, MN6, MN7 and PMOS MP4, MP5；The source electrode of MP4 and the source electrode of MP5 connect The grid of VDD, MP4 and the grid docking of MP5, the drain electrode of MP4 is connected with resistance R4, and the drain electrode of MP5 is connected with resistance R5, resistance The other end of R4 is connected with the other end of resistance R5, the other end of resistance R4 and the other end of resistance R5 all with the grid of MP4 and MP5 Pole points of common connection connects；The grid of MN4 and the positive output end of the second low pass comparator connect, the grid of MN5 and the second low pass The negative output terminal of comparator connects, and the drain electrode of MN4 is connected with the drain electrode of MP4 after the drain electrode docking of MN5, the source electrode of MN4 and MN5 Source electrode docking after with current source I_SS3 connect；The grid of MN6 and the positive output end of the first low pass comparator connect, the grid of MN7 Being connected with the negative output terminal of the first low pass comparator, the drain electrode of MN6 is connected with the drain electrode of MP5 after the drain electrode docking of MN7, MN6 Source electrode dock with the source electrode of MN7 after with current source I_SS3 connect；Current source I_SSThe other end ground connection of 3；The drain electrode of MN4 and MN5 Points of common connection is connected with voltage output end Voutn, and the drain electrode points of common connection of MN6 and MN7 is with voltage output end Voutp even Connect.

The low speed signal amplitude detection method of a kind of transmitted in both directions the most according to claim 1, it is characterised in that: described Difference turns single-ended comparators and includes NMOS tube MN8, MN9, MN10, MN11 and PMOS MP6, MP7, MP8, MP9；MP6、MP7、 The source electrode of MP8, MP9 is all connected with VDD, the docking of the grid of MP6 and MP7, the drain electrode of MP6 respectively with the drain electrode of resistance R6 and MN8 Connecting, the drain electrode of MP7 drain electrode with resistance R7 and MN9 respectively is connected, and the other end of resistance R6 is connected with the other end of resistance R7, The other end of resistance R6 and the other end of resistance R7 are all connected with the grid points of common connection of MP6 and MP7, the grid of MN8 and width The positive output end of degree square comparator connects, the source electrode of MN8 and current source I_ss4 connect, the grid of MN9 and amplitude square comparator Negative output terminal connect, the source electrode of MN9 and current source I_ss4 connect, current source I_ssThe other end ground connection of 4；The drain electrode of MN2 also with The grid of MP8 connects, and the drain electrode of MP7 is also connected with the grid of MP9, and the drain electrode of MP8 is connected with the drain electrode of MN11, the grid of MN11 Being connected with the grid of MN10, the grid points of common connection of MN11 with MN10 is connected with the drain electrode of MN11, the source electrode of MN11 and MN10 Source grounding, the drain electrode of MN10 is connected with drain electrode and the output end vo ut of MP9 respectively.