CN113098481B

CN113098481B - High-performance high-speed input buffer circuit

Info

Publication number: CN113098481B
Application number: CN202110366683.2A
Authority: CN
Inventors: 马锡昆; 谢宜政
Original assignee: CETC 58 Research Institute; Wuxi Zhongwei Yixin Co Ltd
Current assignee: CETC 58 Research Institute; Wuxi Zhongwei Yixin Co Ltd
Priority date: 2021-04-06
Filing date: 2021-04-06
Publication date: 2021-12-17
Anticipated expiration: 2041-04-06
Also published as: CN113098481A

Abstract

The invention discloses a high-performance high-speed input buffer circuit, which relates to the technical field of circuits, and is characterized in that an output clamping circuit is arranged at the differential output end of each differential module, signals output by the differential output ends of two differential modules are subjected to cross coupling through a cross coupling circuit and then output to a post-stage circuit to form a pair of differential output signals, the output clamping circuit can enable the output to be rapidly turned over, the bandwidth is improved, the output common-mode voltage is stabilized, and the cross coupling circuit improves the gain, so that the high-speed input buffer circuit meets the dual requirements of the bandwidth and the gain.

Description

High-performance high-speed input buffer circuit

Technical Field

The invention relates to the technical field of circuits, in particular to a high-performance high-speed input buffer circuit.

Background

When signals are input from the outside of the chip, the signals need to be received through an input buffer circuit, and the signal level is converted into the voltage domain level inside the chip, so that the signals can be further processed. When designing an input buffer circuit, the following aspects are mainly considered:

1. the input signal level standards, such as common mode level VCM and differential mode level VID, different level standards often define different VCM and VID ranges, and if the input buffer circuit needs to be compatible with multiple level standards, such as LVDS/DDR/MIPI applications, the possible VCM is 0.07V-1.8V, and the VID is 0.07V-1.8V. On one hand, a circuit structure with a full-swing input is required to realize that the circuit can work normally under different VCM, and on the other hand, in order to be compatible with different VID ranges, it is generally required to consider that when the VID is minimum, the circuit can amplify a signal so as to convert the signal into a full-swing output.

2. The speed of the input signal, or the bandwidth of the signal. On one hand, as the bandwidth of an input signal is increased, the signal attenuation is caused by the fact that the input signal passes through the chip external package, the wiring and the like, the problem that the signal bandwidth reaches the input buffer circuit and the intersymbol interference is caused is solved, the eye diagram of the received signal is deteriorated, and how to compensate the attenuation of the signal is the content which needs to be processed by the input buffer circuit at a high speed. On the other hand, in order to transmit the signal smoothly, the bandwidth of the input buffer circuit itself needs to be larger than the signal bandwidth, otherwise, signal attenuation will also be caused.

Referring to fig. 1, a folded cascode structure is adopted to amplify signals, VIP and VIN are a pair of P-type and N-type differential input pairs to ensure that the circuit can receive different input levels, VB1, VB2, VB3 and VB4 are locally generated external bias voltages, and as the speed increases, different level standards tend to use smaller VIDs for transmission, which puts dual requirements on bandwidth and gain on the input buffer circuit: the input of the small VID requires a certain gain of a circuit to amplify the signal; the speed is increased, and the bandwidth of the circuit is required to be increased. The input buffer circuit of the prior art configuration shown in fig. 1 has difficulty meeting this requirement.

Disclosure of Invention

The present inventors have proposed a high-performance high-speed input buffer circuit in order to solve the above-mentioned problems and technical needs, and the technical solution of the present invention is as follows:

a high-speed input buffer circuit with high performance comprises a first differential module, a second differential module and a cross-coupling circuit, wherein the first differential module and the second differential module are identical in structure, each differential module comprises a first differential amplification circuit, a second differential amplification circuit and an output module, the first differential amplification circuit is connected with an analog power supply, two output ends of the first differential amplification circuit are connected to the output module, the second differential amplification circuit is connected with an analog ground, two output ends of the second differential amplification circuit are connected to the output module, and a pair of differential input signals with opposite polarities are input into the identical circuit structures of the two differential amplification circuits in the two differential modules in an opposite polarity mode;

each differential module also comprises an output clamping circuit, the output clamping circuit is connected between the internal offset end of the differential module and the differential output end of the differential module, and when the differential output end is pulled high, the output clamping circuit generates high-level clamping of current flowing from the differential output end to the internal offset end on the differential output end; when the differential output end is pulled down, the output clamping circuit generates a current flowing from the internal bias end to the differential output end to clamp the low level of the differential output end;

signals output by the differential output ends of the two differential modules are subjected to cross coupling through the cross coupling circuit and then output a pair of differential output signals to the rear-stage circuit.

The further technical scheme is that the output module in each differential module comprises a bias generation circuit and an output circuit, wherein the bias generation circuit leads out an internal bias end of the differential module and outputs bias voltage to other bias current tubes in the differential module through the internal bias end.

The further technical scheme is that in each differential module:

the bias generating circuit comprises a seventh PMOS tube and a seventh NMOS tube, a drain electrode and a grid electrode of the seventh PMOS tube and a drain electrode and a grid electrode of the seventh NMOS tube are connected with each other and led out to serve as an internal bias end of the differential module to output bias voltage, a source electrode of the seventh PMOS tube is connected with an analog power supply through a fifth PMOS tube controlled by the bias voltage, and a source electrode of the seventh NMOS tube is connected with an analog ground through a fifth NMOS tube controlled by the bias voltage;

the output circuit comprises an upper buffer module and a lower buffer module which are connected in series between an analog power supply and an analog ground, the common end of the two modules is used as a differential output end, the current change direction of the upper buffer module is opposite to the change direction of the bias voltage, and the current change direction of the lower buffer module is the same as the change direction of the bias voltage;

the first output end of the first differential amplification circuit is connected with the common ends of the seventh NMOS transistor and the fifth NMOS transistor, the second output end of the first differential amplification circuit is connected with the lower buffer module, the first output end of the second differential amplification circuit is connected with the common ends of the seventh PMOS transistor and the fifth PMOS transistor, and the second output end of the second differential amplification circuit is connected with the upper buffer module;

when the input pair of differential input signals are not equal, the dynamic adjustment processes of the two differential modules are opposite, and for any one of the differential modules: the first output end of a second differential amplifying circuit in the differential module is pulled down, so that the generated bias voltage is reduced, the current of the upper buffer module is increased, the second output end of the first differential amplifying circuit is pulled up to limit the conduction of the lower buffer module, and the differential output end is pulled up; or the first output end of the first differential amplifying circuit in the differential module is pulled high, so that the generated bias voltage is increased, the current of the lower buffer module is increased, the first output end of the second differential amplifying circuit is pulled low, the upper buffer module is limited to be conducted, and the differential output end is pulled low.

The further technical scheme is that the output clamping circuit comprises resistors, and the two ends of each resistor are respectively connected with the internal offset end and the differential output end.

The output clamping circuit comprises an eleventh NMOS tube and an eleventh PMOS tube which form a transmission gate structure, wherein the source electrode of the eleventh NMOS tube is connected with the drain electrode of the eleventh PMOS tube and is connected with an internal offset end, the drain electrode of the eleventh NMOS tube is connected with the source electrode of the eleventh PMOS tube and is connected with a differential output end, and the grid electrodes of the eleventh NMOS tube and the eleventh PMOS tube are respectively controlled by a pair of control signals with opposite polarities.

The grid electrode of an eleventh NMOS tube is connected with an analog power supply, and the grid electrode of an eleventh PMOS tube is connected with an analog ground;

or the grid electrode of the eleventh NMOS tube is connected with the first output end of the second differential amplification circuit, the grid electrode of the eleventh PMOS tube is connected with the first output end of the first differential amplification circuit, and the output polarities of the first output end of the first differential amplification circuit and the first output end of the second differential amplification circuit are opposite.

The output clamping circuit comprises an eleventh NMOS tube and an eleventh PMOS tube, wherein a source electrode and a grid electrode of the eleventh NMOS tube and a drain electrode and a grid electrode of the eleventh PMOS tube are connected with each other and are connected with an internal bias end, and a drain electrode of the eleventh NMOS tube and a source electrode of the eleventh PMOS tube are connected with each other and are connected with a differential output end.

The cross coupling circuit comprises a first branch and a second branch which have the same circuit structure, in each branch, the source electrode of a ninth PMOS tube is connected with an analog power supply, the drain electrode of the ninth PMOS tube is connected with the source electrode of a tenth PMOS tube, the drain electrode of the tenth PMOS tube is connected with the drain electrode of a tenth NMOS tube and serves as the output end of the branch, the source electrode of the tenth NMOS tube is connected with the drain electrode of the ninth NMOS tube, the source electrode of the ninth NMOS tube is connected with an analog ground, the grid electrodes of the tenth PMOS tube and the tenth NMOS tube are connected and serve as the input ends of the branches, and the grid electrodes of the ninth PMOS tube and the ninth NMOS tube are respectively controlled by bias voltage in a differential module connected with the input ends of the branches;

the input end of the first branch circuit is connected with the differential output end of the first differential module, the output end of the first branch circuit is connected with the input end of the second branch circuit, the input end of the second branch circuit is connected with the differential output end of the second differential module, the output end of the second branch circuit is connected with the input end of the first branch circuit, and the first branch circuit and the second branch circuit output a pair of differential output signals to the rear-stage circuit through respective output ends.

In each branch, the common end of the ninth PMOS transistor and the tenth PMOS transistor of the branch is connected to the second output end of the second differential amplifying circuit in the differential module to which the input end of the branch is connected, and the common end of the ninth NMOS transistor and the tenth NMOS transistor of the branch is connected to the second output end of the first differential amplifying circuit in the differential module to which the input end of the branch is connected.

The further technical scheme is that high-frequency compensation circuits are respectively arranged in the first differential amplification circuit and the second differential amplification circuit, and each high-frequency compensation circuit comprises a resistor and a capacitor which are connected in parallel:

in the first differential amplification circuit, the source electrodes of a first PMOS tube and a second PMOS tube are connected and connected with an analog power supply, the drain electrode of the first PMOS tube is connected with the source electrode of a third PMOS tube, the drain electrode of the third PMOS tube is used as the first output end of the first differential amplification circuit, the drain electrode of the second PMOS tube is connected with the source electrode of a fourth PMOS tube, the drain electrode of the fourth PMOS tube is used as the second output end of the first differential amplification circuit, one end of a built-in high-frequency compensation circuit is connected with the drain electrode of the first PMOS tube, and the other end of the built-in high-frequency compensation circuit is connected with the drain electrode of the second PMOS tube;

in the second differential amplification circuit, the source electrodes of a first NMOS tube and a second NMOS tube are connected with each other and are connected with an analog ground, the drain electrode of the first NMOS tube is connected with the source electrode of a third NMOS tube, the drain electrode of the third NMOS tube is used as the first output end of the second differential amplification circuit, the drain electrode of the second NMOS tube is connected with the source electrode of a fourth NMOS tube, the drain electrode of the fourth NMOS tube is used as the second output end of the second differential amplification circuit, one end of a built-in high-frequency compensation circuit is connected with the drain electrode of the first NMOS tube, and the other end of the built-in high-frequency compensation circuit is connected with the drain electrode of the second NMOS tube;

the grid electrodes of the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube are all controlled by bias voltage in the differential module, a pair of differential input signals with opposite polarities are respectively input into the grid electrodes of the third PMOS tube and the fourth PMOS tube, and simultaneously are respectively input into the grid electrodes of the third NMOS tube and the fourth NMOS tube; the polarities of differential input signals input by the grid electrodes of the third PMOS tube and the third NMOS tube in the same differential module are the same, and the polarities of differential input signals input by the grid electrodes of the third PMOS tube in different differential modules are different.

The beneficial technical effects of the invention are as follows:

the application discloses high-speed input buffer circuit of high performance, this high-speed input buffer circuit is inside to set up output clamp circuit and cross-coupling circuit, and output clamp circuit can make the output overturn fast, improves the bandwidth, stabilizes the common mode voltage of output simultaneously, and cross-coupling circuit improves the gain for high-speed input buffer circuit satisfies the dual requirement of bandwidth and gain.

In addition, the high-speed input buffer circuit is internally provided with a bias generating circuit, and the generated bias voltage is dynamically adjusted along with the input signal, so that extra chip area and routing resources are not required to be consumed, and the output signal turning speed is improved. In addition, a high-frequency compensation circuit can be arranged in the high-speed input buffer circuit to compensate the high-frequency attenuation of signals, so that the performance of the high-speed input buffer circuit is further optimized.

Drawings

Fig. 1 is a partial circuit configuration diagram of a conventional input buffer circuit.

FIG. 2 is a circuit diagram of one embodiment of a high speed input buffer circuit of the present application.

FIG. 3 is a circuit diagram of another embodiment of a high-speed input buffer circuit of the present application.

Fig. 4 is a circuit configuration diagram of the first difference module in fig. 3.

Fig. 5 is a circuit diagram of an implementation of the output clamp circuit based on fig. 4.

Fig. 6 is a circuit diagram of another implementation of the output clamp circuit based on fig. 4.

Fig. 7 is a circuit diagram of yet another implementation of the output clamp circuit based on fig. 4.

Fig. 8 is a circuit diagram of a cross-coupling circuit in the high-speed input buffer circuit of the present application.

Fig. 9 is a circuit diagram of the first difference module with a high frequency compensation circuit provided on the basis of fig. 4.

FIG. 10 is a circuit diagram of yet another embodiment of a high speed input buffer circuit of the present application.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application discloses high-speed input buffer circuit of high performance, please refer to fig. 2, this high-speed input buffer circuit includes first difference module, second difference module and cross-coupling circuit, first difference module and second difference module's structure is the same, every difference module includes first difference amplifier circuit, second difference amplifier circuit and output module respectively, wherein first difference amplifier circuit connects analog power supply VCCA and two output terminals V1A and V2A are connected to the output module, second difference amplifier circuit connects analog ground VSSA and two output terminals V3A and V4A are connected to the output module. A pair of differential input signals VIN and VIP with opposite polarities are input to the same circuit structure of two differential amplification circuits in two differential modules in an opposite polarity manner, and the two differential modules output a pair of differential output signals to a subsequent circuit through respective differential output terminals VOP and VON.

Each differential module further includes an output Clamp circuit (Clamp Cell) connected between an internal bias VA of the differential module and a differential output terminal of the differential module, and fig. 2 is a circuit diagram of the first differential amplifier circuit, the second differential amplifier circuit and the output module based on the conventional structure shown in fig. 1, where the internal bias VA of the differential module is a common terminal of PN7A and MN 7A. When the differential output end is pulled high, the output clamping circuit generates a current flowing from the differential output end to the internal bias end to clamp the high level of the differential output end; when the differential output end is pulled down, the output clamping circuit generates a low level clamping of the current flowing from the internal bias end to the differential output end. Clamping the high and low levels of the VOP means that the VOP can be charged to the high level more quickly or discharged to the low level more quickly, i.e. this increases the circuit bandwidth. Signals output by the differential output ends VOP and VON of the two differential modules are cross-coupled through a cross-coupling circuit and then output a pair of differential output signals to a rear-stage circuit. The cross-coupling circuit can improve the gain of the input buffer circuit through the coupling effect between the VOP/VON. Therefore, the dual requirements of bandwidth and gain can be met simultaneously through the output clamping circuit and the cross coupling circuit.

In the present application, further, the circuit structure of each differential module does not adopt the conventional structure shown in fig. 1, and particularly, the circuit structure of the output module in the differential module is different from the conventional circuit shown in fig. 1, the main difference is that the differential module of the present application has a bias generation circuit built therein, and the circuit diagram of the high-speed input buffer circuit refers to fig. 3. The output module in each differential module comprises a bias generation circuit and an output circuit, wherein the bias generation circuit leads out an internal bias end VA of the differential module and outputs bias voltage to other bias current tubes in the differential module through the internal bias end VA, so that external bias voltage does not need to be generated locally, extra chip area and routing resources do not need to be consumed, and for convenience of representation, the bias voltage generated by the internal bias end VA is also represented by VA in the application.

Taking the first differential module as an example, referring to fig. 4, the circuit structure of the output module in each differential module is:

the bias generating circuit comprises a seventh PMOS tube P7A and a seventh NMOS tube N7A which are connected in a diode connection mode, the drain electrode and the grid electrode of the P7A are connected with the drain electrode and the grid electrode of the N7A, and the grid electrode of the seventh PMOS tube P7A serves as a bias end to output an internal bias end VA in the differential module. The source electrode of the seventh PMOS transistor P7A is connected to the analog power supply VCCA through a fifth PMOS transistor P5A controlled by a bias voltage, and the source electrode of the seventh NMOS transistor N7A is connected to the analog ground VSSA through a fifth NMOS transistor N5A controlled by a bias voltage.

The output circuit comprises an upper buffer module and a lower buffer module which are connected in series between an analog power supply VCCA and an analog ground VSSA, the common end of the two modules is used as a differential output end VOP, the current change direction of the upper buffer module is opposite to the change direction of bias voltage, the current change direction of the lower buffer module is the same as the change direction of the bias voltage, namely, when the bias voltage is increased, the current of the lower buffer module is increased, and when the bias voltage is decreased, the current of the upper buffer module is increased. In the application, the upper buffer module comprises a sixth PMOS transistor P6A and an eighth PMOS transistor P8A, the source of P6A is connected to VCCA, the drain is connected to the source of P8A, the drain of P8A is connected to the lower buffer module and serves as VOP, and the gates of P6A and P8A are controlled by bias voltage. The lower buffer module comprises a sixth NMOS transistor N6A and an eighth NMOS transistor N8A, the source of N6A is connected with VSSA, the drain is connected with the source of N8A, the drain of N8A is used for connecting the upper buffer module and is used as VOP, and the gates of N6A and N8A are controlled by bias voltage.

The first output terminal V3A of the first differential amplifier circuit is connected to the common terminal of the seventh NMOS transistor N7A and the fifth NMOS transistor N5A, and the second output terminal V4A is connected to the lower buffer module. The first output end V1A of the second differential amplifying circuit is connected with the common end of the seventh PMOS tube P7A and the fifth PMOS tube P5A, and the second output end V2A is connected with the upper buffer module. In the present application, the second output terminal V4A of the first differential amplifier circuit is specifically connected to the source of N8A when connected to the lower buffer module, and the second output terminal V2A of the second differential amplifier circuit is specifically connected to the source of P8A when connected to the upper buffer module.

As shown in fig. 4, in the first differential amplifier circuit, sources of a first PMOS transistor P1A and a second PMOS transistor P2A are connected to each other and to an analog power supply VCCA, a drain of P1A is connected to a source of a third PMOS transistor P3A, a drain of P3A is used as a first output terminal V3A of the first differential amplifier circuit, a drain of P2A is connected to a source of a fourth PMOS transistor P4A, and a drain of the fourth PMOS transistor P4A is used as a second output terminal V4A of the first differential amplifier circuit. In the second differential amplifier circuit, the sources of the first NMOS transistor N1A and the second NMOS transistor N2A are connected to the analog ground VSSA, the drain of N1A is connected to the source of the third NMOS transistor N3A, the drain of N3A serves as the first output terminal V1A of the second differential amplifier circuit, the drain of N2A is connected to the source of the fourth NMOS transistor N4A, and the drain of N4A serves as the second output terminal V2A of the second differential amplifier circuit.

Referring to fig. 3, the circuit structures of the two differential modules are the same, and in the present application, the same circuit structure of the two differential modules is distinguished by suffixes a and B of the device numbers, for example, P1A represents the first PMOS transistor in the first differential module, and P1B represents the first PMOS transistor in the second differential module, and so on, the circuit connection manner of the second differential module is the same as that of the first differential module, and the description thereof is omitted. The gates of the first PMOS transistor P1A, the second PMOS transistor P2A, the first NMOS transistor M1A and the second NMOS transistor N2A are all controlled by the bias voltage in the differential module, VA in the first differential module, and VB in the first differential module. A pair of differential input signals VIP and VIN with opposite polarities are respectively input to the gates of the third PMOS transistor P3A and the fourth PMOS transistor P4A, and are simultaneously respectively input to the gates of the third NMOS transistor N3A and the fourth NMOS transistor N4A. The polarities of the differential input signals input to the gates of the third PMOS transistor P3A and the third NMOS transistor N3A in the same differential module are the same, and the polarities of the differential input signals input to the gates of the third PMOS transistor P3A in different differential modules are different, for example, in fig. 3, the polarities of the input VIPs to the gates of P3A and N3A in the first differential module are the same, and the polarities of the input VIN to the gates of P3B and N3B in the second differential module are the same, but the polarities of the input signals to the gates of P3A and P3B are opposite.

Compared with the structure of the conventional differential module shown in fig. 2, the structure of the differential module shown in fig. 3 has the advantages that the bias generating circuit inside the differential module generates the bias voltage to be provided to other bias current pipes, and the bias voltage does not need to be generated locally, so that additional chip area and routing resources do not need to be consumed. And the bias voltage generated by the bias generation circuit in this application is dynamically changed during operation, and this application defines the bias voltage VA as VA _ DC when two differential input signals are equal to each other, i.e., VIP ═ VIN ═ VCM (common mode level). When a pair of input differential signals are not equal, the dynamic adjustment processes of the two differential modules are opposite, and any one of the two differential modules has the following adjustment process, and the first differential module in the structure shown in fig. 3 is taken as an example in the application:

(1) when VIP > VIN, N3A and P4A will be strongly turned on, N4A and P3A will be weakly turned on, the first output terminal V1A of the second differential amplifier circuit in the first differential module is pulled low, so that the current of P5A will flow to N3A more, and P7A will have less current, so that the generated bias voltage VA decreases, when VA decreases, the current of the upper buffer module increases, specifically the current of P6A increases, and the second output terminal V4A of the first differential amplifier circuit is pulled high to limit the lower buffer module to be turned on, specifically to limit N8A to be turned on, so that the differential output terminal VOP of the first differential module is pulled high. In the above adjustment process, the bias voltage VA does not decrease too much, because as the bias voltage VA decreases, the P5A current increases tending to pull the bias voltage VA high, so that the bias voltage VA dynamically varies in a certain range around VA _ DC.

In the second differential module, N3B and P4B are turned on weakly, and N4B and P3B are turned on strongly, which is similar to the adjustment process of the first differential module when VIP < VIN as follows, and the details are not repeated herein.

(2) When VIP < VIN, N3A and P4A will be turned on weakly, N4A and P3A will be turned on strongly, and the first output terminal V3A of the first differential amplifying circuit in the first differential module is pulled high, so that the current of N5A will come from P3A more, and therefore the level of V3A is raised, so that the generated bias voltage VA is raised. When the bias voltage VA rises, the current of the lower buffer module increases, specifically the current of N6A increases, and the first output terminal V1A of the second differential amplifier circuit is pulled down to limit the conduction of the upper buffer module, specifically the conduction of the P8A, so that the differential output terminal VOP of the first differential module is pulled down. During the adjustment process, the bias voltage VA does not increase too much, because the increase of the N5A current tends to pull the bias voltage VA low as the bias voltage VA increases.

In the second differential module, N3B and P4B are turned on strongly, and N4B and P3B are turned on weakly, which is similar to the adjustment process of the first differential module when VIP > VIN, and the details are not repeated herein.

Therefore, based on the circuit structure disclosed by the application, an additional bias circuit is not needed, in the data transmission process, the bias voltage generated by the first differential module dynamically changes around the VA _ DC within a certain range, the second differential module is similar, and the structure is favorable for the level inversion of the differential output ends of the two differential modules. The working process of the output module and the output clamping circuit with the structure is matched as follows:

when VIP is VIN, VOP is VA according to the symmetry of the circuit, and the output clamping circuit has no current. When the difference output end VOP is pulled high, namely when VIP is greater than VIN for the first difference module, along with the pulling high of VOP, the output clamping circuit generates a current flowing from the difference output end VOP to the offset end VA, so that the pulling high degree of VOP is limited, the final high level of VOP becomes smaller than that when no output clamping circuit is added, namely high level clamping is performed on the difference output end. When the differential output end VON is pulled down, the output clamping circuit generates current flowing to the differential output end VOP from the bias end VA, the pulling-down degree of the VOP is limited, the final low level of the VOP is enlarged relative to the situation without the output clamping circuit, and the low level of the differential output end is clamped. The output clamping circuit is added, the average value of the bias voltage VA is used as VA _ DC, the characteristic of dynamic change is utilized, the output swing amplitude of the VOP is limited, and the overturning speed of the VOP can be accelerated. Additionally clamping the high and low levels of the VOP means that the VOP can be charged to the high level faster or discharged to the low level faster, i.e. this increases the circuit bandwidth. In addition, the output clamp circuit also enables the common-mode voltage of the VOP to stably follow the bias voltage VA, and compared with a structure without the output clamp circuit, the common-mode change is smaller, so that the processing of a post-stage circuit is facilitated.

Regardless of the structure shown in fig. 2 or fig. 3, the output clamp circuit in the present application has various implementations:

(1) the output clamping circuit comprises resistors, two ends of which are respectively connected with the offset end VA and the differential output end VOP.

(2) The output clamping circuit comprises an eleventh NMOS transistor N11A and an eleventh PMOS transistor P11A which form a transmission gate structure, wherein the source electrode of N11A is connected with the drain electrode of P11A and connected with an internal bias end VA, the drain electrode of N11A is connected with the source electrode of P11A and connected with a differential output end VOP, and the grid electrodes of N11A and P11A are respectively controlled by a pair of control signals with opposite polarities.

There are two specific ways of connection in this case: the gate of the eleventh NMOS transistor N11A is connected to the analog power source VCCA, and the gate of the eleventh PMOS transistor P11A is connected to the analog ground VSSA, as shown in fig. 5. Alternatively, the gate of the eleventh NMOS transistor N11A is connected to the first output terminal V1A of the second differential amplifier circuit, the gate of the eleventh PMOS transistor P11A is connected to the first output terminal V3A of the first differential amplifier circuit, and the output polarities of the first output terminal V1A of the first differential amplifier circuit and the first output terminal V3A of the second differential amplifier circuit are opposite, as shown in fig. 6.

(3) The output clamp circuit comprises an eleventh NMOS transistor N11A and an eleventh PMOS transistor P11A, wherein the source and the gate of the eleventh NMOS transistor N11A are connected to the drain and the gate of the eleventh PMOS transistor P11A and to the internal bias terminal VA, and the drain of the eleventh NMOS transistor N11A is connected to the source of the eleventh PMOS transistor P11A and to the differential output terminal VOP, as shown in fig. 7.

Regardless of the structure shown in fig. 2 or fig. 3, the structure of the cross-coupled circuit in the present application is as shown in fig. 8, the cross-coupled circuit includes a first branch X4A and a second branch X4B having the same circuit structure, in each branch, taking the first branch X4A as an example, the source of the ninth PMOS transistor P9A is connected to the analog power VCCA, the drain is connected to the source of the tenth PMOS transistor P10A, and the drain of the tenth PMOS transistor P10A is connected to the drain of the tenth NMOS transistor N10A and serves as the output terminal of the branch. The source of the tenth NMOS transistor N10A is connected to the drain of the ninth NMOS transistor N9A, the source of the ninth NMOS transistor N9A is connected to the analog ground VSSA, and the gates of the tenth PMOS transistor P10A and the tenth NMOS transistor N10A are connected to serve as the input terminal of the branch circuit and connected to the differential output terminal of the corresponding differential module. The gates of the ninth PMOS transistor P9A and the ninth NMOS transistor N9A are respectively controlled by the bias voltage in the differential module connected to the input terminals of the branches, P9A and N9A in the first branch X4A are controlled by the bias voltage VA of the first differential module, and P9B and N9B in the second branch X4B are controlled by the bias voltage VB of the second differential module. The input end of the first branch X4A is connected with the differential output end VOP of the first differential module, the output end is connected with the input end of the second branch X4B, the input end of the second branch X4B is connected with the differential output end VON of the second differential module, the output end is connected with the input end of the first branch X4A, and the first branch X4A and the second branch X4B output a pair of differential output signals to a rear-stage circuit through respective output ends.

Taking fig. 3 as an example, the operation process of the cross-coupled circuit is as follows: when VIP is larger than VIN, VOP is turned to high level, VON is turned to low level, when VOP starts to turn to high level, N10A is conducted strongly, so that VON is discharged by the N9A/N10A branch circuit, VON is pulled down more quickly, P10B is conducted strongly after VON is pulled down, and then VOP is charged by the P9B/P10B branch circuit, so that VOP is pulled up more quickly. When VIP < VIN, VOP is turned to low, VON is turned to high, when VOP starts to turn to low, P10A is conducted strongly, so that the P9A/P10A branch charges VON to enable VON to be pulled high more quickly, N10B is conducted strongly after VON is pulled high, and N9B/N10B branch discharges VOP to enable VOP to be pulled low more quickly. The output gain is improved through the coupling effect between the VOP/VON.

Alternatively, as shown in fig. 8, in each branch, a common terminal of the ninth PMOS transistor P9A and the tenth PMOS transistor P10A of the branch is connected to the second output terminal of the second differential amplifying circuit in the differential module to which the input terminal of the branch is connected, and a common terminal of the ninth NMOS transistor N9A and the tenth NMOS transistor N10A of the branch is connected to the second output terminal of the first differential amplifying circuit in the differential module to which the input terminal of the branch is connected. Specifically, the common end of P9A and P10A in the first branch X4A is connected to V2A, the common end of N10A and N9A is connected to V4A, the common end of P9B and P10B in the second branch X4B is connected to V2B, and the common end of N10B and N9B is connected to V4B. This structure may limit the output swing of the cross-coupled circuit.

Further, in the differential module of the present application, not only the circuit structure of the output module is different from the conventional circuit, but also the circuit structure of the two differential amplifier circuits is different from the conventional circuit, taking the first differential module as an example, on the basis of fig. 4, the circuit structure may be further improved as shown in fig. 9, wherein the first differential amplifier circuit and the second differential amplifier circuit are respectively provided with a high frequency compensation circuit, each high frequency compensation circuit includes a resistor R and a capacitor C connected in parallel, taking the first differential module as an example, one end of the high frequency compensation circuit provided in the first differential amplifier circuit is connected to the drain of the first PMOS transistor P1A, the other end is connected to the drain of the second PMOS transistor P2A, one end of the high frequency compensation circuit provided in the second differential amplifier circuit is connected to the drain of the first NMOS transistor N1A, and the other end is connected to the drain of the second NMOS transistor N2A. The high frequency compensation circuit may achieve signal Equalization (Equalization), for example, for low frequency components of the differential input signal, the sources of the differential input pair P3A and P4A are connected by a resistor R in the high frequency compensation circuit, so that the equivalent transconductance gm of the differential input pair is reduced to about 1/R; for the high-frequency component of the differential input signal, the sources of the differential input pair P3A and P4A are connected through a capacitor C in the high-frequency compensation circuit, so that the equivalent transconductance gm of the differential input pair is not influenced, and the low-frequency influence is reduced, so that the compensation for the high-frequency component of the signal is realized. The high-speed input buffer circuit of the present application is actually implemented as shown in fig. 10.

What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims

1. A high-performance high-speed input buffer circuit is characterized in that the high-speed input buffer circuit comprises a first differential module, a second differential module and a cross-coupling circuit, the first differential module and the second differential module are identical in structure, each differential module comprises a first differential amplification circuit, a second differential amplification circuit and an output module, the first differential amplification circuit is connected with an analog power supply, two output ends of the first differential amplification circuit are connected to the output module, the second differential amplification circuit is connected with an analog ground, two output ends of the second differential amplification circuit are connected to the output module, and a pair of differential input signals with opposite polarities are input into the same circuit structure of two differential amplification circuits in the two differential modules in an opposite polarity mode;

each differential module further comprises an output clamping circuit, the output clamping circuit is connected between an internal bias end of the differential module and a differential output end of the differential module, and when the differential output end is pulled high, the output clamping circuit generates high-level clamping on the differential output end by current flowing from the differential output end to the internal bias end; when the differential output end is pulled down, the output clamping circuit generates a low-level clamping of the current flowing from the internal bias end to the differential output end on the differential output end;

2. The cache input buffer circuit of claim 1, wherein the output module in each differential module comprises a bias generation circuit and an output circuit, the bias generation circuit being coupled to the internal bias terminal of the differential module and outputting a bias voltage through the internal bias terminal to be provided to other bias current pipes inside the differential module.

3. The high-speed input buffer circuit according to claim 2, wherein in each differential module:

the bias generating circuit comprises a seventh PMOS tube and a seventh NMOS tube, a drain electrode and a grid electrode of the seventh PMOS tube and a drain electrode and a grid electrode of the seventh NMOS tube are connected and led out to be used as an internal bias end of the differential module to output bias voltage, a source electrode of the seventh PMOS tube is connected with the analog power supply through a fifth PMOS tube controlled by the bias voltage, and a source electrode of the seventh NMOS tube is connected with the analog ground through a fifth NMOS tube controlled by the bias voltage;

the output circuit comprises an upper buffer module and a lower buffer module which are connected in series between the analog power supply and the analog ground, the common end of the two modules is used as a differential output end, the current change direction of the upper buffer module is opposite to the change direction of the bias voltage, and the current change direction of the lower buffer module is the same as the change direction of the bias voltage;

a first output end of the first differential amplification circuit is connected with a common end of the seventh NMOS transistor and the fifth NMOS transistor, a second output end of the first differential amplification circuit is connected with the lower buffer module, a first output end of the second differential amplification circuit is connected with a common end of the seventh PMOS transistor and the fifth PMOS transistor, and a second output end of the second differential amplification circuit is connected with the upper buffer module;

when the input pair of differential input signals are not equal, the dynamic adjustment processes of the two differential modules are opposite, and for any one of the differential modules: a first output end of a second differential amplifying circuit in the differential module is pulled down, so that the generated bias voltage is reduced, the current of the upper buffer module is increased, a second output end of the first differential amplifying circuit is pulled up to limit the conduction of the lower buffer module, and the differential output end is pulled up; or the first output end of the first differential amplifying circuit in the differential module is pulled high, so that the generated bias voltage is increased, the current of the lower buffer module is increased, the first output end of the second differential amplifying circuit is pulled low, so that the upper buffer module is limited to be conducted, and the differential output end is pulled low.

4. The cache input buffer circuit according to any of claims 1-3, wherein the output clamp circuit comprises a resistor connected across the internal bias terminal and the differential output terminal, respectively.

5. The high-speed input buffer circuit according to any one of claims 1 to 3, wherein the output clamp circuit comprises an eleventh NMOS transistor and an eleventh PMOS transistor forming a transmission gate structure, a source of the eleventh NMOS transistor is connected to a drain of the eleventh PMOS transistor and connected to the internal bias terminal, a drain of the eleventh NMOS transistor is connected to a source of the eleventh PMOS transistor and connected to the differential output terminal, and gates of the eleventh NMOS transistor and the eleventh PMOS transistor are controlled by a pair of control signals with opposite polarities, respectively.

6. The high-speed input buffer circuit according to claim 5,

the grid electrode of the eleventh NMOS tube is connected with the analog power supply, and the grid electrode of the eleventh PMOS tube is connected with the analog ground;

or the gate of the eleventh NMOS transistor is connected to the first output end of the second differential amplifier circuit, the gate of the eleventh PMOS transistor is connected to the first output end of the first differential amplifier circuit, and the output polarities of the first output end of the first differential amplifier circuit and the first output end of the second differential amplifier circuit are opposite.

7. The high-speed input buffer circuit according to any one of claims 1 to 3, wherein the output clamp circuit comprises an eleventh NMOS transistor and an eleventh PMOS transistor, a source and a gate of the eleventh NMOS transistor are connected to a drain and a gate of the eleventh PMOS transistor and connected to the internal bias terminal, and a drain of the eleventh NMOS transistor is connected to a source of the eleventh PMOS transistor and connected to the differential output terminal.

8. The high-speed input buffer circuit according to any one of claims 1 to 3, wherein the cross-coupling circuit comprises a first branch and a second branch having the same circuit structure, in each branch, a source of a ninth PMOS transistor is connected to the analog power supply, a drain of the ninth PMOS transistor is connected to a source of a tenth PMOS transistor, a drain of the tenth PMOS transistor is connected to a drain of a tenth NMOS transistor and serves as an output terminal of the branch, a source of the tenth NMOS transistor is connected to a drain of a ninth NMOS transistor, a source of the ninth NMOS transistor is connected to the analog ground, gates of the tenth PMOS transistor and the tenth NMOS transistor are connected and serve as input terminals of the branch, and gates of the ninth PMOS transistor and the ninth NMOS transistor are controlled by bias voltages in the differential module to which the input terminals of the branches are connected, respectively;

the input end of the first branch circuit is connected with the differential output end of the first differential module, the output end of the first branch circuit is connected with the input end of the second branch circuit, the input end of the second branch circuit is connected with the differential output end of the second differential module, the output end of the second branch circuit is connected with the input end of the first branch circuit, and the first branch circuit and the second branch circuit output a pair of differential output signals to a rear-stage circuit through respective output ends.

9. The high-speed input buffer circuit according to claim 8,

10. The high-speed input buffer circuit according to any one of claims 1 to 3, wherein high-frequency compensation circuits are built in the first differential amplifier circuit and the second differential amplifier circuit, respectively, each high-frequency compensation circuit comprising a resistor and a capacitor connected in parallel:

in the first differential amplification circuit, the source electrodes of a first PMOS tube and a second PMOS tube are connected and connected with the analog power supply, the drain electrode of the first PMOS tube is connected with the source electrode of a third PMOS tube, the drain electrode of the third PMOS tube is used as the first output end of the first differential amplification circuit, the drain electrode of the second PMOS tube is connected with the source electrode of a fourth PMOS tube, the drain electrode of the fourth PMOS tube is used as the second output end of the first differential amplification circuit, one end of a built-in high-frequency compensation circuit is connected with the drain electrode of the first PMOS tube, and the other end of the built-in high-frequency compensation circuit is connected with the drain electrode of the second PMOS tube;

in the second differential amplification circuit, the source electrodes of a first NMOS tube and a second NMOS tube are connected with the analog ground, the drain electrode of the first NMOS tube is connected with the source electrode of a third NMOS tube, the drain electrode of the third NMOS tube is used as the first output end of the second differential amplification circuit, the drain electrode of the second NMOS tube is connected with the source electrode of a fourth NMOS tube, the drain electrode of the fourth NMOS tube is used as the second output end of the second differential amplification circuit, one end of a built-in high-frequency compensation circuit is connected with the drain electrode of the first NMOS tube, and the other end of the built-in high-frequency compensation circuit is connected with the drain electrode of the second NMOS tube;