KR100864898B1 - CMOS variable gain amplifier - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS variable gain amplifier, wherein a differential input voltage signal is differentially input to a cascode input terminal, and the transconductance is adjusted according to a gain control voltage signal which is the cascode common gate voltage. A variable transconductance conversion unit generated; A load resistance stage configured to output an output current of the variable transconductance converter to a differential output voltage using a resistive load or an active load; A breeding current generating unit supplying a breeding current to the variable transconductance converting unit in parallel with the load resistance stage; An output DC voltage comparator which detects the DC voltage value of the differential output voltage and compares the DC voltage value of the differential output voltage with a predetermined desired DC voltage value; Characterized in having a. According to the present invention, it is possible to provide a variable gain amplification function for an input signal having a wide range by an external regulated voltage signal at a low supply voltage, and high gain, low distortion, high linearity, wideband operation, and safe current bias type. It is possible to provide a variable gain amplifier having a.

Cascode, Bleeding Current, Load Resistance, Variable Gain Amplifier, Active Load

Description

CMOS variable gain amplifier

1 is a circuit diagram for explaining a conventional variable gain amplifier (VGA);

2 is a circuit diagram for explaining a variable gain amplifier according to a first embodiment of the present invention;

3 is a circuit diagram for explaining a variable gain amplifier according to a second embodiment of the present invention;

4 is a circuit diagram for explaining a variable gain amplifier according to a third embodiment of the present invention;

5 is a circuit diagram illustrating a variable gain amplifier according to a fourth embodiment of the present invention.

<Description of reference numbers for the main parts of the drawings>

100: variable transconductance conversion unit

210: resistance

220: bleeding current generating unit

230: output DC voltage comparator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifier, and more particularly to a CMOS variable gain amplifier for varying the gain to increase the operating area of the circuit.

In transmitting and receiving a signal, the magnitude of the signal varies greatly depending on the distance and state of the transmitter and the receiver. In particular, in the wireless system, the change of the signal becomes more severe by various kinds of parameters. In order to process such a highly variable signal, it must have a constant signal size. Therefore, when a large signal is input, the gain should be small, and when a small signal is input, the gain should be large. Thus, a variable gain amplifier (VGA) capable of adjusting the gain is required.

When designing a variable gain amplifier using a CMOS process, the main considerations are the frequency bandwidth for the desired application, the linearity to accept and process large input signals, the possibility of driving low voltages due to CMOS integration, the variable gain range, and the regulated voltage. And gain control characteristics.

In order to process a large amount of data at a high speed at a time, communication systems for short-range communication have emerged. Accordingly, a variable gain amplifier used in a multi-band system and a UWB system having a wide bandwidth must have a wideband characteristic. In order to integrate the variable gain amplifier with other parts, the variable gain amplifier must have low voltage characteristics and low power characteristics, and the circuit must be simplified to have a small size.

As CMOS processes have evolved, gate line widths have been reduced, resulting in the need for low voltage, low power circuits in integrated CMOS circuits. Therefore, there is a need for a variable gain amplifier having high gain and low distortion when using a low power supply.

1 is a circuit diagram illustrating a conventional variable gain amplifier (VGA). Referring to FIG. 1, the differential input signals V _{in +} and V _in− are input to the gates of the input transistors M1 and M2 to be converted into differential signals in the form of current. The differential current signal is converted into an output voltage differential signal V _out amplified by the load resistor R _L through transistors M3 and M4 located above the cascode. At this time, the gain control signal V _CTRL is applied to the gates of the upper transistors M3 and M4, and the variable gain is obtained by adjusting the transconductance of the entire circuit by the gain control signal V _CTRL . According to the gain control signal V _CTRL , the input transistors M1 and M2 operate in a linear or saturation region, and the upper transistors M3 and M4 operate in a saturation region.

In the conventional case described above, when the supply voltage VDD of the variable gain cell is low, the load resistance R _L must be increased in order to obtain a large gain and a large dynamic range. Then, the DC voltage of the output V _out is lowered by the voltage applied between the load resistors R _L , and all the CMOS transistors M1 to M4 operate in the linear region or the cutoff region, and thus high gain cannot be obtained. . Higher gains can be obtained by reducing the bias current I _S to prevent the output (V _out ) DC voltage from falling.However, when a high differential input signal (V _{in +} , V _in- ) is applied, severe distortion occurs. There is a problem with linearity.

US Patent No. 6,759,904 (Jul. 6, 2004, Large Gain Range, High Linearity, Low Noise MOS VGA), which is already known, uses an additional complex circuit for distortion characteristics, resulting in high power consumption and large integrated size. This is a problem when integrating.

In addition, another known technique, Korean Patent Application No. 01-38781 (published Jan. 08, 2003), has a characteristic of maximizing the gain of the preceding variable gain amplifier in order to improve noise characteristics, but at a low supply voltage. It is unreasonable to maximize the voltage gain in the proposed form.

Accordingly, a technical problem of the present invention is to provide a CMOS variable gain amplifier capable of operating at a low voltage, having a variable gain amplification function for an input signal having a wide variable gain range, and having a wide band operation characteristic by a fixed current bias. To provide. It also provides a variable gain amplifier that is IC integrated to integrate with other parts.

 Variable gain amplifier according to the present invention for achieving the above technical problem,

A variable transconductance converting unit configured to differentially input a differential input voltage signal to a cascode input terminal and adjust a magnitude of a transconductance according to a gain control voltage signal which is the cascode common gate voltage to generate output currents of various magnitudes;

A load resistance stage configured to output an output current of the variable transconductance converter to a differential output voltage using a resistive load or an active load;

A breeding current generating unit supplying a breeding current to the variable transconductance converting unit in parallel with the load resistance stage;

An output DC voltage comparator for detecting a DC voltage value of the differential output voltage and comparing the DC voltage value with a reference DC voltage value to maintain a constant DC voltage value of the differential output voltage; Characterized in having a.

The load resistance terminal connects the gate of the first P-type transistor and the drain of the second P-type transistor with a capacitor, and connects the gate of the second P-type transistor and both ends of the drain of the first P-type transistor with a capacitor. It can be done by.

The load resistance terminal connects the gate of the first N-type transistor and the drain of the second N-type transistor with a capacitor, and connects the gate of the second N-type transistor and the both ends of the drain of the first N-type transistor with a capacitor. It can be done by.

The load resistance stage may include a load resistor.

The variable transconductance converter may include a first transistor driven according to a first input voltage and a second transistor driven according to a second input voltage, in which case the source terminals of the first and second transistors may be resistors. Interconnected by

The variable transconductance converter may include a first transistor driven according to a first input voltage and a second transistor driven according to a second input voltage, in which case the source terminal of the first transistor is the third transistor. Is connected to the drain terminal of the second transistor, and the source terminal of the second transistor is connected to the source terminal of the third transistor.

The variable transconductance converter may include a first transistor driven according to a first input voltage and a second transistor driven in accordance with a second input voltage. In this case, the source terminal of the first transistor may include a third transistor. A source terminal of the second transistor is connected to a drain terminal of the third transistor.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail. The following embodiments are only presented to understand the content of the present invention, and those skilled in the art may make many modifications within the technical spirit of the present invention. Therefore, the scope of the present invention should not be construed as limited to these embodiments.

2 to 5 are circuit diagrams illustrating various embodiments of the variable gain amplifier according to the present invention. The variable gain amplifier according to the present invention includes a variable transconductance converter 100, an output DC voltage comparator 230, a bleeding current generator 220, and a load resistance stage 210. Reference numeral 200 is a load resistor including an output DC voltage comparator 230 and a bleeding current generator 220.

[Variable Transconductance Converter 100]

The variable transconductance converting unit 100 differentially receives and inputs the differential input voltage signals V _{in +} and V _in- through the differential input transistors M1 and M2, and outputs the amplified signals according to the gain control voltage signal V _ctrl . The transconductance is used to adjust the variable gain of the differential input voltage signals (V _{in +} , V _in- ). The cascode type input stage is composed of transistors M1, M2, M3, and M4. The cascode type input stage has an effect of minimizing a Miller effect and parasitic capacitance components.

In FIG. 3, the differential input transistor M1 is connected to the source terminal of the node P1 and the transistor M3, and another input transistor M2 is connected to the source terminal of the node P1 and the transistor M4. 2, 4, and 5, the differential input transistor M1 is connected to the node P1a and the source terminal of the transistor M3, and another differential input transistor M2 is connected to the node P1b and the source terminal of the transistor M4. The gain control voltage signal V _ctrl is applied to the gate terminals of the transistors M3 and M4, and operates as a common gate amplifier according to the gain control voltage signal V _ctrl .

The differential input transistors M1 and M2 operate in the linear or saturation region in accordance with the gain control voltage signal V _ctrl . When the gain control voltage signal V _ctrl is large, the transistors M1, M2, M3, and M4 all operate in the saturation region. On the other hand, when the gain control voltage signal V _ctrl is small, the transistors M1 and M3 operate in the linear region and the transistors M2 and M4 operate in the saturation region.

That is, according to the present invention, when the small differential input voltage signals V _{in +} and V _in- are applied, the gain control voltage signal V _ctrl is increased so that the two transistors M1 and M3 having a cascode connection are connected. ) Are all operated in the saturation region, and when the large differential input voltage signals (V _{in +} , V _in- ) are applied, the gain control voltage signal (V _ctrl ) is made small to make the differential input voltage signals (V _{in +} , V _in- ) Since only two transistors M1 and M2 to which V is applied are operated in the linear region, linearity can be maximized regardless of the magnitudes of the differential input voltage signals V _{in +} and V _in- . In addition, this cascode configuration has the advantage of having a large output impedance when viewed from the output nodes P2 and P3, thereby increasing the voltage gain.

The drain current I _ds in the linear region is

이고,

ego,

The transconductance (gm) in the linear domain is

이다.

to be.

이고,

이며,

는 트랜지스터의 문턱전압(threshold voltage)이다.here,

ego,

Is,

Is the threshold voltage of the transistor.

The drain current I _ds in the saturation region is

이고,

ego,

The transconductance (gm) in the saturation region is

이다. here,

to be.

[Output DC Voltage Comparator 230]

The output DC voltage comparator 230 detects a DC voltage value of the output node point and compares the DC voltage value with a desired reference DC voltage value. The output DC voltage comparator 230 detects the DC voltages of the differential output nodes P2 and P3 by the transistors M5 and M6 as in FIGS. 2, 3, 4, and 5. The DC voltage of the node P4 is the same as the P2 and P3 DC voltages, and AC forms a virtual ground node point by the differential output voltage.

Also, as shown in FIGS. 2 and 3, the DC voltage of the node P4 and the external reference voltage V _cm are compared by a differential amplifier including a transistor M11, a transistor M12, a transistor M13, a transistor M14, and a resistor R2 and a capacitor C2, which are frequency compensation circuits. Determine the bias voltage at node P5.

The bleeding current generator 220 to be described later determines the amount of bleeding current according to the node P5 voltage, and the DC voltages of the output nodes P2 and P3 are changed by the amount of current. Through this process, the external reference voltage V _cm is equal to the DC voltages of the output nodes P2 and P3.

As described above, the output DC voltage comparator 230 and the breeding current generator 220 configure negative bias and stably set the bias current and the output DC voltage. In FIGS. 2 and 3, the resistor R2 and the capacitor C2 allow the output DC voltage comparator 230 to operate stably as a compensation circuit. Since the output DC voltage can be adjusted externally, the DC gain level of the variable gain amplifier input and output can be the same, so that the circuits of FIGS. 2 and 3 can be connected in a cascaded form, thus providing a wider dynamic operating range. It is easy to implement a variable gain amplifier.

[Briding current generator 220]

The breeding current generator 220 applies the DC voltage of the node P5 obtained from the output DC voltage comparator 230 directly to the gate terminals of the transistors M9 and M10 as shown in FIGS. 2 and 3 to convert the current into a variable transconductance converter. 100).

Transistors M9 and M10 act as current sources and have a very high impedance seen at output nodes P2 and P3, and do not affect the performance of the circuit. When the breeding current generator 220 is used, the bias current flows to the load of the circuit and the bias current flows to the variable transconductance converter 100. In the variable transconductance converter 100, since more current flows linearly, the breeding current generator 220 may improve low distortion and high linearity characteristics.

In addition, since the current flowing through the load resistors R1 and 210 can be made small in FIG. 2, a large resistor can be used, thereby obtaining a large gain and a large variable gain range, and enabling low voltage operation while maintaining low distortion. In FIG. 3, as will be explained in the load resistance stage 210, the inverse of the transconductance values of the transistors M7 and M8 becomes an approximate output load (1 / g _m7, 1 / g _m8 ), and currents are applied to the transistors M7 and M8. The smaller the flow rate, the smaller the transconductance, so the output load increases, resulting in a large gain and a large variable gain range. As described above, the breeding current generator 220 may be implemented together with the output DC voltage comparator 230 to have characteristics such as low voltage operation, high gain, and high variable gain range.

[Load resistance stage 210]

Load resistance stage 210 receives a differential signal of a current form of output from the transconductance converter 100, a resistive load or active using a load of the differential signal of the electric current-output voltage of the voltage type (V _{out +,} Output to V _out- ). In detail, in FIG. 2, the load resistance stage 210 changes the differential signal in the form of current output from the differential transconductance converter 100 through the resistive load into the output voltages V _{out +} and V _{out− in the} form of voltage. . 3, 4, and 5 output the output voltages V _{out +} and V _{out− in the} form of voltage by using an active load instead of the resistor. The reason for using an active load instead of a resistive load as in FIGS. 3, 4, and 5 is to enable low voltage operation while improving the frequency characteristics of the CMOS variable gain amplifier.

As shown in Figs. 3, 4 and 5, transistors M7 and M8 have the inverse of their transconductance values, as mentioned above, to approximate output load values. Transistor M7 is connected between power supply voltage source VDD and output node P2 and is operated in accordance with the potential of bias voltage source Vp. Transistor M8 is connected between the power supply voltage source and the node P3 and operates according to the potential of the bias voltage source Vp. The gates of transistors M7 and M8 are connected to a bias voltage source Vp through a resistor R1. The voltage of this voltage source can optionally be connected to a ground signal. The capacitor C1 is connected between the gate terminal of the transistor M7 and the node P3, and between the gate terminal of the transistor M8 and the node P2, respectively.

Specifically, referring to the operating characteristics of the active load, the transistors M7 and M8 are operated as a load. The frequency characteristic compensation capacitor C1 has a zero frequency with the output impedance viewed from nodes P2 and P3, thereby improving the VGA overall circuit frequency characteristics. Therefore, the desired gain can be obtained at the desired frequency by adjusting the size of the frequency compensation capacitor C1 and the resistance R1. This allows for simpler wideband operation with larger gain, low voltage and frequency compensation capacitors than with the resistive load in FIG. 2.

As described above, according to the present invention, it is possible to provide a variable gain amplification function for an input signal having a wide range by an external regulated voltage signal at a low supply voltage, and have high gain, low distortion, high linearity, wideband operation, and safety. A variable gain amplifier having a conventional current bias form can be provided. In addition, CMOS transistors can operate at small supply voltages, making it possible to integrate them into ICs rather than variable gain amplifiers using other devices.

Claims (7)

A variable transconductance converting unit configured to differentially input a differential input voltage signal to a cascode input terminal and adjust a magnitude of a transconductance according to a gain control voltage signal which is the cascode common gate voltage to generate output currents of various magnitudes; A load resistance stage configured to output an output current of the variable transconductance converter to a differential output voltage using a resistive load or an active load; A breeding current generating unit supplying a breeding current to the variable transconductance converting unit in parallel with the load resistance stage; An output DC voltage comparator for detecting a DC voltage value of the differential output voltage and comparing the DC voltage value with a reference DC voltage value to maintain a constant DC voltage value of the differential output voltage; Variable gain amplifier comprising a. 2. The gate driving circuit of claim 1, wherein the load resistance terminal connects a gate of the first P-type transistor and a drain of the second P-type transistor with a capacitor, and the gate of the second P-type transistor and the first P-type transistor. A variable gain amplifier, characterized by connecting both ends of the drain with a capacitor. 2. The gate driving circuit of claim 1, wherein the load resistance terminal connects a gate of the first N-type transistor and a drain of the second N-type transistor with a capacitor, and the gate of the second N-type transistor and the first N-type transistor. A variable gain amplifier, characterized by connecting both ends of the drain with a capacitor. The variable gain amplifier as set forth in claim 1, wherein said load resistor stage comprises a load resistor. The display device of claim 1, wherein the variable transconductance converter includes a first transistor driven according to a first input voltage and a second transistor driven according to a second input voltage, and source terminals of the first and second transistors. A variable gain amplifier, characterized in that are interconnected by a resistor. 2. The variable transconductance converter of claim 1, wherein the variable transconductance converter includes a first transistor driven according to a first input voltage and a second transistor driven according to a second input voltage. And a drain terminal of the third transistor, wherein a source terminal of the second transistor is connected to a source terminal of the third transistor. 2. The variable transconductance converter of claim 1, wherein the variable transconductance converter comprises a first transistor driven according to a first input voltage and a second transistor driven according to a second input voltage, wherein a source terminal of the first transistor is connected to a third transistor. And a source terminal of the transistor, wherein the source terminal of the second transistor is connected to the drain terminal of the third transistor.

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