WO2017030091A1

WO2017030091A1 - Semiconductor device, operational amplifier and electronic device

Info

Publication number: WO2017030091A1
Application number: PCT/JP2016/073759
Authority: WO
Inventors: 井手大介; 片倉雅幸; 田上浩康; 有馬茉莉
Original assignee: ソニー株式会社
Priority date: 2015-08-19
Filing date: 2016-08-12
Publication date: 2017-02-23
Also published as: JP2018157238A

Abstract

The objective of the present invention is to increase the output impedance of a semiconductor device. This semiconductor device is provided with: a first transistor (Tr) element of a first conduction type, interposed in a first line connecting a high potential side power supply to a low potential side power supply; a second Tr element of the first conduction type, interposed in a second line connecting the high potential side power supply to the low potential side power supply; a third Tr element of a second conduction type, interposed in the first line and forming one of a differential pair; a fourth Tr element of the second conduction type, interposed in the second line and forming the other of the differential pair; a first output portion connected to the first line between the first Tr element and the third Tr element; a second output portion connected to the second line between the second Tr element and the fourth Tr element; a first resistor connecting the control terminal of the first Tr element to the first output portion; a second resistor connecting the control terminal of the second Tr element to the second output portion; and a third resistor connecting the control terminal of the first Tr element to the control terminal of the second Tr element.

Description

Semiconductor device, operational amplifier and electronic equipment

This technology relates to semiconductor devices, operational amplifiers, and electronic devices.

FIG. 13 is a diagram showing a basic configuration of a conventional transconductance circuit.

The transconductance circuit shown in FIG. 1 includes a PMOS 1 serving as a load MOS provided on a line L1 connecting between the high potential side power supply VDD and the low potential side power supply Gnd, and the high potential side power supply VDD and the low potential side. A differential pair composed of a PMOS 2 serving as a load MOS interposed on the line L2 connecting between the power supplies Gnd, an NMOS 3 interposed on the line L1, and an NMOS 4 interposed on the line L2. The common-source differential circuit has a common-mode feedback circuit 5 for setting an output common-mode potential and an NMOS 6 as a current source.

The common-mode feedback circuit 5 connects the drain of the PMOS 1 and the drain of the PMOS 2 with the resistors Rfb1 and Rfb2 connected in series, and connects the connection points of the resistors Rfb1 and Rfb2 to the gates of the PMOS1 and PMOS2, respectively. It is. The resistance values of the resistors Rfb1 and Rfb2 are the same. As a result, the common-mode potential of the output of a transconductance circuit that generally receives a differential signal can be set.

In the common-mode feedback circuit 5 described above, the resistors Rfb1 and Rfb2 detect the common-mode potential and feed back to the gates of the PMOS1 and PMOS2. Thereby, the output common-mode potential is set.
At this time, the range of the output common-mode potential is the voltage (VDD−Vdpsat) obtained by subtracting the voltage Vdpsat necessary for the saturation region operation of the PMOSs 1 and 2 from the high potential side power supply VDD, and the voltage necessary for the saturation region operation of the NMOS 3 or NMOS 4. It is between Vdnsat and a voltage (2Vdnsat) obtained by adding a voltage Vdnsat necessary for the operation of the NMOS 6 in the saturation region.

The resistors Rfb1 and Rfb2 do not feed back differential components, but become loads between the differential outputs, so they must be set to a sufficiently high value so as not to reduce the voltage gain of the transconductance circuit. For example, when the input / output common-mode potentials are the same, Vgsp which is the gate-source potential of PMOS 1 and 2 and Vgsn which is the gate-source potential of

NMOS

3 and 4 are 450 mV (Vth (400 mV) +50 mV), and the drain of NMOS 6 When the source-source potential is 150 mV, the operating lower limit voltage is 1.05 V, and the minimum operating voltage as a specification is about 1.2 to 1.3 V. In order to avoid this, there is a configuration shown in FIG. 14, for example, as a configuration in which the input / output operating point is set to such an extent that VDD does not drop to Vgsp (for example, VDD−200 mV). However, the current branch increases and the low current consumption characteristics deteriorate.

Further, the transconductance circuit should have a characteristic that the output impedance is extremely high, and the transconductance Gm should be a certain value and the voltage gain should be extremely large. The following equation (1) is an equation representing the output impedance Zout of the transconductance circuit shown in FIG. In the following equation (1), R _FB is the resistance value of the resistors Rfb1 and Rfb2, R _DSN is the drain-source resistance of the

NMOS

3 and 4, and R _DSP is the drain-source resistance of the PMOS 1 and 2.

As can be seen from the equation (1), in the transconductance circuit shown in FIG. 13, the output impedances of the PMOS 1, 2 and

NMOS

3 and 4 are dominant, and the resistors Rfb1 and Rfb2 of the common-mode feedback circuit further lower the output impedance. Let In addition, with the miniaturization of devices due to advances in LSI technology, the output impedance of transistors tends to decrease, and the output impedance of transconductance circuits also tends to decrease.

The present technology has been made in view of the above problems, and aims to increase the output impedance of the semiconductor device, and more desirably to further reduce the operating voltage and / or power consumption of the semiconductor device. With the goal.

One aspect of the present technology includes a first transistor element of a first conductivity type interposed on a first line connecting a high potential side power source and a low potential side power source, the high potential side power source, A second transistor element of a first conductivity type interposed on a second line connecting between the low potential side power supplies and a second transistor interposed on the first line and constituting one of the differential pairs. A conductive third transistor element; a second conductive fourth transistor element interposed on the second line and constituting the other of the differential pair; the first transistor element and the third transistor element; A first output connected to the first line between, a second output connected to the second line between the second transistor element and the fourth transistor element, and A first connecting the control terminal and the first output unit; A resistor, a second resistor connecting the control terminal of the second transistor element and the second output unit, and a connection between the control terminal of the first transistor element and the control terminal of the second transistor element; And a third resistor.

Another aspect of the present technology includes a first transistor element of a first conductivity type interposed on a first line connecting a high potential side power source and a low potential side power source, and the high potential side A second transistor element of a first conductivity type interposed on a second line connecting between a power source and the low potential side power source, and constitutes one of a differential pair interposed on the first line. A third transistor element of a second conductivity type; a fourth transistor element of a second conductivity type interposed on the second line and constituting the other of the differential pair; the first transistor element and the third transistor; A first output connected to the first line between the first transistor, a second output connected to the second line between the second transistor and the fourth transistor, and the first transistor. Connecting between the control terminal of the element and the first output unit A first resistor, a second resistor connecting the control terminal of the second transistor element and the second output unit, and between the control terminal of the first transistor element and the control terminal of the second transistor element And a third resistor for connecting the two as a differential input stage.

Another aspect of the present technology includes a first transistor element of a first conductivity type interposed on a first line connecting a high potential side power source and a low potential side power source, and the high potential side A second transistor element of a first conductivity type interposed on a second line connecting between a power source and the low potential side power source, and constitutes one of a differential pair interposed on the first line. A third transistor element of a second conductivity type; a fourth transistor element of a second conductivity type interposed on the second line and constituting the other of the differential pair; the first transistor element and the third transistor; A first output connected to the first line between the first transistor, a second output connected to the second line between the second transistor and the fourth transistor, and the first transistor. Connecting between the control terminal of the element and the first output unit A first resistor, a second resistor connecting the control terminal of the second transistor element and the second output unit, and between the control terminal of the first transistor element and the control terminal of the second transistor element And an electronic device including a semiconductor device.

Note that the semiconductor device, operational amplifier, and electronic device described above include various modes such as being implemented in another device or being implemented together with another method.

According to the present technology, it is possible to increase the output impedance of the semiconductor device, and it is also possible to reduce the operating voltage and / or power consumption of the semiconductor device. Note that the effects described in the present specification are merely examples and are not limited, and may have additional effects.

It is a figure which shows the structure of the transconductance circuit which concerns on 1st Embodiment. It is a small signal equivalent circuit of the current source load of the transconductance circuit according to the first embodiment. It is a figure which shows the other structural example of the transconductance circuit which concerns on 1st Embodiment. It is a figure which shows the structure of the transconductance circuit which concerns on 2nd Embodiment. It is a figure which shows the other structural example of the transconductance circuit which concerns on 2nd Embodiment. It is a figure which shows a specific example of the current source generation circuit which concerns on 2nd Embodiment. It is a figure which shows the structure of the transconductance circuit which concerns on 3rd Embodiment. It is a figure which shows the other structural example of the transconductance circuit which concerns on 3rd Embodiment. It is a figure which shows a specific example of a Vcm generation circuit. It is a figure which shows the structure of the transconductance circuit which concerns on 4th Embodiment. It is a figure which shows the other structural example of the transconductance circuit which concerns on 4th Embodiment. It is a figure which shows a specific example of the current source generation circuit which concerns on 4th Embodiment. It is a figure which shows an example of the conventional transconductance circuit. It is a figure which shows an example of the conventional transconductance circuit.

Hereinafter, the present technology will be described in the following order.
(A) First embodiment:
(B) Second embodiment:
(C) Third embodiment:
(D) Fourth embodiment:

(A) First embodiment:
FIG. 1 is a diagram showing a configuration of a transconductance circuit 100 as a semiconductor device according to the present embodiment.

The transconductance circuit 100 is a transconductance circuit based on a common source-common differential circuit, and includes a pair of transistor elements 10 serving as a load, a differential pair 20, a first output unit 30, a second output unit 40, and a current source. 50, a first resistor 60, a second resistor 70, and a third resistor 80.

A pair of transistor elements 10 serving as a load is configured by a PMOS 11 as a first transistor element of a first conductivity type and a PMOS 12 as a second transistor of a first conductivity type. The PMOS 11 is interposed on the line L1 as the first line, and the PMOS 12 is interposed on the line L2 as the second line. The first line and the second line are lines respectively connecting a constant voltage source VDD as a high potential side power source and a ground GND as a low potential side power source.

The differential pair 20 includes an NMOS 21 as a second conductivity type third transistor element and an NMOS 22 as a second conductivity type fourth transistor element. The NMOS 21 is interposed downstream of the PMOS 11 on the line L1, and the NMOS 22 is interposed downstream of the PMOS 12 on the line L2. The voltage Vinp constituting one of the differential input voltages is input to the gate as the control terminal of the NMOS 21, and the voltage Vinn constituting the other of the differential input voltages is input to the gate as the control terminal of the NMOS 22. .

The current source 50 is constituted by an NMOS 51 which is a transistor element of the second conductivity type that connects between the NMOS 21 and NMOS 22 constituting the differential pair and the ground GND. A constant voltage Vgsn is applied to the gate of the NMOS 51. As a result, the current flowing through the NMOS 51 is set to 2 × I0.

The

PMOS

11 and 12 and the NMOSs 21 and 22 described above each have an on-resistance. In FIG. 1, Rdsp is indicated as the on-resistance of the

PMOSs

11 and 12, and Rdsn is indicated as the on-resistance of the

NMOSs

21 and 22. .

The first output unit 30 is connected to a line L1 between the PMOS 11 and the NMOS 21, and the voltage of the first output unit 30 constitutes a voltage Voutp that constitutes one of the differential output voltages.
The second output unit 40 is connected to a line L2 between the PMOS 12 and the NMOS 22, and the voltage of the second output unit 40 constitutes a voltage Voutn that constitutes the other of the differential output voltages.

The first resistor 60 connects between the gate of the PMOS 11 and the first output unit 30, and the second resistor 70 connects between the gate of the PMOS 12 and the second output unit 40. As a result, the first resistor 60 applies positive feedback to the gate of the PMOS 11, and the second resistor 70 applies positive feedback to the gate of the PMOS 12.

The third resistor 80 is connected between the gate of the PMOS 11 and the gate of the PMOS 12. That is, the third resistor 80 connects between the terminal of the first resistor 60 on the side connected to the gate of the PMOS 11 and the terminal of the second resistor 70 on the side connected to the gate of the PMOS 12.

FIG. 2 is a small signal equivalent circuit of the current source load of the transconductance circuit 100 provided with the third resistor 80 as described above. In the figure, Rfb indicates the resistance value of the first resistor 60 and the second resistor 70, Rx indicates half of the resistance value of the third resistor 80, and Gm indicates transconductance.

The output impedance between the first output unit 30 and the second output unit 40 can be expressed by the following equation (2). In the formula (2), (k · Gm) / 2 indicates a negative resistance.

In other words, if k and Gm are set so that the term indicating the negative resistance cancels each term composed only of Rfb, Rx, Rdsn, and Rdsp, it is not necessary to make Rfb sufficiently larger than the drain-source resistance. It can be seen that a very high impedance can be obtained. In addition, although the number of resistors is increased as compared with the conventional circuit, the resistance values of the first resistor 60 and the second resistor 70 can be reduced. Therefore, when the output impedance equivalent to that of the conventional transconductance circuit is realized, the circuit area is reduced. Is less than 1/10.

The transconductance circuit 100 described above may be configured to directly connect the source terminals of the

NMOSs

21 and 22 to the ground GND without providing the current source 50, as shown in FIG. Thus, even in the transconductance circuit 100 in which the current source 50 is not provided, a high low-frequency gain can be realized.

(B) Second embodiment:
FIG. 4 is a diagram showing a configuration of a transconductance circuit 200 as a semiconductor device according to the present embodiment.

The transconductance circuit 200 has the same configuration as that of the transconductance circuit 100 according to the first embodiment except that a resistor 81 and a resistor 82 are provided in series instead of the third resistor 80 and a current source 210 is provided. Therefore, the common configuration is denoted by the same reference numeral as that of the transconductance circuit 100, and detailed description of each component is omitted.

Note that the resistance values of the resistor 81 and the resistor 82 will be described as Rx in order to correspond to the resistance value of the third resistor 80 according to the first embodiment described above in the calculation formula of the output impedance.

The current source 210 is connected between the connection point C of the resistor 81 and the resistor 82 which is the middle point of the third resistor 80 and the ground GND, and the current 2 × Ib is drawn from the connection point C. As a result, the current Ib flows through each of the

resistors

81 and 82, and the current Ib also flows through the first resistor 60 and the second resistor 70, so that the outputs Voutp and Voutn can be increased by Rfb × Ib.

Thus, even if VDD is reduced by Rfb × Ib, the drain-source voltage of the current source 50 can be kept the same, and the power supply voltage can be reduced. Although the current consumption increases by 2 × Ib, the resistance Rfb through which the 2 × Ib flows inevitably becomes high resistance, so the current value of 2 × Ib is about 1/10 of the current value of 2 × I0. The increase in current consumption is very small.

Further, as in the first embodiment described above, a high output impedance can be realized. Thereby, it is possible to realize a transconductance circuit that can achieve both low voltage, low current consumption, and high output impedance.

The transconductance circuit 200 described above may have a configuration in which the current source 50 is not provided and the source terminals of the

NMOSs

21 and 22 are directly connected to the ground GND as shown in FIG. Even in the transconductance circuit 200 in which the current source 50 is not provided, it is possible to realize low voltage, low current consumption, high output impedance, and high low frequency gain.

FIG. 6 is a diagram showing a specific example of the current source 210.

The current source 210 shown in the figure includes a resistor 211, a current source 212, a PMOS 213, a resistor 214, a current source 215, an operational amplifier 216, and

NMOSs

217, 218, and 219.

The resistor 211 and the current source 212 are circuits that generate a desired constant voltage V1.

Specifically, the resistor 211 and the current source 212 are connected in series, and the resistor 211 is connected to the constant voltage source VDD side, the current source 212 is connected to the ground Gnd side, and the constant voltage source VDD and the ground Gnd are connected. . As a result, a desired constant voltage V1 corresponding to the current values of the resistor 211 and the current source 212 is generated.

The PMOS 213, the resistor 214, and the current source 215 are replicas simulating the PMOS 11, the current source 50, and the first resistor 60 (or the PMOS 12, the current source 50, and the second resistor 70) as either one of the left and right sides of the transconductance circuit 200. This is a circuit for generating a current source Ib that is a source of the current value of the current source 210 in the NMOS 217 having a configuration corresponding to the current source 210.

Specifically, the PMOS 213 and the current source 215 are also connected in series. The source terminal of the PMOS 213 is the constant voltage source VDD side, the current source 215 is the ground Gnd side, and the constant voltage source VDD and the ground Gnd are connected. Yes. The gate and drain of the PMOS 213 are connected by a resistor 214 having the same resistance value as the first resistor 60 and the second resistor 70. An NMOS 217 is connected between the gate of the PMOS 213 and the ground GND. The current source 215 is set to a current value half that of the current source 50. As a result, a voltage V2 is generated between the drain of the PMOS 213 and the current source 215, and a current corresponding to the voltage V2 flows to the NMOS 217.

The operational amplifier 216 receives the voltage V2 and the constant voltage V1, and applies a voltage at which the potential difference between the constant voltage V1 and the voltage V2 becomes zero to the gate of the NMOS 217. Thus, the current Ib flowing through the NMOS 217 has a current value corresponding to the constant voltage V1.

The current Ib generated in the NMOS 217 is current mirrored in the

NMOSs

218 and 219. The

NMOSs

218 and 219 are configured to generate a current twice that of the NMOS 217 by, for example, doubling the transistor size. Thereby, a current 2 × Ib generated in the

NMOSs

218 and 219 corresponding to the current source 210 of FIG. 5 is generated as a current supplied from the current source 210 to the transconductance circuit 200.

The current 2 × Ib generated in this way can be constant without depending on device variations or the like, “VDD−Vgs + Rfb × Ib”, which is the input / output common-mode voltage.

(C) Third embodiment:
FIG. 7 is a diagram showing a configuration of a transconductance circuit 300 as a semiconductor device according to the present embodiment.

The transconductance circuit 300 has the same configuration as that of the transconductance circuit 200 according to the second embodiment except that the current source 210 is not provided and the resistor 310 is provided instead. The same reference numerals as those in FIG.

In the resistor 310, one terminal is connected to a connection point C between the resistor 81 and the resistor 82 which is the middle point of the third resistor 80, and the voltage Vcm is input to the other terminal. At this time, the current flowing through the resistor 310 acts on the transconductance circuit 300 as the above-described current 2 × Ib.

In this way, the common-mode voltage Ib of the transconductance circuit 300 can be set with higher accuracy by generating the common-mode current Ib with the resistor 310 having higher current accuracy than the transistor without using a current source including a transistor element. .

The transconductance circuit 300 described above may be configured to directly connect the source terminals of the

NMOSs

21 and 22 to the ground GND without providing the current source 50 as shown in FIG. Thus, even in the transconductance circuit 300 without the current source 50, the same current accuracy and high low frequency gain can be realized.

FIG. 9 is a diagram showing a specific example of a Vcm generation circuit that generates the voltage Vcm.

The Vcm generation circuit 310 shown in the figure includes a resistor 311, a current source 312, a PMOS 313, a resistor 314, a current source 315, a resistor 316, and an operational amplifier 317.

The resistor 311 and the current source 312 are circuits that generate a desired constant voltage V1.

Specifically, the resistor 311 and the current source 312 are connected in series, and the resistor 311 is connected to the constant voltage source VDD side, the current source 312 is connected to the ground Gnd side, and the constant voltage source VDD and the ground Gnd are connected. . As a result, a desired constant voltage V1 corresponding to the current values of the resistor 311 and the current source 312 is generated.

The PMOS 313, the resistor 314, the current source 315, the resistor 316, and the operational amplifier 317 are the PMOS 11, the current source 50, and the first resistor 60 (or the PMOS 12, the current source 50, and the second one as the left or right of the transconductance circuit 300). This is a replica circuit simulating the resistor 70), and is a circuit for generating the voltage Vcm at one terminal of the resistor 316 having a configuration corresponding to the resistor 310.

Specifically, the PMOS 313 and the current source 315 are also connected in series. The source terminal of the PMOS 313 is the constant voltage source VDD side, the current source 315 is the ground Gnd side, and the constant voltage source VDD and the ground Gnd are connected. Yes. The gate and drain of the PMOS 313 are connected by a resistor 314 having the same resistance value as the first resistor 60 and the second resistor 70. The other terminal of the resistor 316 is connected to the gate of the PMOS 313. The resistance value of the resistor 316 is twice that of the resistor 310. The current source 315 is set to a current value half that of the current source 50.
As a result, a voltage V 2 is generated between the drain of the PMOS 313 and the current source 315.

The operational amplifier 317 receives the voltage V2 and the constant voltage V1, has an output terminal connected to the gate of the PMOS 313 via the resistor 316, and an output terminal of the operational amplifier 317 via the

resistors

314 and 316 connected in series. And the inverting input terminal are connected to each other.

At this time, the current flowing through the resistor 316 corresponds to Ib, and the voltage Vcm generated at the terminal of the resistor 316 on the output terminal side of the operational amplifier 317 is a value corresponding to the constant voltage V1. The Vcm generation circuit 310 can supply a voltage Vcm through which a positive current or a negative current flows to the resistor 310 by adjusting the value of the voltage Vcm.

The current 2 × Ib flowing through the resistor 310 by the Vcm generated in this way is constant without depending on the variation of the device or the like, “VDD−Vgs + Rfb × Ib”, which is the input / output common-mode voltage.

(D) Fourth embodiment:
FIG. 10 is a diagram showing a configuration of a transconductance circuit 400 as a semiconductor device according to the present embodiment.

The transconductance circuit 400 has the same configuration as that of the transconductance circuit 100 according to the first embodiment except that a resistor 81 and a resistor 82 are provided in series instead of the third resistor 80 and a current source 410 is provided. Therefore, the common components are denoted by the same reference numerals as those of the transconductance circuit 100, and detailed description of each component is omitted.

The current source 410 is connected between the connection point C of the

resistors

81 and 82, which is the middle point of the third resistor 80, and the constant voltage source VDD, and the current 2 × Ib flows into the connection point C. As a result, the current Ib flows through each of the

resistors

81 and 82, and the current Ib also flows through the first resistor 60 and the second resistor 70, so that the constant voltage source VDD can be lowered by Rfb × Ib.

This makes it possible to secure a wide dynamic range by adjusting the output common-mode reference potential to around VDD / 2. Although the current consumption increases by 2 × Ib, the resistance Rfb through which the 2 × Ib flows inevitably becomes high resistance, so the current value of 2 × Ib is about 1/10 of the current value of 2 × I0. The increase in current consumption is very small.

The transconductance circuit 400 described above may be configured to directly connect the source terminals of the

NMOSs

21 and 22 to the ground GND without providing the current source 50 as shown in FIG. Even in the transconductance circuit 400 in which the current source 50 is not provided, a low voltage, a low current consumption, a high output impedance, and a high low frequency gain can be realized.

FIG. 12 is a diagram showing a specific example of the current source 410.

The current source 410 shown in the figure includes a resistor 411, a current source 412, a PMOS 413, a resistor 414, a current source 415, an operational amplifier 416, and

PMOSs

417, 418, and 419.

The resistor 411 and the current source 412 are circuits that generate a desired constant voltage V1 corresponding to the current 2 × I0 generated by the current source 50.

Specifically, the resistor 411 and the current source 412 are connected in series, and the resistor 411 is connected to the constant voltage source VDD side, the current source 412 is connected to the ground Gnd side, and the constant voltage source VDD and the ground Gnd are connected. . As a result, a desired constant voltage V1 corresponding to the current values of the resistor 411 and the current source 412 is generated.

The PMOS 413, the resistor 414, and the current source 415 are replicas simulating the PMOS 11, the current source 50, and the first resistor 60 (or the PMOS 12, the current source 50, and the second resistor 70) as either one of the left and right sides of the transconductance circuit 400. This is a circuit that generates a current source Ib that is a source of the current value of the current source 410 in a PMOS 417 that has a configuration corresponding to the current source 410.

Specifically, the PMOS 413 and the current source 415 are also connected in series. The source terminal of the PMOS 413 is the constant voltage source VDD side, the current source 415 is the ground Gnd side, and the constant voltage source VDD and the ground Gnd are connected. Yes. The gate and drain of the PMOS 413 are connected by a resistor 414 having the same resistance value as that of the first resistor 60 and the second resistor 70. An NMOS 417 is connected between the gate of the PMOS 413 and the ground GND. The current source 415 has a current value that is half that of the current source 50. As a result, a voltage V2 is generated between the drain of the PMOS 413 and the current source 415, and a current corresponding to the voltage V2 flows to the NMOS 417.

The operational amplifier 416 receives the voltage V2 and the constant voltage V1, and applies a voltage at which the potential difference between the constant voltage V1 and the voltage V2 becomes zero to the gate of the NMOS 417. Thereby, the current Ib flowing through the NMOS 417 becomes a current value corresponding to the constant voltage V1. The current Ib generated in the NMOS 417 in this way is current mirrored in the

NMOSs

418 and 419.

The

NMOSs

418 and 419 are configured to generate a current twice that of the NMOS 417 by, for example, doubling the transistor size. As a result, a current 2 × Ib generated in the

NMOSs

418 and 419 corresponding to the current source 410 in FIG. 11 is generated as a current supplied from the current source 410 to the transconductance circuit 400.

The transconductance circuits 100 to 400 according to the present technology described above are implemented in various modes such as being implemented as an operational amplifier with an output stage or being incorporated in a circuit of an electronic device. . Examples of suitable electronic circuits incorporating the transconductance circuit according to the present technology include those having digital circuits and analog circuits that are required to be miniaturized, low power supply voltage, and low power consumption.

Note that the present technology is not limited to the above-described embodiments, and the configurations disclosed in the above-described embodiments are replaced with each other or the combination thereof is changed, disclosed in the known technology, and in the above-described embodiments. A configuration in which each configuration is mutually replaced or a combination is changed is also included. The technical scope of the present technology is not limited to the above-described embodiment, but extends to the matters described in the claims and equivalents thereof.

And this technique can take the following composition.

(1)
A first transistor element of a first conductivity type interposed on a first line connecting between a high potential side power source and a low potential side power source;
A second transistor element of a first conductivity type interposed on a second line connecting between the high potential side power source and the low potential side power source;
A third transistor element of a second conductivity type interposed on the first line and constituting one of the differential pairs;
A fourth transistor element of a second conductivity type interposed on the second line and constituting the other of the differential pair;
A first output connected to the first line between the first transistor element and the third transistor element;
A second output connected to the second line between the second transistor element and the fourth transistor element;
A first resistor connecting the control terminal of the first transistor element and the first output unit;
A second resistor connecting the control terminal of the second transistor element and the second output unit;
A semiconductor device comprising: a third resistor that connects between a control terminal of the first transistor element and a control terminal of the second transistor element.

(2)
The semiconductor device according to (1), further including a first current source that draws a current from a midpoint of the third resistor.

(3)
The semiconductor device according to (1), further including a second current source that supplies current to a midpoint of the third resistor.

(4)
The semiconductor device according to (1), further including a resistor that connects a middle point of the third resistor and a predetermined constant voltage source.

(5)
A first transistor element of a first conductivity type interposed on a first line connecting between a high potential side power source and a low potential side power source;
A second transistor element of a first conductivity type interposed on a second line connecting between the high potential side power source and the low potential side power source;
A third transistor element of a second conductivity type interposed on the first line and constituting one of the differential pairs;
A fourth transistor element of a second conductivity type interposed on the second line and constituting the other of the differential pair;
A first output connected to the first line between the first transistor element and the third transistor element;
A second output connected to the second line between the second transistor element and the fourth transistor element;
A first resistor connecting the control terminal of the first transistor element and the first output unit;
A second resistor connecting the control terminal of the second transistor element and the second output unit;
An operational amplifier comprising, as a differential input stage, a third resistor that connects between a control terminal of the first transistor element and a control terminal of the second transistor element.

(6)
An electronic apparatus comprising the semiconductor device according to any one of (1) to (4).

DESCRIPTION OF SYMBOLS 10 ... A pair of transistor element used as load, 20 ... Differential pair, 30 ... 1st output part, 40 ... 2nd output part, 50 ... Current source, 60 ... 1st resistance, 70 ... 2nd resistance, 80 ... 1st 3 resistors, 81... Resistors, 82. Resistors, 100 .. transconductance circuit, 200... Transconductance circuit, 210... Current source, 300... Transconductance circuit, 310.

Claims

A first transistor element of a first conductivity type interposed on a first line connecting between a high potential side power source and a low potential side power source;
A second transistor element of a first conductivity type interposed on a second line connecting between the high potential side power source and the low potential side power source;
A third transistor element of a second conductivity type interposed on the first line and constituting one of the differential pairs;
A fourth transistor element of a second conductivity type interposed on the second line and constituting the other of the differential pair;
A first output connected to the first line between the first transistor element and the third transistor element;
A second output connected to the second line between the second transistor element and the fourth transistor element;
A first resistor connecting the control terminal of the first transistor element and the first output unit;
A second resistor connecting the control terminal of the second transistor element and the second output unit;
A semiconductor device comprising: a third resistor that connects between a control terminal of the first transistor element and a control terminal of the second transistor element.
The semiconductor device according to claim 1, further comprising a first current source that draws a current from a midpoint of the third resistor.
The semiconductor device according to claim 1, further comprising a second current source that feeds a current to a middle point of the third resistor.
The semiconductor device according to claim 1, further comprising a resistor that connects a middle point of the third resistor and a predetermined constant voltage source.
A first transistor element of a first conductivity type interposed on a first line connecting between a high potential side power source and a low potential side power source;
A second transistor element of a first conductivity type interposed on a second line connecting between the high potential side power source and the low potential side power source;
A third transistor element of a second conductivity type interposed on the first line and constituting one of the differential pairs;
A fourth transistor element of a second conductivity type interposed on the second line and constituting the other of the differential pair;
A first output connected to the first line between the first transistor element and the third transistor element;
A second output connected to the second line between the second transistor element and the fourth transistor element;
A first resistor connecting the control terminal of the first transistor element and the first output unit;
A second resistor connecting the control terminal of the second transistor element and the second output unit;
An operational amplifier comprising, as a differential input stage, a third resistor that connects between a control terminal of the first transistor element and a control terminal of the second transistor element.
An electronic device comprising the semiconductor device according to claim 1.