CN209265310U - A kind of voltage buffer circuit - Google Patents
A kind of voltage buffer circuit Download PDFInfo
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- CN209265310U CN209265310U CN201821753999.7U CN201821753999U CN209265310U CN 209265310 U CN209265310 U CN 209265310U CN 201821753999 U CN201821753999 U CN 201821753999U CN 209265310 U CN209265310 U CN 209265310U
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Abstract
The utility model relates to technical field of integrated circuits, more particularly to a kind of voltage buffer circuit, the voltage buffer circuit includes amplifier major loop and adaptive-biased, and the non-inverting input terminal VP of the amplifier major loop is connect with input voltage VIN, and inverting input terminal VN is connect with output end VOUT；The adaptive-biased input VP_bias is connect with the non-inverting input terminal VP of the amplifier major loop, and input VN_bias is connect with the inverting input terminal VN of the amplifier major loop；The electric current port IP_amp of the amplifier major loop is connect with the adaptive-biased electric current port IN_bias, its electric current port IN_amp is connect with the adaptive-biased electric current port IP_bias, the utility model is using adaptive-biased in conjunction with amplifier, improve response speed and driving capability, there is high input and output dynamic range simultaneously, adapt to wide power voltage work, low-power consumption.
Description
Technical field
The utility model relates to technical field of integrated circuits, and in particular to a kind of voltage buffer circuit.
Background technique
Voltage buffer (voltage buffer) is often used in voltage needed for providing some circuit work, to enhance
The driving capability of echo signal, while the interference shadow to previous stage circuit output voltage can also be loaded to avoid voltage buffer
It rings.Therefore voltage buffer, which has, extremely widely applies.For example, needing in capacitance touch control chip using voltage
Buffer drives heavy load capacitor and requires fast and stable；For another example, the source electrode driver in liquid crystal display is needed using electricity
Compression buffer provides stable common-mode voltage.
In the prior art, voltage buffer (referring to Fig. 1) is as all Analogous Integrated Electronic Circuits, by Analog Circuit Design
Octagon rule limitation, need to weigh between each performance.In recent years, in consumer electronics sector, chip operation electricity
Press lower and lower, power consumption is smaller and smaller.For voltage buffer, designer is in its low-power consumption, low-voltage, high-speed, small core
The case where piece area etc. has carried out research optimization, is commonly present a certain performance and improves, and other performance declines.
Utility model content
In view of the deficiencies of the prior art, the utility model discloses a kind of voltage buffer circuits, are not increasing chip
Under the premise of power consumption and chip area, capacitive load driving capability is enhanced, and the voltage buffer can work in wide electricity
Under the voltage of source, there is high input and output dynamic range.
The utility model is achieved by the following technical programs:
A kind of voltage buffer circuit, the voltage buffer circuit include amplifier major loop and adaptive-biased, described
The non-inverting input terminal VP of amplifier major loop is connect with input voltage VIN, and inverting input terminal VN is connect with output end VOUT；It is described
Adaptive-biased input VP_bias is connect with the non-inverting input terminal VP of the amplifier major loop, input VN_bias with it is described
The inverting input terminal VN connection of amplifier major loop；The electric current port IP_amp of the amplifier major loop and described adaptive-biased
The IN_bias connection of electric current port, electric current port IN_amp are connect with the adaptive-biased electric current port IP_bias.
Preferably, the amplifier major loop includes input difference to, current mirror and Push-pull-output stage.
Preferably, the grid of the input difference centering of the amplifier major loop one input metal-oxide-semiconductor and amplifier major loop
Non-inverting input terminal VP connection, source electrode are connect with the electric current port IP_amp of amplifier major loop；The input difference is to another input
The grid of metal-oxide-semiconductor is connect with the inverting input terminal VN of amplifier major loop, and the electric current port IN_amp of source electrode and amplifier major loop connects
It connects.
Preferably, the adaptive-biased current source bias VB1 connects with the grid of PMOS tube M1 and PMOS tube M1 ' respectively
It connects, the adaptive-biased Cascode current source bias VB2 is connected with the grid of PMOS tube M5 and PMOS tube M5 ' respectively.
Preferably, it is described it is adaptive-biased in:
The source electrode of the PMOS tube M1 meets power vd D, and drain electrode is connect with the drain electrode of NMOS tube M2；
The grid of the NMOS tube M2 is same mutually defeated as the adaptive-biased input VP_bias and amplifier major loop
Enter VP is held to connect, source electrode is connect with the drain electrode of NMOS tube M3；
The source electrode of the NMOS tube M3 is grounded, and the grid and drain electrode of grid and NMOS tube M4 connect, the NMOS tube M4
Source electrode ground connection；
The drain electrode of the PMOS tube M5 is connect with the grid of the grid of NMOS tube M4 and drain electrode and NMOS tube M3, source electrode
It is connect with the drain electrode of PMOS tube M1 and NMOS tube M2.
Preferably, the adaptive-biased electric current is drawn in the drain electrode of the source electrode of the NMOS tube M2 and the NMOS tube M3
Port IP _ bias.
Preferably, it is described it is adaptive-biased in:
The source electrode of the PMOS tube M1 ' meets power vd D, and drain electrode is connect with the drain electrode of NMOS tube M2 '；
Reverse phase of the grid of the NMOS tube M2 ' as adaptive-biased the input VN_bias and amplifier major loop
Input terminal VN connection, source electrode are connect with the drain electrode of NMOS tube M3 '；
The source electrode of the NMOS tube M3 ' is grounded, and the grid and drain electrode of grid and NMOS tube M4 ' connect, the NMOS tube
The source electrode of M4 ' is grounded；
PMOS tube M5 ' the drain electrode is connect with the grid of the grid of the NMOS tube M4 ' and drain electrode and NMOS tube M3 ',
Its source electrode is connect with the drain electrode of the PMOS tube M1 ' and NMOS tube M2 '.
Preferably, the adaptive-biased electricity is drawn in the drain electrode of the source electrode of the NMOS tube M2 ' and the NMOS tube M3 '
Flow port IN_bias.
The utility model has the following beneficial effects:
1) the utility model is by using adaptive bias, when input voltage VIN variation, adaptive bias
It will sharply increase, and can guarantee voltage buffer quick response, and enable to export the variation that VOUT follows VIN in time；And it is defeated when inputting
Out once stablizing, size of current when bias current will be reduced to original static state, to be increased without any quiescent dissipation and improve
The response speed and driving capability of voltage buffer.
2) the Cascode branch of the utility model adaptive bias circuit, the energy when inputting common mode electrical level and changing bigger
Size of current is effectively adjusted, the stabilization for controlling quiescent current does not change with common mode electrical level and changed, to realize that high input is defeated
Dynamic range out.
3) amplifier major loop is exported using push-pull type in the utility model, further improves the response speed of voltage buffer
Degree and driving capability.
4) amplifier major loop, adaptive bias circuit can work at low supply voltages in the utility model, adapt to wide
The work of supply voltage range.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is traditional voltage buffer circuit schematic diagram；
Fig. 2 is the schematic diagram of the utility model voltage buffer circuit；
Fig. 3 is the amplifier major loop circuit diagram of the utility model voltage buffer；
Fig. 4 is the adaptive bias circuit schematic diagram of the utility model voltage buffer.
Specific embodiment
It is practical new below in conjunction with this to keep the objectives, technical solutions, and advantages of the embodiments of the present invention clearer
Attached drawing in type embodiment, the technical scheme in the utility model embodiment is clearly and completely described, it is clear that is retouched
The embodiment stated is the utility model a part of the embodiment, instead of all the embodiments.Based on the implementation in the utility model
Example, every other embodiment obtained by those of ordinary skill in the art without making creative efforts belong to
The range of the utility model protection.
As shown in Fig. 2, a kind of voltage buffer circuit schematic diagram of the utility model, including amplifier major loop and adaptive
Biasing, the non-inverting input terminal VP of amplifier major loop are connect with input voltage VIN, the inverting input terminal VN of amplifier major loop and output
Hold VOUT connection；Adaptive-biased input VP_bias is connect with the non-inverting input terminal VP of amplifier major loop, adaptive-biased
The inverting input terminal VN of input VN_bias and amplifier major loop is connected to the output end VOUT of voltage buffer circuit；Amplifier
The electric current port IP_amp of major loop is connect with adaptive-biased electric current port IN_bias, the electric current port of amplifier major loop
IN_amp is connect with adaptive-biased electric current port IP_bias.
The present embodiment is by using adaptive bias, and when input voltage VIN variation, adaptive bias will be anxious
Increase severely and add, can guarantee voltage buffer quick response, enables to export the variation that VOUT follows VIN in time；And work as input and output one
Denier is stablized, size of current when bias current will be reduced to original static state, to be increased without any quiescent dissipation and improve voltage
The response speed and driving capability of buffer.
As shown in figure 3, the amplifier major loop of voltage buffer includes input difference to, current mirror and Push-pull-output stage.
The input difference pair of amplifier major loop, non-inverting input terminal VP of the grid of one of input NMOS1 pipe as amplifier major loop
It is connect with the port buffer VIN, electric current port IP_amp and adaptive-biased IN_ of the source electrode of NMOS1 as amplifier major loop
The connection of the port bias；Differential pair it is another input NMOS2 pipe grid as amplifier major loop inverting input terminal VN with connect delay
Rush the connection of the port device VOUT, electric current port IN_amp and adaptive-biased IP_ of the source electrode of NMOS2 as amplifier major loop
The connection of the port bias.
PMOS3 is connected using the drain electrode of diode fashion grid drain electrode and NMOS1, slow as current mirror bias driving voltage
Rush the output stage PMOS4 of device.
PMOS5 is connected using the drain electrode of diode fashion grid drain electrode and NMOS2, drives PMOS6 as current mirror.
The NMOS7 that the drain electrode of PMOS6 is connect with using diode is connected, and NMOS7 is slow as current mirror bias driving voltage
Rush the output stage NMOS8 of device.
The drain electrode of PMOS4 and the drain electrode of NMOS8 are connected to the output port VOUT of Push-pull-output stage.
Amplifier major loop is exported using push-pull type in the present embodiment, further improve the response speed of voltage buffer with
Driving capability.
As shown in figure 4, its adaptive-biased schematic diagram of voltage buffer, the grid of current source bias VB1 and PMOS tube M1
Connection, the source electrode of M1 meet power vd D, and the drain electrode of M1 is connect with the drain electrode of NMOS tube M2.The grid conduct of NMOS tube M2 is described certainly
The input VP_bias for adapting to biasing is connect with the non-inverting input terminal VP of amplifier major loop, the input terminal as voltage buffer
VIN.The source electrode of NMOS tube M2 is connect with the drain electrode of NMOS tube M3, as adaptive-biased electric current port IP_bias, NMOS tube
The source electrode of M3 is grounded, and the grid of NMOS tube M3 is connect with the drain electrode of the grid of NMOS tube M4 and M4, the source electrode ground connection of M4.
The grid of PMOS tube M5 is connect with Cascode (cascode stage) current source bias VB2, the drain electrode of M5 and the grid of M4
Pole, the drain electrode of M4, the grid connection of M3, the drain electrode of the source electrode and M1 of M5, the drain electrode of M2 connect.
Current source bias VB1 is connect with the grid of PMOS tube M1 ', and the source electrode of M1 ' meets power vd D, the drain electrode of M1 ' and NMOS
The drain electrode of pipe M2 ' connects.The grid of NMOS tube M2 ' is as the adaptive-biased input VN_bias and the amplifier main ring
The inverting input terminal VN connection on road, the input terminal VOUT as voltage buffer.The drain electrode of the source electrode and NMOS tube M3 ' of M2 ' connects
It connects, the source electrode as adaptive-biased electric current port IN_bias, M3 ' is grounded.The grid of NMOS tube M3 ' is with NMOS tube M4's '
The drain electrode of grid and M4 ' connect, the source electrode ground connection of M4 '.
The grid of PMOS tube M5 ' is connect with Cascode current source bias VB2, the grid of the drain electrode of M5 ' and M4 ', M4 '
Drain electrode, the grid connection of M3 ', the drain electrode of the source electrode and M1 ' of M5 ', the drain electrode of M2 ' connect.
The Cascode branch of the present embodiment adaptive bias circuit, can be effective when inputting common mode electrical level and changing bigger
Ground adjusts size of current, and the stabilization for controlling quiescent current does not change with common mode electrical level and changed, to realize that high input and output are dynamic
State range.
Fig. 3 and Fig. 4 gives the schematic diagram of adaptive bias circuit and amplifier major loop, by conventional push-pull in the present embodiment
The tail current source replacement of formula buffer is adaptive-biased to give amplifier major loop when inputting stable at adaptive bias source
The electric current of offer is stable.When input voltage VIN changes, the input variation of adaptive bias circuit will be increased dramatically
The tail current of amplifier major loop.
As shown in Figure 3 and Figure 4 when input voltage VIN increases, pass through IN_ in NMOS1 adaptive bias circuit in Fig. 3
Bias node voltage will increase and by transistor M2 ' and transistor M5 ' the grid step voltage of M3 ' be increased, and make amplifier loop
IP_bias current spikes increase and pass through current mirror PMOS3 and PMOS4 mirror image driving buffer output stage, guarantee voltage
Buffer energy quick response makes output VOUT follow VIN in time and increase, when output VOUT follows input VIN to stablize, M2 '
Grid voltage, which passes through the feedback loop that M2 ', M5 ', M4 ' and M3 ' are constituted, makes the current offset electric current of M3 ' with output voltage
The size for stablizing and reducing and being stabilized to before VIN variation.
When input voltage VIN reduces, the variation that VOUT quickly follows VIN is may be implemented in similar principle, and stablizes
Quiescent dissipation keeps stablizing afterwards, does not change with the variation of defeated common mode electrical level.Feedback loop in adaptive bias circuit,
Can be by the stabilization of the guarantee quiescent point of feedback loop when the variation of input voltage, that is, common mode input, while ring
The pole on road realizes the stability of loop by high resistant node and low-resistance node, and then controls the stabilization of quiescent current not with altogether
Mould level change and change.
Amplifier major loop, adaptive bias circuit can work at low supply voltages in the present embodiment, adapt to wide power
Voltage.
In addition to the circuit structure chosen in this present embodiment, including amplifier major loop and adaptive bias circuit its to electricity
Source voltage highest demand is Vth+3Vds, and wherein Vth is metal-oxide-semiconductor threshold voltage, and Vds is metal-oxide-semiconductor source-drain voltage, that is, this reality
Applying example can work at low supply voltages, adapt to wide power voltage.
Above embodiments are only to illustrate the technical solution of the utility model, rather than its limitations；Although referring to aforementioned reality
Example is applied the utility model is described in detail, those skilled in the art should understand that: it still can be to preceding
Technical solution documented by each embodiment is stated to modify or equivalent replacement of some of the technical features；And these
It modifies or replaces, the spirit and model of various embodiments of the utility model technical solution that it does not separate the essence of the corresponding technical solution
It encloses.
Claims (8)
1. a kind of voltage buffer circuit, it is characterised in that: the voltage buffer circuit includes amplifier major loop and adaptive
Biasing, the non-inverting input terminal VP of the amplifier major loop are connect with input voltage VIN, inverting input terminal VN and output end VOUT
Connection；The adaptive-biased input VP_bias is connect with the non-inverting input terminal VP of the amplifier major loop, inputs VN_
Bias is connect with the inverting input terminal VN of the amplifier major loop；The electric current port IP_amp of the amplifier major loop and it is described from
Adapt to the electric current port IN_bias connection of biasing, electric current port IN_amp and the adaptive-biased electric current port IP_
Bias connection.
2. voltage buffer circuit according to claim 1, it is characterised in that: the amplifier major loop includes input difference
To, current mirror and Push-pull-output stage.
3. voltage buffer circuit according to claim 2, it is characterised in that: the input difference centering of the amplifier major loop
The grid of one input metal-oxide-semiconductor is connect with the non-inverting input terminal VP of amplifier major loop, the electric current port of source electrode and amplifier major loop
IP_amp connection；The input difference connect the grid of another input metal-oxide-semiconductor with the inverting input terminal VN of amplifier major loop, source
Pole is connect with the electric current port IN_amp of amplifier major loop.
4. voltage buffer circuit according to claim 1, it is characterised in that: the adaptive-biased current source bias
VB1 is connect with the grid of PMOS tube M1 and PMOS tube M1 ' respectively, and the adaptive-biased Cascode current source bias VB2 points
It is not connected with the grid of PMOS tube M5 and PMOS tube M5 '.
5. voltage buffer circuit according to claim 4, it is characterised in that: it is described it is adaptive-biased in:
The source electrode of the PMOS tube M1 meets power vd D, and drain electrode is connect with the drain electrode of NMOS tube M2；
Non-inverting input terminal of the grid of the NMOS tube M2 as adaptive-biased the input VP_bias and amplifier major loop
VP connection, source electrode are connect with the drain electrode of NMOS tube M3；
The source electrode of the NMOS tube M3 is grounded, and the grid and drain electrode of grid and NMOS tube M4 connect, the source of the NMOS tube M4
Pole ground connection；
The drain electrode of the PMOS tube M5 is connect with the grid of the grid of NMOS tube M4 and drain electrode and NMOS tube M3, source electrode with
PMOS tube M1 is connected with the drain electrode of NMOS tube M2.
6. voltage buffer circuit according to claim 5, it is characterised in that: the source electrode and the NMOS of the NMOS tube M2
The adaptive-biased electric current port IP_bias is drawn in the drain electrode of pipe M3.
7. voltage buffer circuit according to claim 4, it is characterised in that: it is described it is adaptive-biased in:
The source electrode of the PMOS tube M1 ' meets power vd D, and drain electrode is connect with the drain electrode of NMOS tube M2 '；
Anti-phase input of the grid of the NMOS tube M2 ' as adaptive-biased the input VN_bias and amplifier major loop
VN connection is held, source electrode is connect with the drain electrode of NMOS tube M3 '；
The source electrode of the NMOS tube M3 ' is grounded, and the grid and drain electrode of grid and NMOS tube M4 ' connect, the NMOS tube M4's '
Source electrode ground connection；
PMOS tube M5 ' the drain electrode is connect with the grid of the grid of the NMOS tube M4 ' and drain electrode and NMOS tube M3 ', source
Pole is connect with the drain electrode of the PMOS tube M1 ' and NMOS tube M2 '.
8. voltage buffer circuit according to claim 7, it is characterised in that: the source electrode of the NMOS tube M2 ' with it is described
The adaptive-biased electric current port IN_bias is drawn in the drain electrode of NMOS tube M3 '.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821753999.7U CN209265310U (en) | 2018-10-26 | 2018-10-26 | A kind of voltage buffer circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821753999.7U CN209265310U (en) | 2018-10-26 | 2018-10-26 | A kind of voltage buffer circuit |
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| CN209265310U true CN209265310U (en) | 2019-08-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109101069A (en) * | 2018-10-26 | 2018-12-28 | 上海海栎创微电子有限公司 | A kind of voltage buffer circuit |
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2018
- 2018-10-26 CN CN201821753999.7U patent/CN209265310U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109101069A (en) * | 2018-10-26 | 2018-12-28 | 上海海栎创微电子有限公司 | A kind of voltage buffer circuit |
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Address after: Room 411, 4th floor, main building, No. 835 and 937, Dangui Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 200131 Patentee after: Shanghai hailichuang Technology Co.,Ltd. Address before: 201203 Room 411, 4th Floor, Main Building (1 Building) of Zhangjiang Guochuang Center, 899 Dangui Road, Pudong New Area, Shanghai Patentee before: SHANGHAI HYNITRON MICROELECTRONIC Co.,Ltd. |
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