CN109101069A - A kind of voltage buffer circuit - Google Patents
A kind of voltage buffer circuit Download PDFInfo
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- CN109101069A CN109101069A CN201811260784.6A CN201811260784A CN109101069A CN 109101069 A CN109101069 A CN 109101069A CN 201811260784 A CN201811260784 A CN 201811260784A CN 109101069 A CN109101069 A CN 109101069A
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- nmos tube
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- major loop
- drain electrode
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- 230000003044 adaptive effect Effects 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 7
- 230000005611 electricity Effects 0.000 description 5
- 230000006641 stabilisation Effects 0.000 description 4
- 238000011105 stabilization Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Abstract
The present invention relates to technical field of integrated circuits, more particularly to a kind of voltage buffer circuit, the voltage buffer circuit includes amplifier major loop and adaptive-biased, and the non-inverting input terminal VP of the amplifier major loop is connect with input voltage VIN, and inverting input terminal VN is connect with output end VOUT；The adaptive-biased input VP_bias is connect with the non-inverting input terminal VP of the amplifier major loop, and input VN_bias is connect with the inverting input terminal VN of the amplifier major loop；The electric current port IP_amp of the amplifier major loop is connect with the adaptive-biased electric current port IN_bias, its electric current port IN_amp is connect with the adaptive-biased electric current port IP_bias, the present invention is using adaptive-biased in conjunction with amplifier, improve response speed and driving capability, there is high input and output dynamic range simultaneously, adapt to wide power voltage work, low-power consumption.
Description
Technical field
The present invention relates to technical field of integrated circuits, and in particular to a kind of voltage buffer circuit.
Background technique
Voltage buffer (voltage buffer) is often used in voltage needed for providing some circuit work, to enhance
The driving capability of echo signal, while the interference shadow to previous stage circuit output voltage can also be loaded to avoid voltage buffer
It rings.Therefore voltage buffer, which has, extremely widely applies.For example, needing in capacitance touch control chip using voltage
Buffer drives heavy load capacitor and requires fast and stable；For another example, the source electrode driver in liquid crystal display is needed using electricity
Compression buffer provides stable common-mode voltage.
In the prior art, voltage buffer (referring to Fig. 1) is as all Analogous Integrated Electronic Circuits, by Analog Circuit Design
Octagon rule limitation, need to weigh between each performance.In recent years, in consumer electronics sector, chip operation electricity
Press lower and lower, power consumption is smaller and smaller.For voltage buffer, designer is in its low-power consumption, low-voltage, high-speed, small core
The case where piece area etc. has carried out research optimization, is commonly present a certain performance and improves, and other performance declines.
Summary of the invention
In view of the deficiencies of the prior art, the invention discloses a kind of voltage buffer circuits, are not increasing chip power-consumption
And under the premise of chip area, capacitive load driving capability is enhanced, and the voltage buffer can work in wide power electricity
Pressure, there is high input and output dynamic range.
The present invention is achieved by the following technical programs:
A kind of voltage buffer circuit, the voltage buffer circuit include amplifier major loop and adaptive-biased, described
The non-inverting input terminal VP of amplifier major loop is connect with input voltage VIN, and inverting input terminal VN is connect with output end VOUT；It is described
Adaptive-biased input VP_bias is connect with the non-inverting input terminal VP of the amplifier major loop, input VN_bias with it is described
The inverting input terminal VN connection of amplifier major loop；The electric current port IP_amp of the amplifier major loop and described adaptive-biased
The IN_bias connection of electric current port, electric current port IN_amp are connect with the adaptive-biased electric current port IP_bias.
Preferably, the amplifier major loop includes input difference to, current mirror and Push-pull-output stage.
Preferably, the grid of the input difference centering of the amplifier major loop one input metal-oxide-semiconductor and amplifier major loop
Non-inverting input terminal VP connection, source electrode are connect with the electric current port IP_amp of amplifier major loop；The input difference is to another input
The grid of metal-oxide-semiconductor is connect with the inverting input terminal VN of amplifier major loop, and the electric current port IN_amp of source electrode and amplifier major loop connects
It connects.
Preferably, the adaptive-biased current source bias VB1 connects with the grid of PMOS tube M1 and PMOS tube M1 ' respectively
It connects, the adaptive-biased Cascode current source bias VB2 is connected with the grid of PMOS tube M5 and PMOS tube M5 ' respectively.
Preferably, it is described it is adaptive-biased in:
The source electrode of the PMOS tube M1 meets power vd D, and drain electrode is connect with the drain electrode of NMOS tube M2；
The grid of the NMOS tube M2 is same mutually defeated as the adaptive-biased input VP_bias and amplifier major loop
Enter VP is held to connect, source electrode is connect with the drain electrode of NMOS tube M3；
The source electrode of the NMOS tube M3 is grounded, and the grid and drain electrode of grid and NMOS tube M4 connect, the NMOS tube M4
Source electrode ground connection；
The drain electrode of the PMOS tube M5 is connect with the grid of the grid of NMOS tube M4 and drain electrode and NMOS tube M3, source electrode
It is connect with the drain electrode of PMOS tube M1 and NMOS tube M2.
Preferably, the adaptive-biased electric current is drawn in the drain electrode of the source electrode of the NMOS tube M2 and the NMOS tube M3
Port IP _ bias.
Preferably, it is described it is adaptive-biased in:
The source electrode of the PMOS tube M1 ' meets power vd D, and drain electrode is connect with the drain electrode of NMOS tube M2 '；
Reverse phase of the grid of the NMOS tube M2 ' as adaptive-biased the input VN_bias and amplifier major loop
Input terminal VN connection, source electrode are connect with the drain electrode of NMOS tube M3 '；
The source electrode of the NMOS tube M3 ' is grounded, and the grid and drain electrode of grid and NMOS tube M4 ' connect, the NMOS tube
The source electrode of M4 ' is grounded；
PMOS tube M5 ' the drain electrode is connect with the grid of the grid of the NMOS tube M4 ' and drain electrode and NMOS tube M3 ',
Its source electrode is connect with the drain electrode of the PMOS tube M1 ' and NMOS tube M2 '.
Preferably, the adaptive-biased electricity is drawn in the drain electrode of the source electrode of the NMOS tube M2 ' and the NMOS tube M3 '
Flow port IN_bias.
The invention has the benefit that
1) present invention is by using adaptive bias, and when input voltage VIN variation, adaptive bias will be anxious
Increase severely and add, can guarantee voltage buffer quick response, enables to export the variation that VOUT follows VIN in time；And work as input and output one
Denier is stablized, size of current when bias current will be reduced to original static state, to be increased without any quiescent dissipation and improve voltage
The response speed and driving capability of buffer.
2) the Cascode branch of adaptive bias circuit of the present invention, can be effective when inputting common mode electrical level and changing bigger
Ground adjusts size of current, and the stabilization for controlling quiescent current does not change with common mode electrical level and changed, to realize that high input and output are dynamic
State range.
3) present invention in amplifier major loop using push-pull type export, further improve voltage buffer response speed and
Driving capability.
4) amplifier major loop, adaptive bias circuit can work at low supply voltages in the present invention, adapt to wide power
Voltage range work.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is traditional voltage buffer circuit schematic diagram；
Fig. 2 is the schematic diagram of voltage buffer circuit of the present invention；
Fig. 3 is the amplifier major loop circuit diagram of voltage buffer of the present invention；
Fig. 4 is the adaptive bias circuit schematic diagram of voltage buffer of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.
As shown in Fig. 2, a kind of voltage buffer circuit schematic diagram of the invention, including amplifier major loop and it is adaptive partially
It sets, the non-inverting input terminal VP of amplifier major loop is connect with input voltage VIN, the inverting input terminal VN and output end of amplifier major loop
VOUT connection；Adaptive-biased input VP_bias is connect with the non-inverting input terminal VP of amplifier major loop, and adaptive-biased is defeated
The inverting input terminal VN for entering VN_bias and amplifier major loop is connected to the output end VOUT of voltage buffer circuit；Amplifier master
The electric current port IP_amp of loop is connect with adaptive-biased electric current port IN_bias, the electric current port IN_ of amplifier major loop
Amp is connect with adaptive-biased electric current port IP_bias.
The present embodiment is by using adaptive bias, and when input voltage VIN variation, adaptive bias will be anxious
Increase severely and add, can guarantee voltage buffer quick response, enables to export the variation that VOUT follows VIN in time；And work as input and output one
Denier is stablized, size of current when bias current will be reduced to original static state, to be increased without any quiescent dissipation and improve voltage
The response speed and driving capability of buffer.
As shown in figure 3, the amplifier major loop of voltage buffer includes input difference to, current mirror and Push-pull-output stage.
The input difference pair of amplifier major loop, non-inverting input terminal VP of the grid of one of input NMOS1 pipe as amplifier major loop
It is connect with the port buffer VIN, electric current port IP_amp and adaptive-biased IN_ of the source electrode of NMOS1 as amplifier major loop
The connection of the port bias；Differential pair it is another input NMOS2 pipe grid as amplifier major loop inverting input terminal VN with connect delay
Rush the connection of the port device VOUT, electric current port IN_amp and adaptive-biased IP_ of the source electrode of NMOS2 as amplifier major loop
The connection of the port bias.
PMOS3 is connected using the drain electrode of diode fashion grid drain electrode and NMOS1, slow as current mirror bias driving voltage
Rush the output stage PMOS4 of device.
PMOS5 is connected using the drain electrode of diode fashion grid drain electrode and NMOS2, drives PMOS6 as current mirror.
The NMOS7 that the drain electrode of PMOS6 is connect with using diode is connected, and NMOS7 is slow as current mirror bias driving voltage
Rush the output stage NMOS8 of device.
The drain electrode of PMOS4 and the drain electrode of NMOS8 are connected to the output port VOUT of Push-pull-output stage.
Amplifier major loop is exported using push-pull type in the present embodiment, further improve the response speed of voltage buffer with
Driving capability.
As shown in figure 4, its adaptive-biased schematic diagram of voltage buffer, the grid of current source bias VB1 and PMOS tube M1
Connection, the source electrode of M1 meet power vd D, and the drain electrode of M1 is connect with the drain electrode of NMOS tube M2.The grid conduct of NMOS tube M2 is described certainly
The input VP_bias for adapting to biasing is connect with the non-inverting input terminal VP of amplifier major loop, the input terminal as voltage buffer
VIN.The source electrode of NMOS tube M2 is connect with the drain electrode of NMOS tube M3, as adaptive-biased electric current port IP_bias, NMOS tube
The source electrode of M3 is grounded, and the grid of NMOS tube M3 is connect with the drain electrode of the grid of NMOS tube M4 and M4, the source electrode ground connection of M4.
The grid of PMOS tube M5 is connect with Cascode (cascode stage) current source bias VB2, the drain electrode of M5 and the grid of M4
Pole, the drain electrode of M4, the grid connection of M3, the drain electrode of the source electrode and M1 of M5, the drain electrode of M2 connect.
Current source bias VB1 is connect with the grid of PMOS tube M1 ', and the source electrode of M1 ' meets power vd D, the drain electrode of M1 ' and NMOS
The drain electrode of pipe M2 ' connects.The grid of NMOS tube M2 ' is as the adaptive-biased input VN_bias and the amplifier main ring
The inverting input terminal VN connection on road, the input terminal VOUT as voltage buffer.The drain electrode of the source electrode and NMOS tube M3 ' of M2 ' connects
It connects, the source electrode as adaptive-biased electric current port IN_bias, M3 ' is grounded.The grid of NMOS tube M3 ' is with NMOS tube M4's '
The drain electrode of grid and M4 ' connect, the source electrode ground connection of M4 '.
The grid of PMOS tube M5 ' is connect with Cascode current source bias VB2, the grid of the drain electrode of M5 ' and M4 ', M4 '
Drain electrode, the grid connection of M3 ', the drain electrode of the source electrode and M1 ' of M5 ', the drain electrode of M2 ' connect.
The Cascode branch of the present embodiment adaptive bias circuit, can be effective when inputting common mode electrical level and changing bigger
Ground adjusts size of current, and the stabilization for controlling quiescent current does not change with common mode electrical level and changed, to realize that high input and output are dynamic
State range.
Fig. 3 and Fig. 4 gives the schematic diagram of adaptive bias circuit and amplifier major loop, by conventional push-pull in the present embodiment
The tail current source replacement of formula buffer is adaptive-biased to give amplifier major loop when inputting stable at adaptive bias source
The electric current of offer is stable.When input voltage VIN changes, the input variation of adaptive bias circuit will be increased dramatically
The tail current of amplifier major loop.
As shown in Figure 3 and Figure 4 when input voltage VIN increases, pass through IN_ in NMOS1 adaptive bias circuit in Fig. 3
Bias node voltage will increase and by transistor M2 ' and transistor M5 ' the grid step voltage of M3 ' be increased, and make amplifier loop
IP_bias current spikes increase and pass through current mirror PMOS3 and PMOS4 mirror image driving buffer output stage, guarantee voltage
Buffer energy quick response makes output VOUT follow VIN in time and increase, when output VOUT follows input VIN to stablize, M2 '
Grid voltage, which passes through the feedback loop that M2 ', M5 ', M4 ' and M3 ' are constituted, makes the current offset electric current of M3 ' with output voltage
The size for stablizing and reducing and being stabilized to before VIN variation.
When input voltage VIN reduces, the variation that VOUT quickly follows VIN is may be implemented in similar principle, and stablizes
Quiescent dissipation keeps stablizing afterwards, does not change with the variation of defeated common mode electrical level.Feedback loop in adaptive bias circuit,
Can be by the stabilization of the guarantee quiescent point of feedback loop when the variation of input voltage, that is, common mode input, while ring
The pole on road realizes the stability of loop by high resistant node and low-resistance node, and then controls the stabilization of quiescent current not with altogether
Mould level change and change.
Amplifier major loop, adaptive bias circuit can work at low supply voltages in the present embodiment, adapt to wide power
Voltage.
In addition to the circuit structure chosen in this present embodiment, including amplifier major loop and adaptive bias circuit its to electricity
Source voltage highest demand is Vth+3Vds, and wherein Vth is metal-oxide-semiconductor threshold voltage, and Vds is metal-oxide-semiconductor source-drain voltage, that is, this reality
Applying example can work at low supply voltages, adapt to wide power voltage.
The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to the foregoing embodiments
Invention is explained in detail, those skilled in the art should understand that: it still can be to aforementioned each implementation
Technical solution documented by example is modified or equivalent replacement of some of the technical features；And these modification or
Replacement, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (8)
1. a kind of voltage buffer circuit, it is characterised in that: the voltage buffer circuit includes amplifier major loop and adaptive
Biasing, the non-inverting input terminal VP of the amplifier major loop are connect with input voltage VIN, inverting input terminal VN and output end VOUT
Connection；The adaptive-biased input VP_bias is connect with the non-inverting input terminal VP of the amplifier major loop, inputs VN_
Bias is connect with the inverting input terminal VN of the amplifier major loop；The electric current port IP_amp of the amplifier major loop and it is described from
Adapt to the electric current port IN_bias connection of biasing, electric current port IN_amp and the adaptive-biased electric current port IP_
Bias connection.
2. voltage buffer circuit according to claim 1, it is characterised in that: the amplifier major loop includes input difference
To, current mirror and Push-pull-output stage.
3. voltage buffer according to claim 2, it is characterised in that: the input difference centering of the amplifier major loop one
The grid of input metal-oxide-semiconductor is connect with the non-inverting input terminal VP of amplifier major loop, the electric current port IP_ of source electrode and amplifier major loop
Amp connection；The input difference connect the grid of another input metal-oxide-semiconductor with the inverting input terminal VN of amplifier major loop, source electrode
It is connect with the electric current port IN_amp of amplifier major loop.
4. voltage buffer according to claim 1, it is characterised in that: the adaptive-biased current source bias VB1 points
Do not connect with the grid of PMOS tube M1 and PMOS tube M1 ', the adaptive-biased Cascode current source bias VB2 respectively with
PMOS tube M5 is connected with the grid of PMOS tube M5 '.
5. voltage buffer according to claim 1, it is characterised in that: it is described it is adaptive-biased in:
The source electrode of the PMOS tube M1 meets power vd D, and drain electrode is connect with the drain electrode of NMOS tube M2；
Non-inverting input terminal of the grid of the NMOS tube M2 as adaptive-biased the input VP_bias and amplifier major loop
VP connection, source electrode are connect with the drain electrode of NMOS tube M3；
The source electrode of the NMOS tube M3 is grounded, and the grid and drain electrode of grid and NMOS tube M4 connect, the source of the NMOS tube M4
Pole ground connection；
The drain electrode of the PMOS tube M5 is connect with the grid of the grid of NMOS tube M4 and drain electrode and NMOS tube M3, source electrode with
PMOS tube M1 is connected with the drain electrode of NMOS tube M2.
6. voltage buffer according to claim 5, it is characterised in that: the source electrode of the NMOS tube M2 and the NMOS tube M3
Drain electrode draw the adaptive-biased electric current port IP_bias.
7. voltage buffer according to claim 1, it is characterised in that: it is described it is adaptive-biased in:
The source electrode of the PMOS tube M1 ' meets power vd D, and drain electrode is connect with the drain electrode of NMOS tube M2 '；
Anti-phase input of the grid of the NMOS tube M2 ' as adaptive-biased the input VN_bias and amplifier major loop
VN connection is held, source electrode is connect with the drain electrode of NMOS tube M3 '；
The source electrode of the NMOS tube M3 ' is grounded, and the grid and drain electrode of grid and NMOS tube M4 ' connect, the NMOS tube M4's '
Source electrode ground connection；
PMOS tube M5 ' the drain electrode is connect with the grid of the grid of the NMOS tube M4 ' and drain electrode and NMOS tube M3 ', source
Pole is connect with the drain electrode of the PMOS tube M1 ' and NMOS tube M2 '.
8. voltage buffer according to claim 7, it is characterised in that: the source electrode of the NMOS tube M2 ' and the NMOS tube
The adaptive-biased electric current port IN_bias is drawn in the drain electrode of M3 '.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811260784.6A CN109101069A (en) | 2018-10-26 | 2018-10-26 | A kind of voltage buffer circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811260784.6A CN109101069A (en) | 2018-10-26 | 2018-10-26 | A kind of voltage buffer circuit |
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| CN109101069A true CN109101069A (en) | 2018-12-28 |
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| CN201811260784.6A Pending CN109101069A (en) | 2018-10-26 | 2018-10-26 | A kind of voltage buffer circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112034924A (en) * | 2020-08-10 | 2020-12-04 | 唯捷创芯(天津)电子技术股份有限公司 | Self-adaptive fast response LDO (low dropout regulator) circuit and chip thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6642791B1 (en) * | 2002-08-09 | 2003-11-04 | Lsi Logic Corporation | Self-biased amplifier circuit and method for self-basing amplifier circuit |
| US20080273106A1 (en) * | 2007-05-04 | 2008-11-06 | Micron Technology, Inc. | Class AB amplifier and imagers and systems using same |
| CN102571002A (en) * | 2010-12-10 | 2012-07-11 | 上海华虹集成电路有限责任公司 | Automatic-biasing structural operation amplifier applied to band gap reference source |
| CN104460807A (en) * | 2014-12-23 | 2015-03-25 | 电子科技大学 | Low-dropout linear regulator with self-adaptive reference buffer |
| CN104460802A (en) * | 2014-11-27 | 2015-03-25 | 电子科技大学 | Self-adapting current multiplication circuit and low-dropout-voltage linear voltage regulator integrating same |
| CN104901643A (en) * | 2015-06-10 | 2015-09-09 | 思瑞浦微电子科技（苏州）有限公司 | Low-voltage high-common-mode-rejection amplifier |
| US20170315574A1 (en) * | 2016-04-29 | 2017-11-02 | Cavium, Inc. | Voltage regulator with adaptive bias network |
| CN209265310U (en) * | 2018-10-26 | 2019-08-16 | 上海海栎创微电子有限公司 | A kind of voltage buffer circuit |
-
2018
- 2018-10-26 CN CN201811260784.6A patent/CN109101069A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6642791B1 (en) * | 2002-08-09 | 2003-11-04 | Lsi Logic Corporation | Self-biased amplifier circuit and method for self-basing amplifier circuit |
| US20080273106A1 (en) * | 2007-05-04 | 2008-11-06 | Micron Technology, Inc. | Class AB amplifier and imagers and systems using same |
| CN102571002A (en) * | 2010-12-10 | 2012-07-11 | 上海华虹集成电路有限责任公司 | Automatic-biasing structural operation amplifier applied to band gap reference source |
| CN104460802A (en) * | 2014-11-27 | 2015-03-25 | 电子科技大学 | Self-adapting current multiplication circuit and low-dropout-voltage linear voltage regulator integrating same |
| CN104460807A (en) * | 2014-12-23 | 2015-03-25 | 电子科技大学 | Low-dropout linear regulator with self-adaptive reference buffer |
| CN104901643A (en) * | 2015-06-10 | 2015-09-09 | 思瑞浦微电子科技（苏州）有限公司 | Low-voltage high-common-mode-rejection amplifier |
| US20170315574A1 (en) * | 2016-04-29 | 2017-11-02 | Cavium, Inc. | Voltage regulator with adaptive bias network |
| CN209265310U (en) * | 2018-10-26 | 2019-08-16 | 上海海栎创微电子有限公司 | A kind of voltage buffer circuit |
Non-Patent Citations (1)
| Title |
|---|
| ANTONIO J. LÓPEZ-MARTÍN等: "Low-Voltage Super Class AB CMOS OTA Cells With Very High Slew Rate and Power Efficiency", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 40, no. 5, pages 1068 - 1077, XP011131304, DOI: 10.1109/JSSC.2005.845977 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112034924A (en) * | 2020-08-10 | 2020-12-04 | 唯捷创芯(天津)电子技术股份有限公司 | Self-adaptive fast response LDO (low dropout regulator) circuit and chip thereof |
| CN112034924B (en) * | 2020-08-10 | 2023-02-24 | 唯捷创芯(天津)电子技术股份有限公司 | Self-adaptive fast response LDO (low dropout regulator) circuit and chip thereof |
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