CN101222216A

CN101222216A - Comparator

Info

Publication number: CN101222216A
Application number: CNA200710036622XA
Authority: CN
Inventors: 曹先国
Original assignee: Individual
Current assignee: Individual
Priority date: 2007-01-13
Filing date: 2007-01-13
Publication date: 2008-07-16

Abstract

The invention provides a comparator, which consists of a preamplifier, a latch unit and a buffer which are under the accurate control of a clock. During the falling edge of the clock, accurate comparison of the voltage input from both ends is completed; moreover, up level or low level is output as the result of judgment according to needs; then, the invention quickly returns to a reference comparative level before clock signal arrives, and ensures that the previous comparison result does not influence the following comparison, thereby enlarging the voltage amplitude scope and level switching rate of the comparator.

Description

Comparator

Affiliated technical field

The present invention relates to comparator circuit.Especially, it relates to a kind of comparator circuit of accurately being controlled, two input voltage sizes are judged and embodied with high level or low level mode comparative result by clock.

Background technology

One of signal processing most important function is changed between analog and digital signal exactly, and comparator just is widely used in analog signal in the transfer process of digital signal.In the analog-to-digital conversion process, at first must sample to input.Then, through the signal of over-sampling by comparator with decision Analog signals'digital value.Under the simplest situation, comparator can be used as 1 analog-digital converter, represents the comparative result of two input signals by output high level or low level.

The technology that the relates to comparative maturity of present comparator, mainly contain open loop comparator based on non-compensated operational amplifier, the regenerative amplifier that two signal amplitudes are compared is finished in the positive feedback that is similar to sensor amplifier or trigger, and in conjunction with the comprehensive comparator of both advantages.

Yet it is in above listed various comparators, actually rare based on the type that clock is accurately controlled; Consider in the various designs of clock effect, lack necessary level return technique again, thereby under two input voltages change rapidly situation, can not obtain correct result, thereby limit voltage amplitude scope and level conversion speed that comparator is used.

Summary of the invention

The present invention is and addresses the above problem proposition.The comparator circuit that the present invention proposes, both can measure the very little situation of two input voltage differences by preposition amplification, again by latch and buffer, the transmission gate circuit in the latch particularly, when the clock signal no show, return the benchmark comparative level rapidly, make the comparative result last time can be, thereby enlarged voltage amplitude scope and level conversion speed that comparator is used follow-up relatively not exerting an influence.

The present invention is achieved through the following technical solutions:

A kind of comparator is accurately controlled by clock, and the voltage to two inputs when the clock trailing edge arrives accurately compares, and exports high level or low level as required as the result who judges, it is characterized in that, comprising:

Preamplifier, critical piece are differential pair PMOS pipe, and the grid of metal-oxide-semiconductor connects two voltage Vin1 and Vin2 as signal input part, and the drain electrode of metal-oxide-semiconductor is amplified two voltage signals of importing as signal output part;

Latch, form by NMOS pipe and current source that differential pair PMOS pipe, transmission gate are connected with pair of cross, signal input part connects the output of preamplifier, under the accurate control of clock signal, certain interval of time compares the size of two input signals, and transfers to buffer after this result latched;

Buffer is made up of PMOS pipe and a pair of metal-oxide-semiconductor that pair of cross connects, and compared result cushions output;

The clock treatment circuit is handled clock signal, and the transmission gate of control lock storage thus;

Biasing circuit is made up of one group of metal-oxide-semiconductor that the current source mode connects, for preamplifier and latch provide driving.

Described preamplifier comprises with the lower part:

Current source is connected between power supply VDD and the differential pair PMOS pipe, can be made of the PMOS pipe that the common source mode connects biasing circuit first output, also can be made of other devices that is equal to constant current source;

Differential pair PMOS pipe is connected between current source and the current source load, and the grid of metal-oxide-semiconductor connects two voltage Vin1 and Vin2 as signal input part, and the drain electrode of metal-oxide-semiconductor is amplified two voltage signals of importing, and transferred to buffer as signal output part;

Current source load is made up of a pair of NMOS pipe that connects biasing circuit second output, and the NMOS pipe is connected between the drain electrode and ground GND of differential pair PMOS pipe.

Described latch comprises with the lower part:

Current source is connected between power supply VDD and the differential pair PMOS pipe, can be made of the PMOS pipe that the common source mode connects, and also can be made of other devices that is equal to constant current source;

Differential pair PMOS pipe is connected between current source and the transmission gate, and grid connects the signal output part of preamplifier, and drain electrode connects transmission gate and is connected to buffer as output;

Transmission gate is subjected to the clock processing circuit controls, and signal path is connected between two drain electrodes of differential pair PMOS pipe;

The NMOS pipe that pair of cross connects, drain electrode connects the drain electrode of differential pair PMOS pipe, that is the signal path two ends of transmission gate, and source electrode and grid interconnection also are connected on the ground GND.

Described buffer comprises with the lower part:

The PMOS pipe that pair of cross connects, source electrode connects the interconnection of power supply VDD drain and gate, and the signal output of device as a comparison, connect a pair of metal-oxide-semiconductor simultaneously, should be to cross-coupled PMOS pipe, can adopt the cross-coupled drain and gate signal output of device as a comparison of any branch road, also can adopt the cross-coupled drain and gate signal output of device as a comparison of two branch roads simultaneously;

A pair of metal-oxide-semiconductor, grid are as the signal output part of signal input part connection latch, and drain electrode connects the PMOS pipe that pair of cross connects, source electrode connection ground GND.

Described clock treatment circuit is composed in series by two reversers, the P control end of the output control lock storage transmission gate of first reverser, the N control end of the output control lock storage transmission gate of second reverser.

Described biasing circuit is formed in parallel to the PMOS pipe-NMOS pipe branch road that the common source with one group of series connection is connected by the metal-oxide-semiconductor that two groups of current mirror modes of connecting connect, the metal-oxide-semiconductor that the current mirror mode connects is to respectively there being end output, the PMOS pipe that connects of the common source mode of control series connection and the grid of NMOS pipe respectively, and provide driving to preamplifier and latch as output.

Industrial utilization and possibility of its application

Comparator of the present invention can be applied to but be not limited to signal processing, and particularly analog signal is in the transfer process of digital signal in all ranges of application and occasion related to the present invention.

Claims

1. a comparator is accurately controlled by clock, and the voltage to two inputs when the clock trailing edge arrives accurately compares, and exports high level or low level as required as the result who judges, it is characterized in that, comprising:

2. a kind of comparator according to claim 1, it is characterized in that, described preamplifier, comprise with the lower part: current source, be connected between power supply VDD and the differential pair PMOS pipe, can constitute by the PMOS pipe that the common source mode connects biasing circuit first output, also can constitute by other devices that is equal to constant current source;

3. a kind of comparator according to claim 1, it is characterized in that, described latch, comprise with the lower part: current source, be connected between power supply VDD and the differential pair PMOS pipe, can constitute by the PMOS pipe that the common source mode connects, also can constitute by other devices that is equal to constant current source;

4. a kind of comparator according to claim 1 is characterized in that, described buffer comprises with the lower part:

The PMOS pipe that pair of cross connects, source electrode connects power supply VDD, and drain and gate interconnection, and the signal output of device as a comparison connect a pair of metal-oxide-semiconductor simultaneously;

5. according to claim 1,4 described a kind of comparators, it is characterized in that, the PMOS pipe that pair of cross connects in the described buffer, can adopt the cross-coupled drain and gate signal output of device as a comparison of any branch road, also can adopt the cross-coupled drain and gate signal output of device as a comparison of two branch roads simultaneously.

6. a kind of comparator according to claim 1, it is characterized in that described clock treatment circuit is composed in series by two reversers, the P control end of the output control lock storage transmission gate of first reverser, the N control end of the output control lock storage transmission gate of second reverser.

7. a kind of comparator according to claim 1, it is characterized in that, described biasing circuit is formed in parallel to the PMOS pipe-NMOS pipe branch road that the common source with one group of series connection is connected by the metal-oxide-semiconductor that two groups of current mirror modes of connecting connect, the metal-oxide-semiconductor that the current mirror mode connects is to respectively there being end output, the PMOS pipe that connects of the common source mode of control series connection and the grid of NMOS pipe respectively, and provide driving to preamplifier and latch as output.