CN105703744A - Multistage time delay circuit - Google Patents
Multistage time delay circuit Download PDFInfo
- Publication number
- CN105703744A CN105703744A CN201610029621.1A CN201610029621A CN105703744A CN 105703744 A CN105703744 A CN 105703744A CN 201610029621 A CN201610029621 A CN 201610029621A CN 105703744 A CN105703744 A CN 105703744A
- Authority
- CN
- China
- Prior art keywords
- circuit
- pmos
- connects
- nmos tube
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
- H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
Abstract
The invention provides a multistage time delay circuit characterized by comprising at least a first-stage circuit composed of a PMOS transistor Q1 and a NMOS transistor Q2, and a second-stage circuit composed of a PMOS transistor Q3 and a NMOS transistor Q4. The PMOS transistor Q1 and the NMOS transistor Q2 are connected in series between a power end and a ground end. The PMOS transistor Q3 and the NMOS transistor Q4 are connected in series between the power end and the ground end. The output end of each stage of the circuits is provided with a filter capacitor. The multistage time delay circuit is small in size and excellent in voltage withstand performance. Performance can be obviously improved when every stage of circuit is added. Each MOS transistor is stable in electrical performance and has a long service life. The multistage time delay circuit is very suitable for large-scale chip integrated circuits.
Description
Technical field
The present invention relates to a kind of for the multistage time delay circuit in chip integrated circuit。
Background technology
Commonly use time delay function in the middle of chip integrated circuit, impact for all kinds of clock alignments in circuit or buffering surge。Relatively frequently with mode be multiple phase inverters of series connection, each phase inverter realizes the delay of a time, but the preferably buffering effect often demand that reaches has multiple phase inverter, not only increases the volume of circuit, and the pressure performance of phase inverter is not outstanding yet。Comparatively speaking, a kind of switch element of metal-oxide-semiconductor has the features such as little, the pressure excellent performance of volume, therefore the present invention utilizes metal-oxide-semiconductor to realize a kind of time delay circuit。
Summary of the invention
The present invention proposes a kind of multistage time delay circuit, and for overcoming technical problem mentioned in background technology, its concrete technical scheme is as follows:
A kind of multistage time delay circuit, at least include the first order circuit being made up of PMOS Q1 and NMOS tube Q2, the second level circuit being made up of PMOS Q3 and NMOS tube Q4, described PMOS Q1 and NMOS tube Q2, PMOS Q3 and NMOS tube Q4 are connected in series between power end and ground end respectively, and the outfan of circuit at different levels is provided with filter capacitor。
In the middle of one or more embodiments of the invention, described power end is connected to voltage source or the current source of direct current。
In the middle of one or more embodiments of the invention, the source electrode of described PMOS Q1 connects described power end, its drain electrode connects the source electrode of described NMOS tube Q2, the drain electrode of described NMOS tube Q2 connects earth terminal, the grid of the two is connected to the input of this grade of circuit altogether, the drain electrode of PMOS Q1 connects the outfan of this grade of circuit, and is provided with filter capacitor C1 in outfan；The source electrode of described PMOS Q3 connects described power end, its drain electrode connects the source electrode of described NMOS tube Q4, the drain electrode of described NMOS tube Q4 connects earth terminal, the grid of the two is connected to the input of this grade of circuit altogether, the drain electrode of PMOS Q1 connects the outfan of this grade of circuit, and is provided with filter capacitor C2 in outfan。
In the middle of one or more embodiments of the invention, also include the tertiary circuit being made up of PMOS Q5 and NMOS tube Q6, the source electrode of described PMOS Q5 connects described power end, its drain electrode connects the source electrode of described NMOS tube Q6, the drain electrode of described NMOS tube Q6 connects earth terminal, the grid of the two is connected to the input of this grade of circuit altogether, and the drain electrode of PMOS Q5 connects the outfan of this grade of circuit, and is provided with filter capacitor C3 in outfan。
Circuit compact of the present invention, pressure excellent performance, often increase stage circuit performance and be comparatively obviously improved, and the electric property of metal-oxide-semiconductor element is stable, and the life-span is long, is very suitable in middle monster chip integrated circuit and uses。
Accompanying drawing explanation
Fig. 1 is the circuit theory diagrams of the multistage time delay circuit embodiment one of the present invention。
Fig. 2 is the circuit theory diagrams of the multistage time delay circuit embodiment two of the present invention。
Detailed description of the invention
Below in conjunction with accompanying drawing, the application scheme is further described:
As it is shown in figure 1, embodiments of the invention one:
A kind of multistage time delay circuit, at least include the first order circuit being made up of PMOS Q1 and NMOS tube Q2, the second level circuit being made up of PMOS Q3 and NMOS tube Q4, described PMOS Q1 and NMOS tube Q2, PMOS Q3 and NMOS tube Q4 are connected in series between power end and ground end respectively, and the outfan of circuit at different levels is provided with filter capacitor。
The source electrode of described PMOS Q1 connects described power end, its drain electrode connects the source electrode of described NMOS tube Q2, the drain electrode of described NMOS tube Q2 connects earth terminal, the grid of the two is connected to the input of this grade of circuit altogether, the drain electrode of PMOS Q1 connects the outfan of this grade of circuit, and is provided with filter capacitor C1 in outfan；The source electrode of described PMOS Q3 connects described power end, its drain electrode connects the source electrode of described NMOS tube Q4, the drain electrode of described NMOS tube Q4 connects earth terminal, the grid of the two is connected to the input of this grade of circuit altogether, the drain electrode of PMOS Q1 connects the outfan of this grade of circuit, and is provided with filter capacitor C2 in outfan。
Described power end is connected to voltage source or the current source of direct current。
As in figure 2 it is shown, embodiments of the invention two:
It is on the basis of above-described embodiment one, have additional the tertiary circuit being made up of PMOS Q5 and NMOS tube Q6, the source electrode of described PMOS Q5 connects described power end, its drain electrode connects the source electrode of described NMOS tube Q6, the drain electrode of described NMOS tube Q6 connects earth terminal, the grid of the two is connected to the input of this grade of circuit altogether, and the drain electrode of PMOS Q5 connects the outfan of this grade of circuit, and is provided with filter capacitor C3 in outfan。
Above-mentioned preferred implementation should be regarded as the illustration of the application scheme embodiment, all identical with the application scheme, approximate or make based on this technology deduction, replacement, improvement etc., be regarded as the protection domain of this patent。
Claims (4)
1. a multistage time delay circuit, it is characterized in that: at least include the first order circuit being made up of PMOS Q1 and NMOS tube Q2, the second level circuit being made up of PMOS Q3 and NMOS tube Q4, described PMOS Q1 and NMOS tube Q2, PMOS Q3 and NMOS tube Q4 are connected in series between power end and ground end respectively, and the outfan of circuit at different levels is provided with filter capacitor。
2. multistage time delay circuit according to claim 1, it is characterised in that: described power end is connected to voltage source or the current source of direct current。
3. multistage time delay circuit according to claim 2, it is characterized in that: the source electrode of described PMOS Q1 connects described power end, its drain electrode connects the source electrode of described NMOS tube Q2, the drain electrode of described NMOS tube Q2 connects earth terminal, the grid of the two is connected to the input of this grade of circuit altogether, the drain electrode of PMOS Q1 connects the outfan of this grade of circuit, and is provided with filter capacitor C1 in outfan；The source electrode of described PMOS Q3 connects described power end, its drain electrode connects the source electrode of described NMOS tube Q4, the drain electrode of described NMOS tube Q4 connects earth terminal, the grid of the two is connected to the input of this grade of circuit altogether, the drain electrode of PMOS Q1 connects the outfan of this grade of circuit, and is provided with filter capacitor C2 in outfan。
4. multistage time delay circuit according to claim 3, it is characterized in that: also include the tertiary circuit being made up of PMOS Q5 and NMOS tube Q6, the source electrode of described PMOS Q5 connects described power end, its drain electrode connects the source electrode of described NMOS tube Q6, the drain electrode of described NMOS tube Q6 connects earth terminal, the grid of the two is connected to the input of this grade of circuit altogether, and the drain electrode of PMOS Q5 connects the outfan of this grade of circuit, and is provided with filter capacitor C3 in outfan。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610029621.1A CN105703744A (en) | 2016-01-15 | 2016-01-15 | Multistage time delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610029621.1A CN105703744A (en) | 2016-01-15 | 2016-01-15 | Multistage time delay circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105703744A true CN105703744A (en) | 2016-06-22 |
Family
ID=56227515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610029621.1A Pending CN105703744A (en) | 2016-01-15 | 2016-01-15 | Multistage time delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105703744A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040257131A1 (en) * | 2003-06-17 | 2004-12-23 | Stefano Sivero | Regenerative clock repeater |
| CN101841315A (en) * | 2010-05-26 | 2010-09-22 | 中国电子科技集团公司第二十四研究所 | High speed comparator |
| CN103152017A (en) * | 2012-03-27 | 2013-06-12 | 成都芯源系统有限公司 | Delay circuit, circuit system with delay circuit and method thereof |
-
2016
- 2016-01-15 CN CN201610029621.1A patent/CN105703744A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040257131A1 (en) * | 2003-06-17 | 2004-12-23 | Stefano Sivero | Regenerative clock repeater |
| CN101841315A (en) * | 2010-05-26 | 2010-09-22 | 中国电子科技集团公司第二十四研究所 | High speed comparator |
| CN103152017A (en) * | 2012-03-27 | 2013-06-12 | 成都芯源系统有限公司 | Delay circuit, circuit system with delay circuit and method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160622 |