CN210405236U - Differential amplifier with high common-mode dynamic range and constant PVT - Google Patents
Differential amplifier with high common-mode dynamic range and constant PVT Download PDFInfo
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- CN210405236U CN210405236U CN201921825563.9U CN201921825563U CN210405236U CN 210405236 U CN210405236 U CN 210405236U CN 201921825563 U CN201921825563 U CN 201921825563U CN 210405236 U CN210405236 U CN 210405236U
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Abstract
The utility model discloses a high common mode dynamic range and invariable differential amplifier of PVT, differential amplifier includes invariable transconductance biasing circuit, differential amplifier circuit and input common mode component tracking compensation circuit, input common mode component tracking compensation circuit is used for extracting input signal's common mode component, invariable transconductance biasing circuit is used for providing bias voltage and electric current according to the common mode component that input common mode component tracking compensation circuit fed back to offset differential amplifier circuit's intrinsic gain along with PVT's change. The utility model discloses well invariable transconductance biasing circuit can offset the inherent gain of differential amplifier circuit along with PVT's change to reach the invariable characteristic of PVT, input common mode component tracking compensating circuit can draw input signal's common mode component, has enlarged differential amplifier circuit's common mode dynamic range.
Description
Technical Field
The utility model belongs to the technical field of integrated circuit, concretely relates to high common mode dynamic range and invariable differential amplifier of PVT.
Background
Amplifiers with high common mode dynamic range and PVT constancy have very wide application requirements in integrated circuit systems, for example, Low Voltage Differential Signaling (LVDS) receivers, which are widely used in the data interface of point-to-point data transmission links. The LVDS receiver generally needs to integrate a preset amplifier to improve the receiving sensitivity, although the input signal is in a differential form, a common-mode component inevitably exists, and when the common-mode component of the input signal exceeds a certain range, the LVDS receiver is easily saturated, so that the performance of the LVDS receiver is reduced. Therefore, the preset amplifier of LVDS needs to be able to provide a high common-mode dynamic range while having PVT-constant characteristics.
Therefore, in view of the above technical problems, it is necessary to provide a differential amplifier with high common mode dynamic range and constant PVT.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a high common mode dynamic range and invariable differential amplifier of PVT to solve the invariable problem of high common mode dynamic range and PVT in the prior art.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a differential amplifier with high common-mode dynamic range and constant PVT (voltage-to-noise ratio) comprises a constant transconductance biasing circuit, a differential amplifier circuit and an input common-mode component tracking compensation circuit, wherein the input common-mode component tracking compensation circuit is used for extracting common-mode components of input signals, and the constant transconductance biasing circuit is used for providing biasing voltage and current according to the common-mode components fed back by the input common-mode component tracking compensation circuit so as to counteract the variation of the inherent gain of the differential amplifier circuit along with the PVT.
In an embodiment, the constant transconductance biasing circuit includes a cascode current mirror and a bias current amplifying circuit, and the cascode current mirror includes a plurality of PMOS transistors, a plurality of NMOS transistors and a resistor RCThe bias current amplifying circuit comprises an operational amplifier, a resistor connected with two input ends of the operational amplifier and an NMOS tube connected with an output end of the operational amplifier.
In an embodiment, the cascode current mirror is used for providing a bias current, and includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a resistor RC；
The grid electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected, the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with a voltage VDD, the drain electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are respectively connected with the source electrodes of the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube, the grid electrodes of the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are connected, the drain electrodes of the fourth PMOS tube and the fifth PMOS tube are respectively connected with the drain electrodes of the first NMOS tube and the second NMOS tube, the drain electrode of the sixth PMOS tube is connected with a bias current amplifying circuit, the grid electrodes of the first NMOS tube and the second NMOS tube are connected, the source electrodes of the first NMOS tube and the second NMOS tube are respectively connected with the drain electrodes of the third NMOS tube and the fourth NMOS tube, the grid electrodes of the third NMOS tube and the fourth NMOS tube are connected, the source electrode of the third NMOS tube is connected with a voltage VSS, and the source electrode of the fourth NMOS tube is connected with a resistor RCAnd then the grid electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube, and the grid electrode of the third NMOS tube is connected with the drain electrode of the third NMOS tube.
In one embodiment, the bias current amplifying circuit is used for amplifying a bias current provided by the cascode current mirror, and comprises an operational amplifier, a first resistor and a second resistor which are connected with two input ends of the operational amplifier, and a ninth NMOS transistor connected with an output end of the operational amplifier;
the first input end and the second input end of the operational amplifier are connected with the first resistor and the second resistor respectively and then connected with the voltage VSS, the first input end is further connected with the drain electrode of the sixth PMOS tube, the output end of the operational amplifier is connected with the grid electrode of the ninth NMOS tube, the source electrode of the ninth NMOS tube is connected with the second input end of the operational amplifier, and the drain electrode of the ninth NMOS tube is connected with the differential amplifier circuit.
In one embodiment, the differential amplifier circuit comprises a plurality of PMOS tubes, a plurality of NMOS tubes and a plurality of resistors.
In one embodiment, the differential amplifier circuit includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a third resistor, and a fourth resistor;
the source electrodes of the fifth NMOS tube and the sixth NMOS tube are connected with the constant transconductance biasing circuit, the grid electrodes of the fifth NMOS tube and the sixth NMOS tube are respectively connected with the first signal input end and the second signal input end, the drain electrodes of the fifth NMOS tube and the sixth NMOS tube are respectively connected with the source electrodes of the seventh NMOS tube and the eighth NMOS tube, the grid electrodes of the seventh NMOS tube and the eighth NMOS tube are connected, the drain electrodes of the seventh NMOS tube and the eighth NMOS tube are respectively connected with the first signal output end and the second signal output end, the drain electrode of the seventh NMOS tube is connected with the third resistor and then connected with the voltage VDD, and the drain electrode of the eighth NMOS tube is connected with the fourth resistor and then connected with the voltage VDD.
In one embodiment, the input common mode component tracking compensation circuit comprises a PMOS tube and a plurality of resistors.
In one embodiment, the input common-mode component tracking compensation circuit includes a seventh PMOS transistor, a fifth resistor, a sixth resistor, and a seventh resistor, where the fifth resistor and the sixth resistor are used to extract a common-mode component of an input signal;
the source electrode of the seventh PMOS tube is connected with the fifth resistor and then connected with a voltage VDD, the grid electrode of the seventh PMOS tube is connected with the sixth resistor and the seventh resistor respectively and then connected with the first signal input end and the second signal input end, the drain electrode of the seventh PMOS tube is connected with a voltage VSS, and the source electrode of the seventh PMOS tube is connected with the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube.
In one embodiment, the cascode current mirror provides a bias current IbComprises the following steps:
wherein, βmThe transconductance coefficient of the third NMOS tube is shown, and K is the size ratio of the fourth NMOS tube to the third NMOS tube;
the amplification factor of the bias current amplification circuit is a, and a is the ratio of the first resistor to the second resistor.
In one embodiment, the voltage gain of the differential amplifier circuit is AVComprises the following steps:
wherein, βmIs the transconductance coefficient of the third NMOS transistor, K is the size ratio of the fourth NMOS transistor to the third NMOS transistor, βdTransconductance coefficients of a fifth NMOS transistor and a sixth NMOS transistor, a is an amplification coefficient of the bias current amplification circuit, and R is3Is the resistance of the third resistor.
Compared with the prior art, the utility model has the advantages of it is following:
the utility model discloses well invariable transconductance biasing circuit can offset the inherent gain of differential amplifier circuit along with PVT's change to reach the invariable characteristic of PVT, input common mode component tracking compensating circuit can draw input signal's common mode component, has enlarged differential amplifier circuit's common mode dynamic range.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic block diagram of a differential amplifier according to the present invention;
fig. 2 is a schematic circuit diagram of a differential amplifier according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. However, the present invention is not limited to the embodiments, and the structural, method, or functional changes made by those skilled in the art according to the embodiments are all included in the scope of the present invention.
Also, it should be understood that, although the terms first, second, etc. may be used herein to describe various elements or structures, these described elements should not be limited by these terms. These terms are only used to distinguish these descriptive objects from one another. For example, the first NMOS transistor may be referred to as the second NMOS transistor, and similarly, the second NMOS transistor may also be referred to as the first NMOS transistor, without departing from the scope of the present invention.
Referring to fig. 1, the utility model discloses a high common mode dynamic range and invariable differential amplifier of PVT, this differential amplifier includes invariable transconductance biasing circuit, differential amplifier circuit and input common mode component tracking compensation circuit:
the function of the constant transconductance biasing circuit is to provide a bias voltage and current to the differential amplifier circuit that varies with process, voltage, and temperature (PVT) variations.
The effect of the bias voltage and the current on the gain of the whole amplifier also changes along with the change of the PVT, the trend of the change is opposite to the trend of the inherent gain of the differential amplifier circuit along with the change of the PVT, and the change and the trend can mutually cancel out, so that the constant characteristic of the PVT is achieved.
The input common mode component tracking compensation circuit can extract the common mode component of the input signal, and according to the influence exerted on the differential amplifier circuit by the extracted common mode component, for example, by adjusting the bias state and the like, the gain of the differential amplifier is kept not influenced by the common mode component of the input signal, and the common mode dynamic range of the amplifier is widened.
The present invention will be further described with reference to the following specific examples.
Referring to fig. 2, an embodiment of the present invention discloses a differential amplifier with a high common mode dynamic range and a constant PVT, which includes a constant transconductance biasing circuit, a differential amplifier circuit, and an input common mode component tracking compensation circuit, and the following detailed description is made for three circuit units.
Constant transconductance biasing circuit:
the constant transconductance biasing circuit comprises a cascode current mirror and a bias current amplifying circuit, wherein the cascode current mirror comprises a plurality of PMOS (P-channel metal oxide semiconductor) tubes, a plurality of NMOS (N-channel metal oxide semiconductor) tubes and a resistor RCThe bias current amplifying circuit comprises an operational amplifier, a resistor connected with two input ends of the operational amplifier and an NMOS tube connected with an output end of the operational amplifier.
In particular, the cascode current mirror in this embodiment is used to provide the bias current IbIt comprises a first PMOS tube (P)1) And a second PMOS transistor (P)2) And the third PMOS tube (P)3) And the fourth PMOS tube (P)4) And the fifth PMOS tube (P)5) And the sixth PMOS tube (P)6) A first NMOS transistor (N)1) And a second NMOS transistor (N)2) And the third NMOS transistor3) And the fourth NMOS transistor4) And a resistance RC；
The grid electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected, the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with a voltage VDD, the drain electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are respectively connected with the source electrodes of the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube, the grid electrodes of the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are connected, the drain electrodes of the fourth PMOS tube and the fifth PMOS tube are respectively connected with the drain electrodes of the first NMOS tube and the second NMOS tube, the drain electrode of the sixth PMOS tube is connected with a bias current amplifying circuit, the grid electrodes of the first NMOS tube and the second NMOS tube are connected, the source electrodes of the first NMOS tube and the second NMOS tube are respectively connected with the drain electrodes of the third NMOS tube and the fourth NMOS tube, the grid electrodes of the third NMOS tube and the fourth NMOS tube are connected, the source electrode of the third NMOS tube is connected with a voltage VSS, and the source electrode of the fourth NMOS tube is connected with a resistor RCAnd then the grid electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube, and the grid electrode of the third NMOS tube is connected with the drain electrode of the third NMOS tube.
The bias current amplifying circuit in the embodiment is used for amplifying the bias current provided by the cascode current mirror, and comprises an operational amplifier (A) and a first resistor (R) connected with two input ends of the operational amplifier (A)1) And a second resistance (R)2) And the ninth NMOS tube (N) connected with the output end of the operational amplifier (A)9)；
The first input end and the second input end of the operational amplifier are connected with the first resistor and the second resistor respectively and then connected with the voltage VSS, the first input end is further connected with the drain electrode of the sixth PMOS tube, the output end of the operational amplifier is connected with the grid electrode of the ninth NMOS tube, the source electrode of the ninth NMOS tube is connected with the second input end of the operational amplifier, and the drain electrode of the ninth NMOS tube is connected with the differential amplifier circuit.
A differential amplifier circuit:
the differential amplifier circuit comprises a plurality of PMOS tubes, a plurality of NMOS tubes and a plurality of resistors.
Specifically, the differential amplifier circuit in this embodiment includes a fifth NMOS transistor (N)5) And the sixth NMOS transistor6) And the seventh NMOS transistor (N)7) And the eighth NMOS transistor (N)8) And a third resistor (R)3) And a fourth resistor (R)4)；
The source electrodes of the fifth NMOS tube and the sixth NMOS tube are connected with the constant transconductance biasing circuit, and the grid electrodes of the fifth NMOS tube and the sixth NMOS tube are respectively connected with the first signal input end Vin，nAnd a second signal input terminal Vin，pThe drain electrodes of the fifth NMOS tube and the sixth NMOS tube are respectively connected with the source electrodes of the seventh NMOS tube and the eighth NMOS tube, the grid electrodes of the seventh NMOS tube and the eighth NMOS tube are connected, and the drain electrodes of the seventh NMOS tube and the eighth NMOS tube are respectively connected with the first signal output end Vout，pAnd a second signal output terminal Vout，nAnd the drain electrode of the seventh NMOS tube is connected with the third resistor and then connected with the voltage VDD, and the drain electrode of the eighth NMOS tube is connected with the fourth resistor and then connected with the voltage VDD.
Input common mode component tracking compensation circuit:
the input common-mode component tracking compensation circuit comprises a PMOS tube and a plurality of resistors.
Specifically, the input in the present embodimentThe common mode component tracking compensation circuit comprises a seventh PMOS tube (P)7) A fifth resistor (R)5) A sixth resistor (R)6) And a seventh resistor (R)7) Fifth resistance (R)5) A sixth resistor (R)6) For extracting a common mode component of the input signal;
the source electrode of the seventh PMOS tube is connected with the fifth resistor and then connected with the voltage VDD, the grid electrode of the seventh PMOS tube is connected with the sixth resistor and the seventh resistor respectively and then connected with the first signal input end and the second signal input end, the drain electrode of the seventh PMOS tube is connected with the voltage VSS, and the source electrode of the seventh PMOS tube is connected with the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube.
The cascode current mirror in the constant transconductance biasing circuit of the embodiment has the advantage of high output impedance, and provides the biasing current IbComprises the following steps:
wherein, βmAnd K is the size ratio of the fourth NMOS tube to the third NMOS tube.
The amplification factor of the bias current amplification circuit is a, a is the ratio of the first resistor to the second resistor, and the bias current amplification circuit can amplify the bias current I of the current mirrorbThe amplification is a times, and the tail current of the operational amplifier (A) is obtained.
The feedback circuit composed of the operational amplifier (A) can greatly increase the secondary resistance (R)2) Looking at the input impedance Z of the circuit, thereby reducing bias current variations to the differential amplifier circuit due to supply voltage variations.
From the fifth NMOS transistor (N)5) And the sixth NMOS transistor6) The transconductance of the differential input stage can be expressed as:
wherein, βdThe transconductance coefficients of the fifth NMOS transistor and the sixth NMOS transistor (the transconductance coefficients of the fifth NMOS transistor and the sixth NMOS transistor)Equal in number), a is the amplification factor of the bias current amplifier circuit, IbIs the bias current.
Combining formula (1), one can obtain:
thus, the voltage gain of the differential amplifier circuit may be represented as AV＝gmR3Namely:
from the equation (4), the voltage gain of the differential amplifier circuit is only related to parameters such as the ratio of the resistors and the size ratio of the MOS transistors, and is not related to the bias voltage, the process parameters, and the like, so that the voltage gain of the differential amplifier circuit can achieve the effect of PVT constancy.
Sixth resistor (R) in the present embodiment6) And a seventh resistor (R)7) The resistors are large resistors with equal resistance values and are used for extracting the common-mode component of the input signal. The extracted common mode component passes through a seventh PMOS tube (P7) and a fifth resistor (R)5) The voltage conversion circuit is used for the seventh NMOS transistor (N) in the differential amplifier circuit7) And an eighth NMOS transistor (N)8) When the common-mode component of the input signal generates large-range offset by applying a grid bias voltage, the offset is followed by the bias voltage converted by the common-mode component, so that the MOS tube in the differential amplifier circuit is ensured to work in a saturation region, and the common-mode dynamic range of the differential amplifier circuit is enlarged.
According to the technical scheme provided by the utility model, the utility model discloses following beneficial effect has:
the utility model discloses well invariable transconductance biasing circuit can offset the inherent gain of differential amplifier circuit along with PVT's change to reach the invariable characteristic of PVT, input common mode component tracking compensating circuit can draw input signal's common mode component, has enlarged differential amplifier circuit's common mode dynamic range.
It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A differential amplifier with high common-mode dynamic range and constant PVT (voltage-to-noise ratio), which is characterized in that the differential amplifier comprises a constant transconductance biasing circuit, a differential amplifier circuit and an input common-mode component tracking compensation circuit, wherein the input common-mode component tracking compensation circuit is used for extracting a common-mode component of an input signal, and the constant transconductance biasing circuit is used for providing a biasing voltage and a current according to the common-mode component fed back by the input common-mode component tracking compensation circuit so as to counteract the variation of the inherent gain of the differential amplifier circuit along with the PVT.
2. The high common-mode dynamic range and PVT constant differential amplifier of claim 1, wherein the constant transconductance biasing circuit comprises a cascode current mirror and a bias current amplification circuit, the cascode current mirror comprising PMOS transistors, NMOS transistors and a resistor RCThe bias current amplifying circuit comprises an operational amplifier, a resistor connected with two input ends of the operational amplifier and an NMOS tube connected with an output end of the operational amplifier.
3. The differential amplifier with high common-mode dynamic range and constant PVT as claimed in claim 2, wherein the cascode current mirror is used for providing the bias current and comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a resistor RC；
The grid electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected, the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with a voltage VDD, the drain electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are respectively connected with the source electrodes of the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube, the grid electrodes of the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are connected, the drain electrodes of the fourth PMOS tube and the fifth PMOS tube are respectively connected with the drain electrodes of the first NMOS tube and the second NMOS tube, the drain electrode of the sixth PMOS tube is connected with a bias current amplifying circuit, the grid electrodes of the first NMOS tube and the second NMOS tube are connected, the source electrodes of the first NMOS tube and the second NMOS tube are respectively connected with the drain electrodes of the third NMOS tube and the fourth NMOS tube, the grid electrodes of the third NMOS tube and the fourth NMOS tube are connected, the source electrode of the third NMOS tube is connected with a voltage VSS, and the source electrode of the fourth NMOS tube is connected with a resistor RCAnd then the grid electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube, and the grid electrode of the third NMOS tube is connected with the drain electrode of the third NMOS tube.
4. The differential amplifier with high common-mode dynamic range and constant PVT as claimed in claim 3, wherein the bias current amplifying circuit is used for amplifying the bias current provided by the cascode current mirror, and comprises an operational amplifier, a first resistor and a second resistor connected with two input ends of the operational amplifier, and a ninth NMOS transistor connected with an output end of the operational amplifier;
the first input end and the second input end of the operational amplifier are connected with the first resistor and the second resistor respectively and then connected with the voltage VSS, the first input end is further connected with the drain electrode of the sixth PMOS tube, the output end of the operational amplifier is connected with the grid electrode of the ninth NMOS tube, the source electrode of the ninth NMOS tube is connected with the second input end of the operational amplifier, and the drain electrode of the ninth NMOS tube is connected with the differential amplifier circuit.
5. The high common-mode dynamic range and PVT constant differential amplifier of claim 4, wherein the differential amplifier circuit comprises PMOS transistors, NMOS transistors, and resistors.
6. The high common-mode dynamic range and PVT constant differential amplifier of claim 5, wherein the differential amplifier circuit comprises a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and third and fourth resistors;
the source electrodes of the fifth NMOS tube and the sixth NMOS tube are connected with the constant transconductance biasing circuit, the grid electrodes of the fifth NMOS tube and the sixth NMOS tube are respectively connected with the first signal input end and the second signal input end, the drain electrodes of the fifth NMOS tube and the sixth NMOS tube are respectively connected with the source electrodes of the seventh NMOS tube and the eighth NMOS tube, the grid electrodes of the seventh NMOS tube and the eighth NMOS tube are connected, the drain electrodes of the seventh NMOS tube and the eighth NMOS tube are respectively connected with the first signal output end and the second signal output end, the drain electrode of the seventh NMOS tube is connected with the third resistor and then connected with the voltage VDD, and the drain electrode of the eighth NMOS tube is connected with the fourth resistor and then connected with the voltage VDD.
7. The high common-mode dynamic range and PVT constant differential amplifier of claim 6, wherein the input common-mode component tracking compensation circuit comprises a PMOS tube and resistors.
8. The high-common-mode dynamic range and PVT-constant differential amplifier according to claim 7, wherein the input common-mode component tracking compensation circuit comprises a seventh PMOS transistor, a fifth resistor, a sixth resistor and a seventh resistor, wherein the fifth resistor and the sixth resistor are used for extracting the common-mode component of the input signal;
the source electrode of the seventh PMOS tube is connected with the fifth resistor and then connected with a voltage VDD, the grid electrode of the seventh PMOS tube is connected with the sixth resistor and the seventh resistor respectively and then connected with the first signal input end and the second signal input end, the drain electrode of the seventh PMOS tube is connected with a voltage VSS, and the source electrode of the seventh PMOS tube is connected with the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube.
9. The high common-mode dynamic range and PVT constant differential amplifier of claim 4, wherein the cascode current mirror provides a bias current IbComprises the following steps:
wherein, βmThe transconductance coefficient of the third NMOS tube is shown, and K is the size ratio of the fourth NMOS tube to the third NMOS tube;
the amplification factor of the bias current amplification circuit is a, and a is the ratio of the first resistor to the second resistor.
10. The high common-mode dynamic range and PVT constant differential amplifier of claim 6, wherein the voltage gain of the differential amplifier circuit is AVComprises the following steps:
wherein, βmIs the transconductance coefficient of the third NMOS transistor, K is the size ratio of the fourth NMOS transistor to the third NMOS transistor, βdTransconductance coefficients of a fifth NMOS transistor and a sixth NMOS transistor, a is an amplification coefficient of the bias current amplification circuit, and R is3Is the resistance of the third resistor.
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