CN114362688A

CN114362688A - Rail-to-rail amplifier with common-mode feedback of dynamic bias current

Info

Publication number: CN114362688A
Application number: CN202210053686.5A
Authority: CN
Inventors: 周雄; 杨本能
Original assignee: Xinjuwei Technology Chengdu Co ltd
Current assignee: Xinjuwei Technology Chengdu Co ltd
Priority date: 2022-01-18
Filing date: 2022-01-18
Publication date: 2022-04-15

Abstract

The application discloses a rail-to-rail amplifier with dynamic bias current common-mode feedback, which comprises a bias circuit, a constant transconductance input circuit, a cascode load circuit, a floating bias circuit, a class-AB output circuit, a Miller compensation circuit and a complementary dynamic bias common-mode feedback circuit, wherein the complementary dynamic bias common-mode feedback circuit is used for compensating a current variation of a floating current source arranged in the cascode load circuit, which is caused by input common-mode variation in the constant transconductance input circuit, so that the current in the floating current source is kept constant; and the output ends Vop and Von of the class-AB output circuit are used as the input ends of the complementary dynamic bias common mode feedback circuit. The invention achieves the aim of keeping the current flowing through the floating current source stable by creatively adding the complementary common mode feedback n-type CMFB and p-type CMFB and dynamically adjusting the current, thereby stabilizing the open-loop gain and the output common mode of the amplifier when the input common mode Vicm is dynamically changed and ensuring the linearity of the amplifier.

Description

Rail-to-rail amplifier with common-mode feedback of dynamic bias current

Technical Field

The invention relates to the technical field of amplifiers, in particular to the technical field of high-linearity rail-to-rail amplifiers, and particularly relates to a rail-to-rail amplifier with dynamic bias current common-mode feedback.

Background

The signal link of the high-precision analog-to-digital converter needs modules such as a high-precision buffer, a filter, an adjustable gain amplifier and the like. In these modules, the amplifier is a core component. The situation where the input signal is accompanied by a large common-mode signal and at the same time requires a signal chain with a high dynamic range places more stringent requirements on several aspects of the amplifier. For example, an amplifier requires a rail-to-rail Input range, a high Common-mode rejection ratio (CMRR), low equivalent Input noise (IRN), and low harmonic distortion (THD). These criteria make the design of the amplifier difficult.

The differential amplifier circuit helps to suppress common mode interference signals. In general, a differential amplifier requires a common-mode feedback circuit to stabilize its output common-mode voltage. In this way, the latter circuit can be protected from common mode interference. The rail-to-rail input range is typically implemented by a constant-gm input pair. Fig. 7 shows a constant transconductance input circuit, which mainly uses two adaptive current mirrors to respectively perform fixed compensation on the currents of a PMOS transistor and an NMOS transistor, wherein the adaptive coefficients of the current mirrors are determined by the sizes of the PMOS transistor and the NMOS transistor, that is, the mobility of the PMOS transistor and the NMOS transistor is different, but based on the technology, no matter what difference exists, effective matching can be theoretically achieved, so as to achieve the effect of constant transconductance. However, although the constant transconductance is solved and the rail-to-rail input range is satisfied, the output current will change the equivalent resistance of the back-end cascode load due to the change of the input common mode, and finally the gain of the amplifier changes and decreases, the linearity is deteriorated, and the application requirement of the high-precision scene cannot be satisfied. Therefore, it is a difficult problem in amplifier design to ensure that linearity is not affected while satisfying the rail-to-rail input range and ensuring stable gain of the amplifier.

Disclosure of Invention

In order to solve the problem that the linearity is reduced after the amplifier meets the rail-to-rail input range through constant transconductance in the prior art, the invention provides the rail-to-rail amplifier with the dynamic bias current common-mode feedback, which is used for meeting the requirements of large-range rail-to-rail input and gain stability and ensuring the linearity of the amplifier.

In order to achieve the purpose, the technical scheme adopted by the application is as follows:

the rail-to-rail amplifier with the dynamic bias current common-mode feedback comprises a bias circuit, a constant transconductance input circuit, a cascode load circuit, a floating bias circuit, a class-AB output circuit, a Miller compensation circuit and a complementary dynamic bias common-mode feedback circuit, and is used for compensating a current variation of a floating current source arranged in the cascode load circuit, which is caused by input common-mode variation in the constant transconductance input circuit, so that the current in the floating current source is kept constant; and the output ends Vop and Von of the Miller compensation circuit are used as the input ends of the complementary dynamic bias common-mode feedback circuit.

As a preferred design scheme of the present invention, the cascode load circuit further includes a common-mode feedback pair NMOS transistor and a common-mode feedback pair PMOS transistor respectively connected to the floating current source; the complementary dynamic bias common-mode feedback circuit comprises an N-type CMFB used for compensating the current variation of the common-mode feedback pair NMOS tube and a P-type CMFB used for compensating the current variation of the common-mode feedback pair PMOS tube;

the common mode feedback pair NMOS tube comprises a cascode M39 and a cascode M40, wherein a source electrode is connected with VSS, a drain electrode is connected with the floating current source through a common gate NMOS pair tube, and a grid electrode is connected with an output end CMFBn of the first common mode feedback circuit; the common mode feedback pair PMOS tube comprises cascode M29 and M30, wherein a source electrode is connected with VDD, a drain electrode is connected with the floating current source through a common gate PMOS pair tube, and a grid electrode is connected with an output end CMFBp of the second common mode feedback circuit. By adopting the structure, the targeted compensation can be realized, and no matter how the input voltage Vip and Vin fluctuate between the rail and the rail range, the NMOS tube and the PMOS tube can be dynamically compensated by the common-mode feedback, so that the current flowing through the floating current source is kept constant and is not changed by the fluctuation of the input voltage Vip and Vin.

Still further, the complementary dynamic bias common mode feedback circuit further comprises a common mode feedback input circuit connected to the N-type CMFB and the P-type CMFB, respectively, and providing an output common mode Vocm, wherein the output common mode Vocm = (Vop + Von)/2.

In order to ensure the matching of dynamic compensation, the invention is preferably realized by adopting the following specific scheme: the N-type CMFB is composed of 4 PMOS tubes M53, M54, M55 and M58, and 3 NMOS tubes M56, M57 and M59; the grid of M54 is connected with the output common mode Vocm, the source of M54 is respectively connected with the drains of M53, M58 and M59 and the source of M55, the sources of M53 and M58 are connected with VDD, the drains of M54 and M56 are connected with the grid of M56 and connected with the output end CMFBn of the first common mode feedback circuit, the sources of M56, M57 and M59 are connected with VSS, the drain of M57 is connected with the grid of M55, the grid of M55 is connected with the reference voltage Vref, the grid of M58 is connected with the first dynamic bias voltage Vpsw, and the grid of M59 is connected with the second dynamic bias voltage Vnsw;

the P-type CMFB is composed of 4 NMOS tubes M62, M63, M64 and M66, and 3 PMOS tubes M60, M61 and M65; the grid of M62 is connected with the output common mode Vocm, the source of M62 is respectively connected with the drains of M64, M65 and M66 and the source of M63, the sources of M64 and M66 are connected with VSS, the drains of M62 and M60 are connected with the grid of M60 and are connected with the grid of the output end CMFBp of the second common mode feedback circuit, the sources of M60, M61 and M65 are connected with VDD, the drain of M61 is connected with the grid of M63, the grid of M63 is connected with the reference voltage Vref, the grid of M65 is connected with the first dynamic bias voltage Vpsw, and the grid of M66 is connected with the second dynamic bias voltage Vnsw.

Advantageously, the common mode feedback input circuit is composed of a pair of symmetrically arranged resistors Rcm and a pair of symmetrically arranged capacitors Ccm; one end of each resistor Rcm is connected with an output common mode Vocm, and the other end of each resistor Rcm is connected with Vop and Von respectively; one end of any capacitor Ccm is connected with the output common mode Vocm, and the other end of the capacitor Ccm is connected with Vop and Von respectively.

Has the advantages that:

the invention achieves the purpose of keeping the current flowing through the floating current source stable by adding complementary common mode feedback n-type CMFB and p-type CMFB and creatively and dynamically adjusting the currents of M29/M30 and M39/M40, thereby keeping the gain of the amplifier unchanged and having higher linearity. The invention can stabilize the open-loop gain and the output common mode of the amplifier when the input common mode Vicm is dynamically changed, thereby ensuring the linearity of the amplifier.

The invention fundamentally overcomes the problems that the equivalent output impedance of the cascode load changes along with the change of the input common mode Vicm, finally the gain of the amplifier changes and the linearity is inevitably influenced by a larger degree, which are inevitably caused by the fact that one end of the traditional CMOS amplifier is used as a constant current source and the other end of the CMOS amplifier is used as the common mode feedback input.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a circuit diagram of the present invention (not including a complementary dynamic bias common mode feedback circuit).

Fig. 2 is a graph of transconductance gm of fig. 1 as a function of input common mode Vicm.

Fig. 3 is a diagram of a conventional constant bias common mode feedback circuit.

Fig. 4 is a complementary dynamic bias common mode feedback circuit.

Fig. 5 is a schematic diagram of the structure of the buffer of the present invention when the input is extended to 4.

Fig. 6 is Total Harmonic Distortion (THD) and Spurious Free Dynamic Range (SFDR) of the input buffer.

Fig. 7 is a schematic diagram of a prior art constant transconductance input circuit.

In the figure: 100-a bias circuit; 200-a constant transconductance input circuit; 201-PMOS switch; 202-NMOS switch; 300-cascode load circuit; 301-a floating current source; 302-common mode feedback to NMOS transistor; 303-common mode feedback to PMOS transistor; 400-a floating bias circuit; a 500-class-AB output circuit; 600-miller compensation circuit; 700-complementary dynamic bias common mode feedback circuit; 701-common mode feedback input circuit; 702-N-type CMFB; 703-P-type CMFB.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

Example 1:

in order to better explain the invention, the technical improvement principle and the content of the invention are contrasted and explained with pertinence and prominence; first, the present embodiment will be explained by using a circuit structure and an operation principle without adding the complementary dynamic bias common mode feedback circuit 700, so as to enable those skilled in the art to fully understand the technical scheme adopted by the complementary dynamic bias common mode feedback circuit 700 to solve the problem of amplifier linearity and the necessary beneficial technical effects, which are specifically as follows:

the rail-to-rail amplifier shown in fig. 1 in conjunction with the description herein includes a bias circuit 100, a constant transconductance input circuit 200, a cascode load circuit 300, a floating bias circuit 400, a class-AB output circuit 500, and a miller compensation circuit 600.

The bias circuit 100 generates constant bias voltages Vpt, Vpcas, Vncas, and Vntail through 4 PMOS transistors and 2 NMOS transistors, and respectively acts on the constant transconductance input circuit 200, the cascode load circuit 300, and the floating bias circuit 400 to implement the operations of the corresponding PMOS transistors and NMOS transistors, as shown in fig. 1.

The operating principle of the constant transconductance input circuit 200 is as follows:

the basic principle of realizing the constant input transconductance is realized by utilizing the inverse conduction characteristics of PMOS and NMOS, namely, the characteristics of PMOS on low level (Vgs < Vthp <0, Vthp is the threshold voltage of a PMOS tube) and NMOS on high level (Vgs > Vthn >0, Vthn is the threshold voltage of an NMOS tube) are utilized, so that when the input common mode is changed in a large range, the input tube is always conducted and the transconductance is constant. As shown in FIG. 1, M19-M22 are input PMOS tubes, M23-M26 are input NMOS tubes, and since the input tubes all work in the subthreshold region, the sizes of the tubes are M19: M20: M21: M22=1, and M23: M24: M25: M26= 1.

The first situation is as follows: when the input common mode [ Vicm = (Vip + Vin)/2 ] is at the middle level (near VDD/2), the PMOS input pair transistors M20 and M21 are turned on, and at this time, since the PMOS transistor M17 is in the off state, the PMOS transistors M19 and M22 are not turned on; similarly, the NMOS input pair transistors M24 and M25 are turned on simultaneously, and since the NMOS transistor M27 is in the off state, the NMOS transistors M23 and M26 are not turned on, and the input transconductance is at this time

gm-total=gmp+gmn=2gm

Here gmp and gmn are set to be approximately the same.

Case two: when the input common mode is reduced, the source terminal voltage Vsn is pushed low because the tail currents (Id 27, Id 28) are constant current sources. When Vicm is lower than around Vds27/28+ Vthn, the NMOS inputs of M24, M25 are gradually turned off with zero current flowing through the pair, while the current switch M14 is gradually turned on because Vsn is low. The current Id27 of M27 flows through M14 and M13 in turn, and M17 mirrors the current through the current mirrors of M13 and M17, so that the current flows into M19 and M22, and simultaneously, the gates of M13 and M17 generate the first dynamic bias voltage Vpsw, and the tubes in operation are 4 input PMOS tubes of M19 to M22. The total transconductance of the inputs is

gm-total=2*gmp=2gm；

Case three: when the input common mode rises, the source terminal voltage Vsp is also pushed high because the tail currents Id17 and Id18 are both constant current sources. When Vicm is higher than around Vds17/18+ Vthp, the pair of M20 and M21 PMOS inputs is gradually turned off, the current flowing is zero, and the other current switch M15 is gradually turned on because Vsp is high. The current Id17 of M17 in turn flows through M15 and M16, which is mirrored by M27 through the current mirrors of M16 and M27, so that current flows into M23 and M26, while the gates of M16 and M27 generate the second dynamic bias voltage Vnsw'; the working transistors are 4 input NMOS transistors from M23 to M26, and the total transconductance of the input is

gm-total=2*gmn=2gm；

It is worth mentioning that: in the upper and lower transition regions, it also happens that the transconductance gm-total of all the transistors (including the working PMOS transistors and NMOS transistors) is slightly larger or smaller than 2gm in sum, and generally, the gm-total varies in the range of 3-8%.

The fluctuation curve of the total transconductance gm-total of the input common mode (Vicm = (Vip + Vin)/2) in the VSS-VDD range is shown in FIG. 2.

The above description illustrates the operation of the input common mode Vicm with the full swing in the rail-to-rail (rail-to-rail) range, but this will cause the current flowing into V1, V2 and V3, V4 to change in the subsequent source-common gate load circuit 300, that is, the current flowing into/out of M39, M40, M29 and M30 to change; it can be seen that if a conventional CMOS amplifier is used, one terminal of the conventional CMOS amplifier is used as a constant current source (the bias voltage Vpt shown in fig. 3) and the other terminal is used as an input of the common mode feedback (the common mode feedback CMFB shown in fig. 3), as shown in detail in fig. 3, the currents flowing into the floating current sources M33/M35, M34/M36 will vary according to the magnitude of the input common mode. As a result, the equivalent output impedance of the source-common-gate load circuit 300 also changes, and the gain of the amplifier changes, so that the linearity is relatively greatly affected. And the output common mode has common mode fluctuation of more than 5mV even under the condition of common mode feedback. Finally, Vop and Von are output through the floating bias circuit 400, the class-AB output circuit 500 and the miller compensation circuit 600, resulting in the whole amplifier satisfying the rail-to-rail input range but not guaranteeing the linearity of the gain.

Example 2:

based on the above problem explained in embodiment 1, the solution adopted by this embodiment further includes a complementary dynamic bias common mode feedback circuit 700, and is used to compensate the amount of current variation of the floating current source 301 disposed in the cascode load circuit 300 due to the input common mode variation in the constant transconductance input circuit 200, so that the current in the floating current source 301 is kept constant; the output terminals Vop and Von of the miller compensation circuit 600 are used as the input terminals of the complementary dynamic bias common mode feedback circuit 700. The current is dynamically compensated by the complementary dynamic bias common mode feedback circuit 700, so that the current of the floating current source 301 in the whole constant-gm process is kept constant, and the problem that the gain of the amplifier is changed finally due to the change of the equivalent output impedance of the cascode load caused by the fluctuation of the input common mode Vicm in the rail-to-rail (rail-to-rail) range in embodiment 1 is solved, so that the linearity of the amplifier is not greatly influenced.

As guided by the inventive concept provided by the present invention, the present embodiment further provides a rail-to-rail amplifier with a common-mode feedback of a dynamic bias current, and the cascode load circuit 300 further includes a common-mode feedback pair NMOS transistor 302 and a common-mode feedback pair PMOS transistor 303 respectively connected to the floating current source 301; the complementary dynamic bias common mode feedback circuit 700 comprises an N-type CMFB702 for compensating the current variation of the common mode feedback pair NMOS tube 302 and a P-type CMFB703 for compensating the current variation of the common mode feedback pair PMOS tube 303;

the common mode feedback pair NMOS transistor 302 includes cascode M39 and M40, in which the source is connected to VSS, the drain is connected to the floating current source 301 through a common gate NMOS pair transistor, the gate is connected to the first common mode feedback circuit output terminal CMFBn, the gate of the common gate NMOS pair transistor is connected to the bias voltage Vpcas, the source is connected to the common mode feedback pair NMOS transistor 302, and the drain is connected to the floating current source 301; the common mode feedback pair PMOS tube 303 comprises a common source and a common drain M29 and M30, wherein a source electrode is connected with VDD, a drain electrode is connected with the floating current source 301 through a common gate PMOS pair tube, a grid electrode is connected with the output end CMFBp of the second common mode feedback circuit, the grid electrode of the common gate PMOS pair tube is connected with a bias voltage Vncas, the source electrode is connected with the common mode feedback pair PMOS tube, and the drain electrode is connected with the floating current source 301; the first common mode feedback circuit and the second common mode feedback circuit are implemented by the prior art and are not shown in the figure.

The complementary dynamic bias common mode feedback circuit 700 further comprises a common mode feedback input circuit 701 connected to the N-type CMFB702 and the P-type CMFB703, respectively, and providing an output common mode Vocm, wherein the output common mode Vocm = (Vop + Von)/2. As shown in fig. 4, the common mode feedback input circuit 701 is composed of a pair of symmetrically arranged resistors Rcm and a pair of symmetrically arranged capacitors Ccm; one end of each resistor Rcm is connected with an output common mode Vocm, and the other end of each resistor Rcm is connected with Vop and Von respectively; one end of any capacitor Ccm is connected with the output common mode Vocm, and the other end of the capacitor Ccm is connected with Vop and Von respectively. By adopting the structure, the output common mode Vocm is obtained by averaging two Rcm, Ccm compensates a parasitic zero point of Ccm, and then the output common mode Vocm is respectively input into the N-type CMFB702 and the P-type CMFB 703.

Specifically, the method comprises the following steps:

the N-type CMFB702 is composed of 4 PMOS tubes M53, M54, M55 and M58 and 3 NMOS tubes M56, M57 and M59 in total; the grid of M54 is connected with output common mode Vocm, the source of M54 is respectively connected with the drains of M53, M58 and M59 and the source of M55, the sources of M53 and M58 are connected with VDD, the drains of M54 and M56 are connected with the grid of M56 and connected with the output end CMFBn of the first common mode feedback circuit, the sources of M56, M57 and M59 are connected with VSS, the drain of M57 is connected with the grid of M55, the grid of M55 is connected with reference voltage Vref, the grid of M58 is connected with first dynamic bias voltage Vpsw, and the grid of M59 is connected with second dynamic bias voltage Vnsw.

The working principle of the N-type CMFB702 is as follows: the output common mode Vocm is firstly input to the PMOS tube M54, and a stable current source is provided under the control of the constant bias voltage Vpt of the current source tube M53. The first dynamic bias voltage Vpsw is the control voltage of the M13/M17 current mirror, and can control the current of M58 and dynamically inject I1 according to the state of the PMOS switch 201 (current switch) M14, and similarly, the second dynamic bias voltage Vnsw is the control voltage of the M16/M27 current mirror, and can control the current of M59 and dynamically inject I2 according to the state of the NMOS switch 202 (current switch) M15; so far, under the action of I1 and I2, the current flowing through M56 can be controlled through the compensation current I3, so that the increase or decrease of the current of M39/M40 caused by constant-gm can be compensated.

The P-type CMFB703 is composed of 4 NMOS tubes M62, M63, M64 and M66, and 3 PMOS tubes M60, M61 and M65; the grid of M62 is connected with the output common mode Vocm, the source of M62 is respectively connected with the drains of M64, M65 and M66 and the source of M63, the sources of M64 and M66 are connected with VSS, the drains of M62 and M60 are connected with the grid of M60 and are connected with the grid of the output end CMFBp of the second common mode feedback circuit, the sources of M60, M61 and M65 are connected with VDD, the drain of M61 is connected with the grid of M63, the grid of M63 is connected with the reference voltage Vref, the grid of M65 is connected with the first dynamic bias voltage Vpsw, and the grid of M66 is connected with the second dynamic bias voltage Vnsw.

The working principle of the P-type CMFB703 is as follows: the output common mode Vocm is firstly input into the NMOS tube M62, and the current source tube M64 provides a stable current source under the control of a constant bias voltage Vntail. The first dynamic bias voltage Vpsw is the control voltage of the M13/M17 current mirror, and can control the current of M65 and dynamically inject I4 according to the state of the PMOS switch 201 (current switch) M14, and similarly, the second dynamic bias voltage Vnsw is the control voltage of the M16/M27 current mirror, and can control the current of M66 and dynamically inject I5 according to the state of the NMOS switch 202 (current switch) M15; so far, under the action of I4 and I5, the current flowing through M60 can be controlled through the compensation current I6, so that the increase or decrease of the current of M29/M30 caused by constant-gm can be compensated.

The current of the M29/M30 and the M39/M40 can be dynamically adjusted through the structure, so that the requirement that the current in the floating current source 301 is kept constant can be met, namely the current flowing through the floating current sources M33+ M35 and M34+ M36 is stable, and the problem that the linearity of gain cannot be guaranteed when the conventional rail-to-rail amplifier inputs a common mode full swing is solved fundamentally.

To further illustrate the linearity of the structure shown in this embodiment, referring to fig. 5 and fig. 6 of the specification, the input buffer shown in fig. 5 is taken as an example, and the amplifier used in the illustration is a 4-input structure, that is, a pair of constant current input stages is added to the original structure, and a unity-gain input buffer is constructed in a closed-loop manner. At a voltage of 3V, when the input differential signal peak-peak voltage range is + -2.26V, the harmonic performance of the output signal is as shown in FIG. 6, the low-frequency harmonic distortion of the input buffer using the amplifier of the present embodiment is-118.4 dB, and the SFDR is as high as 120 dB. Compared with the conventional structure, the single-ended common-mode feedback rail-to-rail amplifier is difficult to achieve THD below-100 dB and SFDR above 100dB, so that the open-loop gain and the output common mode of the amplifier can be stabilized when the input common mode Vicm is dynamically changed by adopting the mode of the embodiment, and the linearity of the amplifier is ensured. Compared with the conventional rail-to-rail amplifier without dynamic bias compensation, the high-linearity rail-to-rail amplifier with the dynamic bias current provided by the implementation has outstanding substantive characteristics and remarkable progress.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. Rail to rail amplifier that takes attitude bias current common mode feedback, including biasing circuit (100), invariable transconductance input circuit (200), cascode load circuit (300), floating bias circuit (400), class-AB output circuit (500) and miller compensation circuit (600), its characterized in that:

the current compensation circuit further comprises a complementary dynamic bias common-mode feedback circuit (700) and is used for compensating the current change amount of a floating current source (301) arranged in the cascode load circuit (300) caused by the input common-mode change in the constant transconductance input circuit (200), so that the current in the floating current source (301) is kept constant; the output terminals Vop and Von of the class-AB output circuit (500) are used as the input terminals of the complementary dynamic bias common mode feedback circuit (700).

2. The rail-to-rail amplifier with common-mode feedback of dynamic bias currents according to claim 1, wherein: the cascode load circuit (300) further comprises a common-mode feedback pair NMOS tube (302) and a common-mode feedback pair PMOS tube (303) which are respectively connected with the floating current source (301); the complementary dynamic bias common-mode feedback circuit (700) comprises an N-type CMFB (702) for compensating the current variation of the common-mode feedback pair NMOS tube (302) and a P-type CMFB (703) for compensating the current variation of the common-mode feedback pair PMOS tube (303);

the common-mode feedback pair NMOS transistor (302) comprises a common-source-common-gate M39 and a common-source-common-gate M40, wherein a source electrode is connected with VSS, a drain electrode is connected with the floating current source (301) through a common-gate NMOS pair transistor, and a grid electrode is connected with an output end CMFBn of the first common-mode feedback circuit; the common mode feedback pair PMOS tube (303) comprises a common source and a common gate M29 and M30, wherein the source is connected with VDD, the drain is connected with the floating current source (301) through the common gate PMOS pair tube, and the gate is connected with the output end CMFBp of the second common mode feedback circuit.

3. A rail-to-rail amplifier with common-mode feedback of dynamic bias currents according to claim 2, characterized in that: the complementary dynamic bias common mode feedback circuit (700) further comprises a common mode feedback input circuit (701) connected to the N-type CMFB (702) and the P-type CMFB (703), respectively, and providing an output common mode Vocm, wherein the output common mode Vocm = (Vop + Von)/2.

4. A rail-to-rail amplifier with common-mode feedback of dynamic bias currents according to claim 3, characterized in that: the N-type CMFB (702) is composed of 4 PMOS tubes M53, M54, M55 and M58 and 3 NMOS tubes M56, M57 and M59 in total; the grid of M54 is connected with the output common mode Vocm, the source of M54 is respectively connected with the drains of M53, M58 and M59 and the source of M55, the sources of M53 and M58 are connected with VDD, the drains of M54 and M56 are connected with the grid of M56 and connected with the output end CMFBn of the first common mode feedback circuit, the sources of M56, M57 and M59 are connected with VSS, the drain of M57 is connected with the grid of M55, the grid of M55 is connected with the reference voltage Vref, the grid of M58 is connected with the first dynamic bias voltage Vpsw, and the grid of M59 is connected with the second dynamic bias voltage Vnsw;

the P-type CMFB (703) is composed of 4 NMOS tubes M62, M63, M64 and M66 and 3 PMOS tubes M60, M61 and M65 in total; the grid of M62 is connected with the output common mode Vocm, the source of M62 is respectively connected with the drains of M64, M65 and M66 and the source of M63, the sources of M64 and M66 are connected with VSS, the drains of M62 and M60 are connected with the grid of M60 and are connected with the grid of the output end CMFBp of the second common mode feedback circuit, the sources of M60, M61 and M65 are connected with VDD, the drain of M61 is connected with the grid of M63, the grid of M63 is connected with the reference voltage Vref, the grid of M65 is connected with the first dynamic bias voltage Vpsw, and the grid of M66 is connected with the second dynamic bias voltage Vnsw.

5. A rail-to-rail amplifier with common-mode feedback of dynamic bias currents according to claim 3, characterized in that: the common-mode feedback input circuit (701) is composed of a pair of symmetrically arranged resistors Rcm and a pair of symmetrically arranged capacitors Ccm; one end of each resistor Rcm is connected with an output common mode Vocm, and the other end of each resistor Rcm is connected with Vop and Von respectively; one end of any capacitor Ccm is connected with the output common mode Vocm, and the other end of the capacitor Ccm is connected with Vop and Von respectively.