CN216565084U - Operational amplifier circuit and UWB filter applying same - Google Patents
Operational amplifier circuit and UWB filter applying same Download PDFInfo
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- CN216565084U CN216565084U CN202123135671.3U CN202123135671U CN216565084U CN 216565084 U CN216565084 U CN 216565084U CN 202123135671 U CN202123135671 U CN 202123135671U CN 216565084 U CN216565084 U CN 216565084U
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Abstract
The application provides an operational amplifier circuit and applied this operational amplifier circuit's UWB filter, the operational amplifier circuit includes: the output end of the first-stage operational amplifier is connected with the input end of the second-stage operational amplifier, wherein the input end of the first-stage operational amplifier is connected with an input signal, and the output end of the second-stage operational amplifier is used for providing an output signal; and the feedforward module is connected between the input end of the first-stage operational amplifier and the output end of the second-stage operational amplifier and is used for compensating the output signal based on the input signal. According to the technical scheme, the gain bandwidth product of the circuit is increased, the power consumption of the circuit is reduced, and the performance of the circuit is improved.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to an operational amplifier circuit and a UWB filter using the same.
Background
With the progress of science and technology, more and more electronic devices are applied to the daily life and work of people, and great convenience is brought to the daily life and work of people. The ultra-wideband (UWB) technology is a wireless carrier communication technology, and has the advantages of insensitivity to channel fading, low transmitted signal power density, low interception rate, low system complexity, and capability of providing accurate positioning at the centimeter level. UWB filters play a critical role in UWB systems, and are responsible for filtering the downconverted signals. Because the UWB system is low power consumption and high bandwidth, the UWB filter is also required to be low power consumption and high bandwidth to meet the requirements of the UWB system. In addition, in the UWB system, the intermediate frequency is selected to be 250MHz, i.e., the bandwidth of the UWB filter is 250 MHz. In UWB systems, high bandwidth means a higher gain-bandwidth product.
In UWB filter circuits, performance is highly dependent on the op-amp circuit. In the prior art, the operational amplifier circuit with low power consumption has low performance and cannot meet the performance requirement of a UWB system, and the operational amplifier circuit which meets the performance requirement of the UWB system has high power consumption and cannot meet the requirement of the UWB system on low power consumption. Therefore, it is one of the problems to be solved by those skilled in the art to design an operational amplifier circuit with low power consumption and high gain-bandwidth product on the premise of meeting the requirement of gain.
Disclosure of Invention
In view of this, the present application provides an operational amplifier circuit and a UWB filter using the same, which increases a gain-bandwidth product of the circuit, reduces power consumption of the circuit, and improves performance of the circuit.
In order to achieve the purpose, the invention provides the following technical scheme:
the application provides an operational amplifier circuit, the operational amplifier circuit includes:
the output end of the first-stage operational amplifier is connected with the input end of the second-stage operational amplifier, wherein the input end of the first-stage operational amplifier is connected with an input signal, and the output end of the second-stage operational amplifier is used for providing an output signal;
and the feedforward module is connected between the input end of the first-stage operational amplifier and the output end of the second-stage operational amplifier and is used for compensating the output signal based on the input signal.
Optionally, the method further includes:
a first bias circuit for providing a first current to the first stage operational amplifier;
the second bias circuit is used for providing a second current for the second-stage operational amplifier;
and the third bias circuit is used for providing a third current for the feedforward module.
Optionally, the input signal comprises a first input signal and a second input signal;
the first stage operational amplifier includes: the MOS transistor comprises first to fourth MOS transistors, a first resistor and a second resistor;
the grid electrode of the first MOS tube is used for accessing the first input signal, the first pole of the first MOS tube is connected with the first node, and the second pole of the first MOS tube is connected with the second node; the second node is used for connecting the first bias circuit;
the grid electrode of the second MOS tube is used for accessing the second input signal, the first pole of the second MOS tube is connected with the third node, and the second pole of the second MOS tube is connected with the second node;
the grid electrodes of the third MOS tube and the fourth MOS tube are connected with a fourth node, and first poles of the third MOS tube and the fourth MOS tube are input with first power supply voltage; the second pole of the third MOS tube is connected with the first node and is connected with the fourth node through the first resistor; and the second pole of the fourth MOS tube is connected with the third node and is connected with the fourth node through the second resistor.
Optionally, the resistance of the first resistor is equal to the resistance of the second resistor.
Optionally, the first bias circuit includes a fifth MOS transistor, a gate of the fifth MOS transistor is used for receiving a first bias voltage, a first pole of the fifth MOS transistor is connected to the second node, and a second pole of the fifth MOS transistor is input with a second power supply voltage;
wherein the first bias voltage is used to control the first current.
Optionally, the output signal comprises a first output signal and a second output signal; the output end of the first-stage operational amplifier comprises a first output end and a second output end;
the second stage operational amplifier includes: the MOS transistor comprises sixth to ninth MOS transistors, a third resistor and a fourth resistor;
the grid electrode of the sixth MOS tube is used for being connected with the first output end, the first pole of the sixth MOS tube is connected with the fifth node, and the second pole of the sixth MOS tube is connected with the sixth node; the sixth node is used for connecting the second bias circuit;
the grid electrode of the seventh MOS tube is used for being connected with the second output end, the first pole of the seventh MOS tube is connected with the seventh node, and the second pole of the seventh MOS tube is connected with the sixth node;
the grid electrodes of the eighth MOS tube and the ninth MOS tube are both connected with an eighth node, and first poles of the eighth MOS tube and the ninth MOS tube are both input with a first power supply voltage; a second pole of the eighth MOS transistor is connected to the fifth node, and is connected to the eighth node through the third resistor, where the fifth node is configured to output the first output signal; and the second pole of the ninth MOS transistor is connected with the seventh node, is connected with the eighth node through the fourth resistor, and is used for outputting the second output signal.
Optionally, a resistance of the third resistor is equal to a resistance of the fourth resistor.
Optionally, the second bias circuit includes a tenth MOS transistor, a gate of the tenth MOS transistor is used for receiving a second bias voltage, a first pole of the tenth MOS transistor is connected to the sixth node, and a second pole of the tenth MOS transistor is input with a second power supply voltage;
wherein the second bias voltage is used to control the second current.
Optionally, the input signal comprises a first input signal and a second input signal; the output signals comprise a first output signal and a second output signal; the feed forward module includes: an eleventh MOS transistor and a twelfth MOS transistor;
the gate of the eleventh MOS transistor is used for receiving the first input signal, the first pole of the eleventh MOS transistor is connected to the first output signal, and the second pole of the eleventh MOS transistor is connected to the ninth node; the ninth node is used for connecting the third bias circuit;
the gate of the twelfth MOS transistor is used for receiving the second input signal, the first pole of the twelfth MOS transistor is connected to the second output signal, and the second pole of the twelfth MOS transistor is connected to the ninth node.
Optionally, the third bias circuit includes a thirteenth MOS transistor, a gate of the thirteenth MOS transistor is used for receiving a third bias voltage, a first pole of the thirteenth MOS transistor is connected to the ninth node, and a second pole of the thirteenth MOS transistor is input with a second power supply voltage;
wherein the third bias voltage is used to control the third current.
Optionally, the first MOS transistor and the second MOS transistor are both NMOS.
Optionally, the sixth MOS transistor and the seventh MOS transistor are both NMOS.
The present application also provides a UWB filter, comprising:
the operational amplifier circuit of any one of the above.
According to the operational amplifier circuit and the UWB filter using the operational amplifier circuit, the output signal is compensated through the feedforward module based on the input signal, the gain bandwidth product of the circuit is increased, the power consumption of the circuit is reduced, and the performance of the circuit is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
The structures, proportions, and dimensions shown in the drawings and described in the specification are for illustrative purposes only and are not intended to limit the scope of the present disclosure, which is defined by the claims, but rather by the claims, it is understood that these drawings and their equivalents are merely illustrative and not intended to limit the scope of the present disclosure.
Fig. 1 is a circuit schematic diagram of an operational amplifier circuit according to an embodiment of the present invention;
fig. 2 is a circuit schematic diagram of another operational amplifier circuit according to an embodiment of the present invention;
fig. 3 is a circuit schematic diagram of another operational amplifier circuit according to an embodiment of the present invention;
fig. 4 is a circuit schematic diagram of another operational amplifier circuit according to an embodiment of the present invention;
fig. 5 is a circuit schematic diagram of another operational amplifier circuit according to an embodiment of the present invention;
fig. 6 is a comparison diagram of the effect of an operational amplifier circuit according to an embodiment of the present invention.
Detailed Description
Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown, and in which it is to be understood that the embodiments described are merely illustrative of some, but not all, of the embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a circuit schematic diagram of an operational amplifier circuit according to an embodiment of the present invention. The operational amplifier circuit is a conventional filter circuit used in existing UWB systems. As shown in fig. 1, the filter circuit includes: an operational amplifier OP1, an operational amplifier OP2, an operational amplifier OP 3; a resistor R1, a resistor R2, a resistor R3 and a resistor R4; a capacitor C1, a capacitor C2, a capacitor C3, and an input signal Vin +, an input signal Vin-, which is input by an OP1, an output signal Vout +, an output signal Vout-, which is output by an OP 3. Wherein, OP1 and OP2 form the first stage operational amplifier, OP3 forms the second stage operational amplifier, wherein, the gain of the whole circuit is equal to the product of the gains of the two stages of operational amplifiers, namely
The bandwidth of the whole filter is
And
two broadband values affect each other. R3 ═ R4 ═ R6, C1 ═ C2 ═ C3, and the bandwidth of the filter is generally defined as
Wherein
However, the above situation requires the operational amplifier circuit to be an ideal operational amplifier, and therefore, the filter circuit shown in fig. 1 cannot meet the requirements of high bandwidth and low power consumption.
Referring to fig. 2, fig. 2 is a circuit schematic diagram of another operational amplifier circuit according to an embodiment of the present invention. This operational amplifier circuit is traditional bi-polar operational amplifier circuit, and this operational amplifier circuit includes: MOS transistor Q11, MOS transistor Q12, MOS transistor Q13, MOS transistor Q14 and MOS transistor Q15; a power supply voltage Vdd, a power supply voltage Vss; an input signal Vin1 inputted from Q11, an input signal Vin2 inputted from Q12; an output signal Vout1 and an output signal Vout2 output by the operational amplifier circuit; a bias voltage Vbias; wherein, Q11, Q12 and Q13 are NMOS, and Q14 and Q15 are PMOS. The gain of the operational amplifier circuit is gm RsWhere gm is transconductance, RsIs the sum of the equivalent resistances of the PMOS transistors in fig. 2, i.e. the sum of the equivalent resistances of Q14 and Q15 shown in fig. 2. The operational amplifier circuit has simple structure, the current of the whole circuit is provided by Q13, the power consumption is low, but because R is RsThe operation amplifier circuit has the advantages that the operation amplifier circuit is small in size, poor in performance, and incapable of meeting requirements of a UWB system due to the fact that the product of gain and gain bandwidth is not enough, and the operation amplifier circuit is not provided with a feedback circuit, unstable in work and incapable of being applied to a UWB filter.
It should be noted that the gain-bandwidth product has a crucial influence on the bandwidth of the filter, and a too small gain-bandwidth product will limit the maximum bandwidth of the filter, and thus affect the performance of the filter.
Referring to fig. 3, fig. 3 is a circuit schematic diagram of another operational amplifier circuit according to an embodiment of the present invention. The operational amplifier circuit is a traditional two-stage operational amplifier structure with common-mode feedback. The operational amplifier circuit includes: a power supply voltage Vdd, a power supply voltage Vss; MOS transistor Q21, MOS transistor Q22, MOS transistor Q23, MOS transistor Q24, MOS transistor Q25, MOS transistor Q26, MOS transistor Q27, MOS transistor Q28, MOS transistor Q29, MOS transistor Q210, MOS transistor Q211, MOS transistor Q212, MOS transistor Q213 and MOS transistor Q214; a resistor R1, a resistor R2, a resistor R3 and a resistor R4; an input signal Vin1, an input signal Vin2, an output signal Vout1, an output signal Vout 2; bias voltage Vbias, common mode voltage Vcm, reference voltage Vref, feedback voltage Vcmfb. The gain of the circuit is the gain of a primary operational amplifier composed of Q21, Q22, Q23, Q24 and Q25 and the gain of a secondary operational amplifier composed of Q26, Q27, Q28 and Q29. Compared with the operational amplifier circuit shown in fig. 2, the gain of the operational amplifier circuit shown in fig. 3 is greatly increased, and a common mode feedback circuit composed of Q210, Q211, Q212, Q213 and Q214 is introduced to increase the stability of the circuit, but the common mode feedback circuit affects the gain bandwidth product of the whole circuit to a certain extent, and the power consumption of the whole circuit is relatively increased.
In addition, a miller compensation capacitor (not shown in fig. 3) is generally added in the operational amplifier circuit shown in fig. 3, the dominant pole is moved to a low frequency, the non-dominant pole is moved to a high frequency, separation of the poles is achieved, and meanwhile, a zero is introduced, which has a certain influence on the stability of the circuit structure, so that a compensation resistor is further added, and the zero of the right half plane is moved to a high frequency, so as to reduce or even cancel the influence of the zero on the stability of the circuit structure. While introducing miller compensation can increase the gain-bandwidth product of the circuit, it can increase the power consumption of the overall circuit. Therefore, in summary, the operational amplifier circuit cannot meet the requirements of the UWB filter for high bandwidth and low power consumption.
In fig. 3, the partial circuits where R1 and R2 are located are correspondingly connected in the main circuit, Vcm in the partial circuit is correspondingly connected in the main circuit, Vout1 in the partial circuit is correspondingly connected in the main circuit at Vout1, and Vout2 in the partial circuit is correspondingly connected in Vout 2. Fig. 3 shows two parts, based on a circuit diagram, without connecting R1 and R2 to the main circuit.
Based on the above problem, the application provides an operational amplifier circuit and a UWB filter using the same, which have the characteristics of high bandwidth and low power consumption, and are suitable for being applied to UWB filter circuits in UWB systems.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.
Referring to fig. 4, fig. 4 is a circuit schematic diagram of another operational amplifier circuit according to an embodiment of the present invention. As shown in fig. 4, the present application provides an operational amplifier circuit, including:
the output end of the first-stage operational amplifier OP11 is connected with the input end of the second-stage operational amplifier OP12, wherein the input end of the first-stage operational amplifier OP11 is connected with an input signal, and the output end of the second-stage operational amplifier OP12 is used for providing an output signal;
and the feedforward module 1 is connected between the input end of the first-stage operational amplifier OP11 and the output end of the second-stage operational amplifier OP12, and the feedforward module 1 is used for compensating the output signal based on the input signal.
Compared with the operational amplifier circuit shown in fig. 3, the operational amplifier circuit shown in fig. 4 does not need a separate common-mode feedback, but adds a local common-mode feedback (local common-mode feedback) compensation mode, that is, the feed-forward module 1, which greatly reduces the power consumption of the circuit without affecting the performance of the whole circuit, and has a high gain, and is suitable for being applied to a UWB filter circuit in a UWB system.
Referring to fig. 5, fig. 5 is a circuit schematic diagram of another operational amplifier circuit according to an embodiment of the present invention. It should be noted that the operational amplifier circuit shown in fig. 5 is an embodiment of the operational amplifier circuit shown in fig. 4. Therefore, the operational amplifier circuit further comprises: a first bias circuit for providing a first current to the first stage operational amplifier OP 11; a second bias circuit for supplying a second current to the second stage operational amplifier OP 12; and a third bias circuit for providing a third current to the feed forward module 1.
The first current is a current for ensuring the first-stage operational amplifier OP11 to work, the second current is a current for ensuring the second-stage operational amplifier OP12 to work, and the third current is a current for ensuring the feedforward module to work.
In the embodiment of the present application, the input signals include a first input signal Vin1 and a second input signal Vin 2; the first-stage operational amplifier OP11 includes: the first MOS transistor Q31 to the fourth MOS transistor Q34, a first resistor R1 and a second resistor R2;
the gate of the first MOS transistor Q31 is used for receiving a first input signal Vin1, the first pole of which is connected to the first node N1, and the second pole of which is connected to the second node N2; the second node N2 is used for connecting the first bias circuit;
the gate of the second MOS transistor Q32 is used for receiving a second input signal Vin2, the first pole of the second MOS transistor Q32 is connected to the third node N3, and the second pole of the second MOS transistor Q32 is connected to the second node N2;
the gates of the third MOS transistor Q33 and the fourth MOS transistor Q34 are both connected to the fourth node N4, and the first poles of the third MOS transistor Q33 and the fourth MOS transistor Q34 are both input with the first power supply voltage Vdd; the second pole of the third MOS transistor Q33 is connected to the first node N1, and is connected to the fourth node N4 through the first resistor R1; the second pole of the fourth MOS transistor Q34 is connected to the third node N3, and is connected to the fourth node N4 through a second resistor R2. Optionally, the resistance of the first resistor R1 is equal to the resistance of the second resistor R2.
In addition, the first bias circuit includes a fifth MOS transistor Q35, a gate of the fifth MOS transistor Q35 is used for receiving the first bias voltage Vbias1, a first pole of the fifth MOS transistor Q35 is connected to the second node N2, and a second pole of the fifth MOS transistor Q35 is input with the second power supply voltage Vss; wherein the first bias voltage Vbias1 is used to control the first current.
As shown in fig. 5, the output signals include a first output signal Vout1 and a second output signal Vout 2; the output end of the first-stage operational amplifier OP11 comprises a first output end and a second output end; the second-stage operational amplifier OP12 includes: sixth to ninth MOS transistors Q36 to Q39, a third resistor R3, and a fourth resistor R4;
the gate of the Q36 of the sixth MOS transistor is used for connecting the first output terminal, the first pole thereof is connected to the fifth node N5, and the second pole thereof is connected to the sixth node N6; a sixth node N6 for connecting the second bias circuit;
the gate of the seventh MOS transistor Q37 is connected to the second output terminal, the first pole thereof is connected to the seventh node N7, and the second pole thereof is connected to the sixth node N6;
the gates of the eighth MOS transistor Q38 and the ninth MOS transistor Q39 are both connected to the eighth node N8, and the first poles of the eighth MOS transistor Q38 and the ninth MOS transistor Q39 are both input with the first power supply voltage Vdd; the second pole of the eighth MOS transistor Q38 is connected to a fifth node N5, which is connected to an eighth node N8 through the third resistor R3, and the fifth node N5 is configured to output a first output signal Vout 1; the second pole of the ninth MOS transistor Q39 is connected to the seventh node N7, the eighth node N8 through the fourth resistor R4, and is used for outputting the second output signal Vout 2. The resistance of the third resistor R3 is equal to the resistance of the fourth resistor R4.
Optionally, in the embodiment of the present application, the resistances of R1 ═ R2, R3 ═ R4, and R1 and R3 are equal or different.
It should be noted that the second pole of the third MOS transistor Q33 is used as the first output end of the first operational amplifier OP11, and is connected to the first pole of the sixth MOS transistor Q36; in addition, the second pole of the fourth MOS transistor Q34 is used as the second output terminal of the first operational amplifier OP11, and is connected to the first pole of the seventh MOS transistor Q37.
In addition, the second bias circuit includes a tenth MOS transistor Q310, a gate of the tenth MOS transistor Q310 is configured to be connected to the second bias voltage Vbias2, a first pole thereof is connected to the sixth node N6, and a second pole thereof is input with the second power voltage Vss; wherein the second bias voltage Vbias2 is used to control the second current.
In the embodiment of the present application, one of the first and second poles of all the MOS transistors is a source, and the other is a drain.
As shown in fig. 5, the input signals include a first input signal Vin1 and a second input signal Vin 2; output signals first output signal Vout1 and second output signal Vout 2. The feedforward module 1 includes: an eleventh MOS transistor Q311 and a twelfth MOS transistor Q312;
the gate of the eleventh MOS transistor Q311 is used for receiving the first input signal Vin1, the first pole thereof is connected to the first output signal Vout1, and the second pole thereof is connected to the ninth node N9; the ninth node N9 is used for connecting the third bias circuit;
the gate of the twelfth MOS transistor Q312 is used for receiving the second input signal Vin2, and the first pole thereof is connected to the second output signal Vout2, and the second pole thereof is connected to the ninth node N9.
In addition, the third bias circuit includes a thirteenth MOS transistor Q313, a gate of the thirteenth MOS transistor Q313 is configured to be connected to the third bias voltage Vbias3, a first pole of the thirteenth MOS transistor Q313 is connected to the ninth node N9, a second pole of the thirteenth MOS transistor Q313 is input with the second power voltage Vss, wherein the third bias voltage Vbias3 is configured to control the third current.
The first current, the second current, and the third current may be equal or different. For example, by controlling the magnitude of the first current, one can control the magnitude of the first current by controlling the variation of the first bias voltage Vbias 1; the other one can control the magnitude of the first current by controlling the width-to-length ratio of the fifth MOS transistor Q35. In practical applications, one of the two may be selected or both may be selected based on requirements, which is not described herein again.
Compared to the prior art operational amplifier circuit shown in fig. 3, the third current in the embodiment of the present application is equivalent to a current induced in the operational amplifier circuit. In the operational amplifier circuit, GBW is gm/c, where GBW is the gain bandwidth product, gm is the transconductance, and c is the output capacitance. At the same voltage and the same width-to-length ratio, gm is proportional to the current. Therefore, the third current is introduced to increase the current of the whole circuit, further increase gm and further improve the gain-bandwidth product of the whole circuit.
Optionally, the first MOS transistor Q31 and the second MOS transistor Q32 are both NMOS. The sixth MOS transistor Q36 and the seventh MOS transistor Q37 are both NMOS. Due to the fact that
Wherein gm is transconductance, mu is mobility of the MOS transistor, c is capacitance,
the width-length ratio of the MOS tube is shown, and I is current; and the mobility mu of the NMOS is larger and is generally twice of that of the PMOS under the same condition, so that the input tube in the operational amplifier circuit is set to be the NMOS to obtain larger gm, and further the gain bandwidth product of the operational amplifier circuit is improved.
It should be noted that, although the output tube is set as NMOS to further increase the gain-bandwidth product of the operational amplifier circuit, when the output tube is PMOS, the gain-bandwidth product of the operational amplifier circuit is also increased compared to the prior art. Therefore, the NMOS or PMOS can be set based on actual requirements, which is not limited by the invention.
In the embodiment of the present application, the first input signal Vin1 is input to the first operational amplifier OP11 through the first MOS transistor Q31, is output through the third MOS transistor Q33, i.e., is output through the first output terminal of the first operational amplifier OP11, and the output signal is input to the second operational amplifier OP12 through the sixth MOS transistor Q36 and is output through the eighth MOS transistor Q38, so as to form the first output signal Vout 1. Correspondingly, the second input signal Vin2 is input to the first operational amplifier OP11 through the second MOS transistor Q32, is output through the fourth MOS transistor Q34, i.e., is output through the second output terminal of the first operational amplifier OP11, and the output signal is input to the second operational amplifier OP12 through the seventh MOS transistor Q37 and is output through the ninth MOS transistor Q39 to form the second output signal Vout 2.
Meanwhile, the first output signal Vout1 and the second output signal Vout2 are compensated by the feedforward module 1 based on the first input signal Vin1 and the second input signal Vin2, respectively. The compensation mode of the embodiment of the application introduces a left half-plane zero point, and the pole separation does not exist, so that the gain-bandwidth product of the circuit can be greatly increased. Compared with the gain bandwidth product of the miller compensation increasing circuit introduced in the prior art, the compensation mode of the embodiment of the application has better effect on increasing the gain bandwidth product and has lower power consumption compared with the prior art. In addition, the third current is introduced, so that the current of the operational amplifier circuit is increased, gm is improved, and the gain bandwidth product of the operational amplifier circuit is further increased.
In addition, the operational amplifier circuit in the embodiment of the present application does not need the operational amplifier circuit shown in fig. 3 to use a single operational amplifier as common mode feedback, but uses R1, R2, R3, and R4 as feedback, so that the power consumption of the entire operational amplifier circuit is reduced.
It should be noted that when a current passes through the resistors R1, R2, R3, and R4, a voltage of the third MOS transistor Q33, the fourth MOS transistor Q34, the eighth MOS transistor Q38, and the ninth MOS transistor is raised, so that the influence of the MOS transistors on the operational amplifier circuit due to manufacturing process errors is eliminated.
Referring to fig. 6, fig. 6 is a comparison diagram illustrating the effect of an operational amplifier circuit according to an embodiment of the present invention, where as shown in fig. 6, a curve a is the gain of the operational amplifier circuit in the prior art, and a curve B is the gain of the operational amplifier circuit according to the present invention. In most frequencies, the gain of the operational amplifier circuit corresponding to the invention is larger than that of the operational amplifier circuit in the prior art, especially under the common intermediate frequency of a 250MHz UWB system, the gain of the operational amplifier circuit of the invention is far larger than that of the operational amplifier circuit in the prior art, and generally under the frequency of 250MHz, the operational amplifier circuit of the invention can have the gain of 20+ dB.
In addition, the operational amplifier circuit provided by the invention greatly reduces the power consumption of the system and has a very high gain-bandwidth product. For example, when the operational amplifier circuit in the prior art needs a current in a milliamp level to achieve a certain performance, the operational amplifier circuit provided by the invention can achieve the same performance only by needing a current in a microamp level, and a lower current represents that the power consumption of the operational amplifier circuit is lower.
The present application also provides a UWB filter, the UWB filter including: any of the operational amplifier circuits described above.
According to the operational amplifier circuit and the UWB filter using the same, the feed-forward module is used for replacing a common-mode feedback module formed by the whole operational amplifier in the prior art, and the power consumption of the operational amplifier circuit is reduced. In addition, compensation is carried out by arranging the feedforward module, and compared with Miller compensation in the prior art, the gain-bandwidth product of the operational amplifier circuit is increased. Meanwhile, a third current is introduced into the operational amplifier circuit, so that the gain-bandwidth product of the operational amplifier circuit is further increased. And the gain bandwidth product of the operational amplifier circuit is further increased by setting the input tube in the operational amplifier circuit as NMOS. In summary, the operational amplifier circuit and the UWB filter using the same provided by the invention increase the gain-bandwidth product of the circuit, reduce the power consumption of the circuit, and improve the performance of the circuit.
The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It should be noted that in the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only used for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be configured and operated in a specific orientation, and thus, should not be construed as limiting the present application. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. The term "comprising" is used to specify the presence of stated elements, but not to preclude the presence or addition of one or more other like elements in a claim or a device.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (13)
1. An operational amplifier circuit, comprising:
the output end of the first-stage operational amplifier is connected with the input end of the second-stage operational amplifier, wherein the input end of the first-stage operational amplifier is connected with an input signal, and the output end of the second-stage operational amplifier is used for providing an output signal;
and the feedforward module is connected between the input end of the first-stage operational amplifier and the output end of the second-stage operational amplifier and is used for compensating the output signal based on the input signal.
2. The operational amplifier circuit of claim 1, further comprising:
a first bias circuit for providing a first current to the first stage operational amplifier;
the second bias circuit is used for providing a second current for the second-stage operational amplifier;
a third bias circuit for providing a third current to the feed forward module.
3. The operational amplifier circuit of claim 2, wherein the input signal comprises a first input signal and a second input signal;
the first stage operational amplifier includes: the MOS transistor comprises first to fourth MOS transistors, a first resistor and a second resistor;
the grid electrode of the first MOS tube is used for accessing the first input signal, the first pole of the first MOS tube is connected with the first node, and the second pole of the first MOS tube is connected with the second node; the second node is used for connecting the first bias circuit;
the grid electrode of the second MOS tube is used for accessing the second input signal, the first pole of the second MOS tube is connected with the third node, and the second pole of the second MOS tube is connected with the second node;
the grid electrodes of the third MOS tube and the fourth MOS tube are connected with a fourth node, and first poles of the third MOS tube and the fourth MOS tube are input with first power supply voltage; the second pole of the third MOS tube is connected with the first node and is connected with the fourth node through the first resistor; and the second pole of the fourth MOS tube is connected with the third node and is connected with the fourth node through the second resistor.
4. The operational amplifier circuit as claimed in claim 3, wherein the first resistor has a resistance equal to that of the second resistor.
5. The operational amplifier circuit according to claim 3, wherein the first bias circuit comprises a fifth MOS transistor, a gate of the fifth MOS transistor is used for receiving a first bias voltage, a first pole of the fifth MOS transistor is connected to the second node, and a second pole of the fifth MOS transistor is input with a second supply voltage;
wherein the first bias voltage is used to control the first current.
6. The operational amplifier circuit of claim 2, wherein the output signal comprises a first output signal and a second output signal; the output end of the first-stage operational amplifier comprises a first output end and a second output end;
the second stage operational amplifier includes: the MOS transistor comprises sixth to ninth MOS transistors, a third resistor and a fourth resistor;
the grid electrode of the sixth MOS tube is used for being connected with the first output end, the first pole of the sixth MOS tube is connected with the fifth node, and the second pole of the sixth MOS tube is connected with the sixth node; the sixth node is used for connecting the second bias circuit;
the grid electrode of the seventh MOS tube is used for being connected with the second output end, the first pole of the seventh MOS tube is connected with the seventh node, and the second pole of the seventh MOS tube is connected with the sixth node;
the grid electrodes of the eighth MOS tube and the ninth MOS tube are both connected with an eighth node, and first poles of the eighth MOS tube and the ninth MOS tube are both input with a first power supply voltage; a second pole of the eighth MOS transistor is connected to the fifth node, and is connected to the eighth node through the third resistor, where the fifth node is configured to output the first output signal; and the second pole of the ninth MOS transistor is connected with the seventh node, is connected with the eighth node through the fourth resistor, and is used for outputting the second output signal.
7. The operational amplifier circuit as claimed in claim 6, wherein the third resistor has a resistance equal to that of the fourth resistor.
8. The operational amplifier circuit according to claim 6, wherein the second bias circuit comprises a tenth MOS transistor, a gate of the tenth MOS transistor is used for receiving a second bias voltage, a first pole of the tenth MOS transistor is connected to the sixth node, and a second pole of the tenth MOS transistor is inputted with a second power supply voltage;
wherein the second bias voltage is used to control the second current.
9. The operational amplifier circuit of claim 2, wherein the input signal comprises a first input signal and a second input signal; the output signals comprise a first output signal and a second output signal; the feed forward module includes: an eleventh MOS transistor and a twelfth MOS transistor;
the gate of the eleventh MOS transistor is used for receiving the first input signal, the first pole of the eleventh MOS transistor is connected to the first output signal, and the second pole of the eleventh MOS transistor is connected to the ninth node; the ninth node is used for connecting the third bias circuit;
the gate of the twelfth MOS transistor is used for receiving the second input signal, the first pole of the twelfth MOS transistor is connected to the second output signal, and the second pole of the twelfth MOS transistor is connected to the ninth node.
10. The operational amplifier circuit according to claim 9, wherein the third bias circuit comprises a thirteenth MOS transistor, a gate of the thirteenth MOS transistor is used for receiving a third bias voltage, a first pole of the thirteenth MOS transistor is connected to the ninth node, and a second pole of the thirteenth MOS transistor is inputted with a second power voltage;
wherein the third bias voltage is used to control the third current.
11. The operational amplifier circuit as claimed in claim 3, wherein the first MOS transistor and the second MOS transistor are both NMOS transistors.
12. The operational amplifier circuit as claimed in claim 6, wherein the sixth MOS transistor and the seventh MOS transistor are both NMOS.
13. An UWB filter, comprising:
the operational amplifier circuit as set forth in any of the preceding claims 1-12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202123135671.3U CN216565084U (en) | 2021-12-10 | 2021-12-10 | Operational amplifier circuit and UWB filter applying same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123135671.3U CN216565084U (en) | 2021-12-10 | 2021-12-10 | Operational amplifier circuit and UWB filter applying same |
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| CN216565084U true CN216565084U (en) | 2022-05-17 |
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