CN111522389B - Wide-input low-dropout linear voltage stabilizing circuit - Google Patents
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Abstract
The invention discloses a wide-input low-dropout linear voltage stabilizing circuit which comprises a comparison circuit, a dynamic bias circuit, a wide-input buffer stage circuit, a power tube, a detection feedback circuit, a frequency compensation circuit and an off-chip capacitor, wherein the comparison circuit is connected with the dynamic bias circuit; the comparison circuit compares the feedback voltage with the reference voltage, adjusts the power tube according to the comparison result, and ensures stable output voltage; the dynamic bias circuit dynamically adjusts the current of the wide input buffer stage circuit according to the magnitude of the load current, so that the LDO circuit drives a large load with a small quiescent current; the wide input buffer stage circuit drives a grid capacitor of the power tube to play a role of isolation; the detection feedback circuit is used for sampling the output voltage and feeding back the sampling result to the input end of the comparison circuit; the frequency compensation circuit is used for compensating the frequency of the LDO circuit and ensuring the stability of the LDO circuit in the whole load range. The LDO circuit provided by the invention can drive the large off-chip capacitor and realize the low-voltage design of the LDO circuit.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, relates to a voltage stabilizer, and particularly relates to a wide-input low-dropout linear voltage stabilizing circuit.
Background
Low-Dropout (LDO) linear voltage regulator is called LDO for short and is widely applied to electronic systems. LDO belongs to linear voltage stabilizer, and its characteristics are that the noise of circuit itself is low and output voltage ripple is little. The disadvantages of LDOs are also apparent, as the power supply is not energy efficient, and efficiency is related to the input-output voltage difference. Switching power converters are another type of power management that has the greatest advantage of being energy efficient, but with large output voltage ripple. The common application is to place the LDO after the switching power supply, and isolate the analog and radio frequency circuits sensitive to noise by suppressing the power supply ripple through the LDO while considering the energy efficiency of the power supply.
With the rapid development of mobile intelligent devices, internet of things and intelligent home, the market demand for wireless communication chips is also increasing. And the power management module is an essential part of the wireless communication system. In order to expand the application range of the chip, the chip is required to be capable of operating under a wider power supply voltage range. Especially in low voltage operating environments, the selection of LDO circuit structures faces greater challenges.
The main modules of the LDO comprise: the circuit comprises a biasing circuit, an error amplifier, a voltage buffer stage, a power tube, a resistor divider circuit, a frequency compensation circuit and other modules. The bias circuit is used for generating a reference voltage and a bias current. The error amplifier compares the difference between the feedback voltage and the reference voltage and adjusts the gate voltage of the power tube. The voltage buffer stage is arranged between the error amplifier and the power tube and is used for driving the grid capacitance of the power tube, and the voltage buffer stage and the frequency compensation circuit together ensure the stability of a system loop. The resistor divider circuit detects the output voltage and feeds the output voltage back to the input end of the error amplifier. The lowest operating voltage of the LDO is greatly affected by the voltage buffer stage. For example, jssc.2007 (Mohammad Al-Shyoukh) proposes a transient enhanced LDO structure with buffer stages, see in detail fig. 1. The voltage buffer stage of the structure is a Super source follower (Super Source Follower, super-SF) with dynamic bias, which can reduce the equivalent impedance of the grid node of the power tube and push the pole of the power tube far outside the loop bandwidth. The circuit structure can provide good system stability in the whole load range, reduces the requirement on the series equivalent resistance of the off-chip capacitor, and is a very excellent LDO circuit scheme. But the Super-SF itself is a feedback loop and stability issues need to be considered, adding to the complexity of the circuit. Moreover, the attenuation of the output impedance by the Super-SF only acts within the own loop bandwidth (GBW_SSF), and when the frequency exceeds GBW_SSF, the equivalent output impedance is approximately equal to that of a simple SF. In addition, the introduction of SF limits the minimum operating voltage (Vdd_min) of the LDO, making the structure unsuitable for low voltage applications.
U.S. Pat. No. 6518737b1 proposes an LDO architecture that does not include Miller (Miller) frequency compensation, see in detail fig. 2, to achieve greater loop bandwidth and better power supply ripple rejection characteristics. The circuit adds a capacitor in the resistor feedback network to be connected with the resistor above in parallel to generate a zero point and a pole so as to improve the stability of the loop. Since the ratio of the zero to the pole is related to the ratio of the upper and lower resistors, this frequency compensation scheme limits the selectable range of reference and output voltages. In addition, the LDO uses an OTA connected with unit gain feedback as a voltage buffer stage to drive the power tube. Since the minimum input voltage of the voltage buffer stage is limited, although the buffer stage has a lower requirement for vdd_min than the source follower, it is still difficult to operate in a scenario where the power supply voltage is lower than 1.5V.
In view of this, there is an urgent need to design a new LDO circuit to overcome at least some of the above-mentioned drawbacks of the existing LDO circuits.
Disclosure of Invention
The invention provides a wide-input low-dropout linear voltage stabilizing circuit, which can drive a large capacitor outside a chip to realize the low-voltage design of the low-dropout linear voltage stabilizing circuit.
In order to solve the technical problems, according to one aspect of the present invention, the following technical scheme is adopted:
a wide input low dropout linear voltage regulator circuit, the low dropout linear voltage regulator circuit comprising: the device comprises a comparison circuit, a dynamic bias circuit, a wide input buffer stage circuit, a power tube, a detection feedback circuit, a frequency compensation circuit and an off-chip capacitor;
The input voltage is respectively connected with the comparison circuit, the dynamic bias circuit and the power tube; the input end of the comparison circuit is respectively connected with the reference voltage and the detection feedback circuit, and the output end of the comparison circuit is connected with the input end of the wide input buffer stage circuit;
the comparison circuit compares the feedback voltage with the reference voltage, adjusts the power tube according to the comparison result, and ensures stable output voltage;
the output end of the dynamic bias circuit is connected with the input end of the wide input buffer stage circuit, and the output end of the wide input buffer stage circuit is connected with the power tube;
The dynamic bias circuit dynamically adjusts the current of the wide input buffer stage circuit according to the magnitude of the load current, so that the LDO circuit drives a large load with a small static current;
The wide input buffer stage circuit is arranged between the comparison circuit and the power tube, drives a capacitor connected with the grid electrode of the power tube, and plays an isolating role;
the output end of the frequency compensation circuit is respectively connected with the power tube and the detection feedback circuit; the output voltage is respectively connected with the power tube, the off-chip capacitor and the detection feedback circuit;
The detection feedback circuit is used for sampling the output voltage and feeding back the sampling result to the input end of the comparison circuit;
the frequency compensation circuit is used for compensating the frequency of the LDO circuit and ensuring the stability of the LDO circuit in the whole load range.
When the load is switched from large to small, the swing rate of the output end of the wide input buffer stage circuit is large due to the existence of the dynamic bias circuit, so that the charging of the grid capacitor of the power tube is accelerated, the output voltage reaches a stable value more quickly, and the transient characteristic is enhanced.
As an embodiment of the present invention, the off-chip capacitor is used to improve transient characteristics of the output voltage of the LDO circuit, and plays a role in loop stability.
As an embodiment of the present invention, the comparison circuit includes an error amplifier.
As an embodiment of the present invention, the comparison circuit includes a folded cascode operational amplifier.
As one embodiment of the present invention, the error amplifier includes a P-type tail current source, a first P-type input amplifying tube, a second P-type input amplifying tube, a first N-type current source, a second N-type current source, a first common-gate transistor, a second common-gate transistor, a first P-type current mirror load, and a second P-type current mirror load;
The input voltage is respectively connected with the source electrode of the P-type tail current source, the source electrode of the first P-type current mirror load and the source electrode of the second P-type current mirror load;
the drain electrode of the P-type tail current source is respectively connected with the source electrodes of the first P-type input amplifying tube and the second P-type input amplifying tube;
the drain electrode of the first P-type input amplifying tube is respectively connected with the source electrode of the first common gate transistor and the drain electrode of the first N-type current source; the drain electrode of the second P-type input amplifying tube is respectively connected with the source electrode of the second common-gate transistor and the drain electrode of the second N-type current source;
the grid electrode of the first P-type current mirror load is respectively connected with the grid electrode of the second P-type current mirror load, the drain electrode of the first P-type current mirror load and the drain electrode of the first common-gate transistor; and the drain electrode of the second P-type current mirror load is connected with the drain electrode of the second common-gate transistor.
As one embodiment of the present invention, the detection feedback circuit includes a first polysilicon resistor and a second polysilicon resistor; the drain electrode of the power tube is connected with the first end of the first polysilicon resistor, and the grid electrode of the first P-type input amplifying tube is respectively connected with the second end of the first polysilicon resistor and the first end of the second polysilicon resistor;
The change of the output voltage is detected by means of the resistive voltage division and the detected voltage value is returned to the input of the error amplifier.
As one embodiment of the present invention, the compensation circuit includes a compensation capacitor and a cascode circuit; the cascode circuit comprises a first N-type current source, a second N-type current source, a first common-gate transistor and a second common-gate transistor; the cascode circuit is shared by the error amplifier;
One end of the compensation capacitor is connected with the output end Vout of the LDO circuit, and the other end of the compensation capacitor is connected with the source electrode of the second common-gate transistor to form a compensation mode based on the Current Buffer.
As an embodiment of the present invention, the dynamic bias circuit includes a first resistor, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a second resistor, a fifth MOS transistor, a sixth MOS transistor, a current limiting resistor, and a seventh MOS transistor;
The first end of the first resistor is connected with the grid electrode of the first MOS tube and the grid electrode of the fourth MOS tube; the second end of the first resistor is respectively connected with the drain electrode of the first MOS tube, the grid electrode of the second MOS tube and the grid electrode of the third MOS tube;
the input voltage is connected with the source electrode of the sixth MOS tube, and the grid electrode of the sixth MOS tube is respectively connected with the drain electrode of the fifth MOS tube and the first end of the second resistor; the drain electrode of the sixth MOS tube is connected with the source electrode of the fifth MOS tube;
the grid electrode of the fifth MOS tube is respectively connected with the second end of the second resistor and the drain electrode of the fourth MOS tube; the source electrode of the fourth MOS tube is connected with the drain electrode of the third MOS tube, and the source electrode of the third MOS tube is connected with the source electrode of the second MOS tube.
As one embodiment of the present invention, the wide input buffer stage circuit includes a rail-to-rail input stage and a cascode output stage;
the rail-to-rail input stage comprises a P-type tail current source, an N-type input pair transistor and a P-type input pair transistor; the N-type input pair transistors comprise a first N-type transistor and a second N-type transistor, and the P-type input pair transistors comprise a first P-type transistor and a second P-type transistor;
The source electrode of the P-type tail current source is connected with the input voltage, the grid electrode of the P-type tail current source is connected with the grid electrode of the sixth MOS tube, and the drain electrodes of the P-type tail current source are respectively connected with the source electrodes of two transistors in the P-type input pair transistor;
the drain electrode of the N-type tail current source is connected with the source electrode of the N-type input pair transistor, and the source electrode of the N-type tail current source is grounded;
The cascode output stage comprises a first current source, a second current source, a first N-type common-gate tube, a second N-type common-gate tube and a current mirror;
the drain electrode of the first current source is respectively connected with the drain electrode of the first P-type transistor and the source electrode of the first N-type common-gate transistor, and the drain electrode of the first N-type common-gate transistor is connected with the current mirror;
And the drain electrode of the second current source is respectively connected with the drain electrode of the second P-type transistor and the source electrode of the second N-type common-gate transistor, and the drain electrode of the second N-type common-gate transistor is connected with the current mirror.
As an implementation mode of the invention, the power tube is a P-type MOS tube.
As an embodiment of the present invention, the off-chip capacitance is a Murata ceramic capacitance of 2.2 uF.
The invention has the beneficial effects that: the wide-input low-dropout linear voltage stabilizing circuit provided by the invention can drive the off-chip large capacitor and realize the low-voltage design of the LDO circuit. In the invention, the buffer stage formed by rail-to-rail OTA (rail-to-rail operational transconductance amplifier) can not introduce extra voltage drop, so that the LDO has a wider working voltage range. In addition, the invention uses dynamic bias, which is very beneficial to the realization of low power consumption and optimizes the transient characteristic of the LDO circuit to a certain extent.
Drawings
FIG. 1 is a schematic diagram of an LDO circuit with a buffer stage according to the prior art.
FIG. 2 is a schematic diagram of an LDO circuit with a buffer stage according to the prior art.
FIG. 3 is a schematic diagram of a wide input LDO circuit with an off-chip capacitor according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a comparing circuit, a detecting feedback circuit and a frequency compensating circuit according to an embodiment of the invention.
FIG. 5 is a schematic diagram of a wide input buffer stage and a dynamic bias circuit according to an embodiment of the present invention.
Fig. 6 is a schematic diagram showing the composition of a simplified model of small signal analysis according to an embodiment of the present invention.
Fig. 7 is a schematic diagram showing the composition of a simplified model of small signal analysis according to an embodiment of the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
For a further understanding of the present invention, preferred embodiments of the invention are described below in conjunction with the examples, but it should be understood that these descriptions are merely intended to illustrate further features and advantages of the invention, and are not limiting of the claims of the invention.
The description of this section is intended to be illustrative of only a few exemplary embodiments and the invention is not to be limited in scope by the description of the embodiments. It is also within the scope of the description and claims of the invention to interchange some of the technical features of the embodiments with other technical features of the same or similar prior art.
The invention discloses a wide-input low dropout linear voltage regulator circuit, FIG. 3 is a schematic diagram of the wide-input low dropout linear voltage regulator circuit (LDO circuit) with an off-chip capacitor according to an embodiment of the invention; referring to fig. 3, in an embodiment of the present invention, the LDO circuit includes: the dynamic bias circuit comprises a comparison circuit 1, a dynamic bias circuit 2, a wide input buffer stage circuit 3, a power tube 4, a detection feedback circuit 5, a frequency compensation circuit 6 and an off-chip capacitor 7.
The input voltage is respectively connected with the comparison circuit 1, the dynamic bias circuit 2 and the power tube 4; the input end of the comparison circuit 1 is respectively connected with a reference voltage and a detection feedback circuit 5, and the output end of the comparison circuit 1 is connected with the input end of the wide input buffer stage circuit 3. The comparison circuit 1 compares the feedback voltage with the reference voltage Vref, adjusts the power tube 4 according to the comparison result, and ensures stable output voltage.
The output end of the dynamic bias circuit 2 is connected with the input end of the wide input buffer stage circuit 3, and the output end of the wide input buffer stage circuit 3 is connected with the power tube 4. The dynamic bias circuit 2 dynamically adjusts the current of the wide input buffer stage circuit 3 according to the magnitude of the load current, so as to realize that the LDO circuit drives a large load with a small quiescent current. In an embodiment, when the load is switched from large to small, due to the existence of the dynamic bias circuit 2, the slew rate (SLEWING RATE) of the output end of the wide input buffer stage circuit 3 is large, so that the charging of the grid capacitor of the power tube 4 is accelerated, the output voltage reaches a stable value more quickly, and the enhancement of transient characteristics is realized.
The wide input buffer stage circuit 3 is arranged between the comparison circuit 1 and the power tube 4, drives a capacitor connected with the grid electrode of the power tube 4, and plays an isolating role. The load of the LDO circuit varies widely, and in one embodiment, the load current may vary from 1uA to 100mA, spanning 5 orders of magnitude. The gate voltage of the power transistor 4 has a wide variation range, and thus the wide input buffer stage circuit 3 is required to have a wide input voltage range. The power tube 4 is connected to an input and an output and has a relatively large size and thus a large current output capability. The detection feedback circuit 5 samples the output voltage and feeds back the sampling result to the input terminal of the comparison circuit 1.
The output end of the frequency compensation circuit 6 is respectively connected with the power tube 4 and the detection feedback circuit 5; the output voltage is respectively connected with the power tube 4, the off-chip capacitor 7 and the detection feedback circuit 5. The detection feedback circuit 5 is configured to sample the output voltage and feed back the sampling result to the input terminal of the comparison circuit 1. The frequency compensation circuit 6 is used for compensating the frequency of the LDO circuit, so as to ensure the stability of the LDO circuit in the whole load range. The off-chip capacitor 7 improves transient characteristics of the output voltage of the LDO circuit, and plays a role in loop stability.
FIG. 4 is a schematic diagram of a comparing circuit, a detecting feedback circuit and a frequency compensating circuit according to an embodiment of the present invention; referring to fig. 4, in an embodiment of the present invention, the comparing circuit 1 includes a folded cascode operational amplifier as an error amplifier. In one embodiment, the error amplifier includes a P-type tail current source 200, a first P-type input amplifier 201, a second P-type input amplifier 202, a first N-type current source 203, a second N-type current source 204, a first common-gate transistor 205, a second common-gate transistor 206, a first P-type current mirror load 207, and a second P-type current mirror load 208. The input voltage is respectively connected to the source of the P-type tail current source 200, the source of the first P-type current mirror load 207 and the source of the second P-type current mirror load 208. The drains of the P-type tail current sources 200 are respectively connected to the sources of the first P-type input amplifying tube 201 and the second P-type input amplifying tube 202. The drain electrode of the first P-type input amplifying tube 201 is respectively connected with the source electrode of the first common gate transistor 205 and the drain electrode of the first N-type current source 203; the drain of the second P-type input amplifier 202 is connected to the source of the second common-gate transistor 206 and the drain of the second N-type current source 204, respectively. The gate of the first P-type current mirror load 207 is connected to the gate of the second P-type current mirror load 208, the drain of the first P-type current mirror load 207, and the drain of the first common-gate transistor 205, respectively; the drain of the second P-type current mirror load 208 is connected to the drain of the second common-gate transistor 206.
With continued reference to fig. 4, in an embodiment of the present invention, the detection feedback circuit includes a first polysilicon resistor 211 and a second polysilicon resistor 212; the drain electrode of the power tube is connected to the first end of the first polysilicon resistor 211, and the gate electrode of the first P-type input amplifying tube 201 is respectively connected to the second end of the first polysilicon resistor 211 and the first end of the second polysilicon resistor 212. The change of the output voltage is detected by means of the resistive voltage division and the detected voltage value is returned to the input of the error amplifier.
As shown in fig. 4, in an embodiment of the present invention, the frequency compensation circuit 6 includes a compensation capacitor 213 and a cascode circuit; the cascode circuit comprises a first N-type current source 203, a second N-type current source 204, a first cascode transistor 205, and a second cascode transistor 206; the cascode circuit is shared with an error amplifier. One end of the compensation capacitor 213 is connected to the output terminal Vout of the LDO circuit, and the other end is connected to the source of the second common-gate transistor 206, so as to form a compensation mode based on Current Buffer. This current buffer based frequency compensation approach has two main advantages over conventional Miller (Miller) compensation. On one hand, the structure can push the non-main pole point of the second stage to a higher frequency, so that the bandwidth of a loop can be effectively improved; on the other hand, the structure eliminates the zero point of the right half plane, also provides the zero point of the left half plane, and further optimizes the frequency characteristic of the system.
FIG. 5 is a schematic diagram of a wide input buffer stage and a dynamic bias circuit according to an embodiment of the present invention; referring to fig. 5, in an embodiment of the present invention, the dynamic bias circuit 2 includes a first resistor 301, a first MOS transistor 302, a second MOS transistor 303, a third MOS transistor 304, a fourth MOS transistor 305, a second resistor 306, a fifth MOS transistor 307, and a sixth MOS transistor 308. A first end of the first resistor 301 is connected to the gate of the first MOS transistor 302 and the gate of the fourth MOS transistor 305; the second end of the first resistor 301 is connected to the drain of the first MOS transistor 302, the gate of the second MOS transistor 303, and the gate of the third MOS transistor 304, respectively. The input voltage is connected to the source of the sixth MOS transistor 308, and the gate of the sixth MOS transistor 308 is connected to the drain of the fifth MOS transistor 307 and the first end of the second resistor 306, respectively; the drain of the sixth MOS transistor 308 is connected to the source of the fifth MOS transistor 307. The gate of the fifth MOS transistor 307 is connected to the second end of the second resistor 306 and the drain of the fourth MOS transistor 305, respectively; the source electrode of the fourth MOS transistor 305 is connected to the drain electrode of the third MOS transistor 304, and the source electrode of the third MOS transistor 304 is connected to the source electrode of the second MOS transistor 303.
In one embodiment, as shown in fig. 5, the gates of the transistors 324 are connected in series with a current limiting resistor 323,324, and the gates of the transistors are connected to the power transistor gate, so that different output currents Iab can be obtained according to the load current. The current Iab is added to the input bias current Ibias to form the dynamic bias circuit 2.
In one embodiment of the present invention, the wide input buffer stage 3 comprises a transconductance amplifier OTA connected in a unity gain feedback mode. Because the load variation range of the LDO is large, the gate voltage variation range of the power tube is also very large. When the power tube is in idle load, the grid voltage of the power tube is close to the power supply voltage; and when reloading, the gate voltage of the power is lower. In order to meet the application requirement of low voltage, the lower the grid voltage of the power tube is, the better the grid voltage of the power tube is under the premise of ensuring the normal working state of the error amplifier. Based on the above considerations, the input of the buffer stage should have a wide voltage range, where a rail-to-rail (rail-to-rail) input configuration is used.
Referring to fig. 5, the wide input buffer stage circuit includes a rail-to-rail input stage and a cascode output stage. The rail-to-rail input stage comprises a P-type tail current source 309, an N-type tail current source 313, an N-type input pair transistor and a P-type input pair transistor; the N-type input pair transistors include a first N-type transistor 311a and a second N-type transistor 312a, and the P-type input pair transistors include a first P-type transistor 311b and a second P-type transistor 312b. The source of the P-type tail current source 309 is connected to the input voltage, the gate of the P-type tail current source 309 is connected to the gate of the sixth MOS transistor 308, and the drain of the P-type tail current source 309 is connected to the sources of two transistors in the P-type input pair transistor, respectively. The drain of the N-type tail current source 313 is connected to the source of the N-type input pair transistor, and the source of the N-type tail current source 313 is grounded.
The cascode output stage includes a first current source 315, a second current source 316, a first N-type cascode tube 317, a second N-type cascode tube 318, and a current mirror. The drain of the first current source 315 is connected to the drain of the first P-type transistor 311b and the source of the first N-type common-gate tube 317, respectively, and the drain of the first N-type common-gate tube 317 is connected to the current mirror. The drain of the second current source 316 is connected to the drain of the second P-type transistor 312b and the source of the second N-type common-gate transistor 318, respectively, and the drain of the second N-type common-gate transistor 318 is connected to the current mirror.
In an embodiment of the present invention, the power transistor 4 has a large gate capacitance, and the current of the buffer stage has a certain minimum requirement in order to drive the gate capacitance. In addition, in order to ensure that the introduction of the buffer stage does not have obvious influence on loop stability, the bandwidth of the buffer stage should be far greater than the loop bandwidth of the LDO circuit. In fact, the loop bandwidth of the LDO circuit increases along with the increase of the load, and the requirement on the bandwidth of the buffer stage also increases along with the increase of the load, so that the introduction of the dynamic bias can effectively reduce the quiescent current of the buffer stage and also effectively reduce the quiescent current of the whole LDO circuit.
In an embodiment of the present invention, the power transistor is of PMOS type, as shown in fig. 4. The power tube connects the input and the output to provide enough current for the load. Compared with NMOS, PMOS is selected as the power tube, so that small input-output voltage difference can be realized, and a certain small signal gain can be provided for the loop. In addition, PMOS is more advantageous than NMOS in the face of electrostatic discharge (ESD) phenomena. In one embodiment, the reference voltage Vref is only 0.6V, and the input device selects a P-type MOS tube; the folded operational amplifier can be very conveniently introduced into an efficient frequency compensation mode.
In one embodiment of the invention, the off-chip capacitance is a Murata ceramic capacitance of 2.2 uF. The LDO scheme adopts a high-efficiency frequency compensation mode, and reduces the requirement on the Equivalent Series Resistance (ESR) of the off-chip capacitor. The LDO can operate stably as long as the ESR of the capacitor is less than 200 milliohms.
The invention uses rail-to-rail OTA as the buffer stage of LDO, effectively reduces the power supply voltage requirement of the circuit, and realizes the design of wide input LDO with off-chip large capacitance. In addition, the invention introduces dynamic bias for the buffer stage of the LDO circuit, thereby effectively reducing the static power consumption of the LDO. The invention provides a wide-input and low-power-consumption implementation scheme of LDO.
Loop stability analysis of the LDO circuit in an embodiment of the present invention is performed as follows, which is also an important feature of the LDO circuit. The resulting loop transfer function may be different due to ring breaks at different locations. In order to completely analyze the frequency characteristics of the LDO, the loop is disconnected at two positions, and the obtained loop bandwidth and the pole are distinguished by using subscripts loop1 and loop 2.
In the first case, the loop is disconnected at the input of the error amplifier. The small signal model of the LDO of the embodiment is simplified to obtain an analytical model as shown in fig. 6. Fig. 6 g m1、gm3、gmp shows transconductance parameters of the first P-type input amplifier 201, the second common-gate transistor 206, and the power MOS of fig. 4, respectively; r o1、C1、Roeq、CL is the impedance of the output end of the error amplifier, the capacitance and the impedance and the capacitance of the output end of the LDO respectively; c C is current buffer compensation capacitor; and B is a feedback coefficient of the detection feedback module. The loop is broken between the feedback block and the error amplifier, and the signals on both sides of the break point are assumed to be T in、Tout, respectively.
Firstly, considering the influence of a buffer stage on loop frequency characteristics; the buffer stage is constituted by a unit fed-back wide input operational amplifier. Assuming that the op-amp is a single-pole characteristic, its unity gain bandwidth is GBW OTA. The input/output transfer function of the buffer stage is easy to obtain through deduction and simplification:
For the LDO loop, the buffer stage introduces a pole with a frequency at GBW OTA. Furthermore, the buffer stage introduces a low frequency gain of 1 at frequencies much less than GBW OTA. From the above, it is easy to conclude that as long as GBW OTA is much larger (typically more than 5 times) than the loop bandwidth of the LDO, the impact of the buffer stage on the frequency response of the LDO is negligible.
According to the small signal simplified model shown in fig. 6, the following expression is easily obtained:
through simulation of actual parameters of a circuit, the following steps are generally:
Due to the large off-chip capacitance, the LDO has good stability under light load. When the load current of the LDO is large enough, with g mpro1CC＞＞CL, the above expression can be simplified as:
the unit gain bandwidth and the second point of the easy-to-obtain LDO are respectively According to both expressions, better stability can be obtained by increasing the compensation capacitance C C or by decreasing the load capacitance C L.
In the second case, the loop is disconnected at the output of the error amplifier. Simplifying the small signal model of the LDO of the embodiment to obtain an analysis model shown in FIG. 7; the meaning of each symbol in fig. 7 is the same as in fig. 6. The following expression is readily obtained from analytical deductions
The third pole has a greater influence on the phase margin of the loop due to the cancellation effect of the zero on the second pole. After simplification, it is obvious thatThese two expressions indicate that to improve loop stability, either the compensation capacitance C C should be reduced or the load capacitance C L should be increased.
Both methods of opening the loop result in two loop expressions, both of which reflect the frequency characteristics of the system from some aspect. The phase margin of loop1 and loop2 are mutually influencing and should be taken into account in a compromise. In practical applications, the size of the load capacitor is generally determined first, and then the compensation capacitor is adjusted to obtain good system stability.
In summary, the LDO circuit provided by the present invention can drive the off-chip large capacitor to realize the low voltage design of the LDO circuit. In the invention, the buffer stage formed by the rail-to-rail OTA can not introduce extra voltage drop, so that the LDO has a wider working voltage range. In addition, the invention uses dynamic bias, which is very beneficial to the realization of low power consumption and optimizes the transient characteristic of the LDO circuit to a certain extent.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The description and applications of the present invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Effects or advantages referred to in the embodiments may not be embodied in the embodiments due to interference of various factors, and description of the effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and alternatives and equivalents of the various components of the embodiments are known to those of ordinary skill in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other assemblies, materials, and components, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.
Claims (10)
1. A wide input low dropout linear voltage regulator circuit, the low dropout linear voltage regulator circuit comprising: the device comprises a comparison circuit, a dynamic bias circuit, a wide input buffer stage circuit, a power tube, a detection feedback circuit, a frequency compensation circuit and an off-chip capacitor;
The input voltage is respectively connected with the comparison circuit, the dynamic bias circuit and the power tube; the input end of the comparison circuit is respectively connected with the reference voltage and the detection feedback circuit, and the output end of the comparison circuit is connected with the input end of the wide input buffer stage circuit;
the comparison circuit compares the feedback voltage with the reference voltage, adjusts the power tube according to the comparison result, and ensures stable output voltage;
The output end of the dynamic bias circuit is connected with the bias input end of the wide input buffer stage circuit, and the output end of the wide input buffer stage circuit is connected with the power tube;
The dynamic bias circuit dynamically adjusts the current of the wide input buffer stage circuit according to the magnitude of the load current, so that the LDO circuit drives a large load with a small static current;
The wide input buffer stage circuit is arranged between the comparison circuit and the power tube, drives a capacitor connected with the grid electrode of the power tube, and plays an isolating role;
the output end of the frequency compensation circuit is respectively connected with the power tube and the detection feedback circuit; the output voltage is respectively connected with the power tube, the off-chip capacitor and the detection feedback circuit;
The detection feedback circuit is used for sampling the output voltage and feeding back the sampling result to the input end of the comparison circuit;
the frequency compensation circuit is used for compensating the frequency of the LDO circuit and ensuring the stability of the LDO circuit in the whole load range.
2. The wide-input low-dropout linear voltage regulator circuit according to claim 1, wherein:
when the load is switched from large to small, the swing rate of the output end of the wide input buffer stage circuit is large due to the existence of the dynamic bias circuit, so that the charging of the grid capacitor of the power tube is accelerated, the output voltage reaches a stable value more quickly, and the transient characteristic is enhanced.
3. The wide-input low-dropout linear voltage regulator circuit according to claim 1, wherein:
The off-chip capacitor is used for improving transient characteristics of the output voltage of the LDO circuit and plays a role in loop stability.
4. The wide-input low-dropout linear voltage regulator circuit according to claim 1, wherein:
the comparison circuit includes an error amplifier including a folded cascode operational amplifier.
5. The wide-input low-dropout linear voltage regulator circuit according to claim 4, wherein:
the error amplifier comprises a P-type tail current source, a first P-type input amplifying tube, a second P-type input amplifying tube, a first N-type current source, a second N-type current source, a first common-gate transistor, a second common-gate transistor, a first P-type current mirror load and a second P-type current mirror load;
The input voltage is respectively connected with the source electrode of the P-type tail current source, the source electrode of the first P-type current mirror load and the source electrode of the second P-type current mirror load;
the drain electrode of the P-type tail current source is respectively connected with the source electrodes of the first P-type input amplifying tube and the second P-type input amplifying tube;
the drain electrode of the first P-type input amplifying tube is respectively connected with the source electrode of the first common gate transistor and the drain electrode of the first N-type current source; the drain electrode of the second P-type input amplifying tube is respectively connected with the source electrode of the second common-gate transistor and the drain electrode of the second N-type current source;
the grid electrode of the first P-type current mirror load is respectively connected with the grid electrode of the second P-type current mirror load, the drain electrode of the first P-type current mirror load and the drain electrode of the first common-gate transistor; and the drain electrode of the second P-type current mirror load is connected with the drain electrode of the second common-gate transistor.
6. The wide-input low-dropout linear voltage regulator circuit according to claim 5, wherein:
The detection feedback circuit comprises a first polysilicon resistor and a second polysilicon resistor; the drain electrode of the power tube is connected with the first end of the first polysilicon resistor, and the grid electrode of the first P-type input amplifying tube is respectively connected with the second end of the first polysilicon resistor and the first end of the second polysilicon resistor;
The change of the output voltage is detected by means of the resistive voltage division and the detected voltage value is returned to the input of the error amplifier.
7. The wide-input low-dropout linear voltage regulator circuit according to claim 1, wherein:
The compensation circuit comprises a compensation capacitor and a cascode circuit; the cascode circuit comprises a first N-type current source, a second N-type current source, a first common-gate transistor and a second common-gate transistor; the cascode circuit is shared by the error amplifier;
One end of the compensation capacitor is connected with the output end Vout of the LDO circuit, and the other end of the compensation capacitor is connected with the source electrode of the second common-gate transistor to form a compensation mode based on a current buffer.
8. The wide-input low-dropout linear voltage regulator circuit according to claim 1, wherein:
The dynamic bias circuit comprises a first resistor, a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a second resistor, a fifth MOS tube, a sixth MOS tube, a current limiting resistor and a seventh MOS tube;
The first end of the first resistor is connected with the grid electrode of the first MOS tube and the grid electrode of the fourth MOS tube; the second end of the first resistor is respectively connected with the drain electrode of the first MOS tube, the grid electrode of the second MOS tube and the grid electrode of the third MOS tube;
the input voltage is connected with the source electrode of the sixth MOS tube, and the grid electrode of the sixth MOS tube is respectively connected with the drain electrode of the fifth MOS tube and the first end of the second resistor; the drain electrode of the sixth MOS tube is connected with the source electrode of the fifth MOS tube;
the grid electrode of the fifth MOS tube is respectively connected with the second end of the second resistor and the drain electrode of the fourth MOS tube; the source electrode of the fourth MOS tube is connected with the drain electrode of the third MOS tube, and the source electrode of the third MOS tube is connected with the source electrode of the second MOS tube.
9. The wide-input low-dropout linear voltage regulator circuit according to claim 1, wherein:
The wide input buffer stage circuit comprises a rail-to-rail input stage and a common-source common-gate output stage;
the rail-to-rail input stage comprises a P-type tail current source, an N-type input pair transistor and a P-type input pair transistor; the N-type input pair transistors comprise a first N-type transistor and a second N-type transistor, and the P-type input pair transistors comprise a first P-type transistor and a second P-type transistor;
The source electrode of the P-type tail current source is connected with the input voltage, the grid electrode of the P-type tail current source is connected with the grid electrode of the sixth MOS tube, and the drain electrodes of the P-type tail current source are respectively connected with the source electrodes of two transistors in the P-type input pair transistor;
the drain electrode of the N-type tail current source is connected with the source electrode of the N-type input pair transistor, and the source electrode of the N-type tail current source is grounded;
The cascode output stage comprises a first current source, a second current source, a first N-type common-gate tube, a second N-type common-gate tube and a current mirror;
the drain electrode of the first current source is respectively connected with the drain electrode of the first P-type transistor and the source electrode of the first N-type common-gate transistor, and the drain electrode of the first N-type common-gate transistor is connected with the current mirror;
And the drain electrode of the second current source is respectively connected with the drain electrode of the second P-type transistor and the source electrode of the second N-type common-gate transistor, and the drain electrode of the second N-type common-gate transistor is connected with the current mirror.
10. The wide-input low-dropout linear voltage regulator circuit according to claim 1, wherein:
The power tube is a P-type MOS tube;
the off-chip capacitance is a Murata ceramic capacitance of 2.2 uF.
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| CN112000169B (en) * | 2020-09-02 | 2022-03-11 | 恒烁半导体(合肥)股份有限公司 | Current buffer circuit and application thereof |
| CN113741604B (en) * | 2021-07-27 | 2022-08-30 | 西安电子科技大学 | Low-power-consumption and quick transient response numerical control LDO circuit |
| CN113625810B (en) * | 2021-07-29 | 2022-11-11 | 西安电子科技大学 | Low-power-consumption full-range stable LDO linear voltage regulator without off-chip capacitor |
| CN113672019B (en) * | 2021-08-18 | 2022-12-06 | 成都华微电子科技股份有限公司 | Dynamic bias high PSRR low dropout regulator |
| CN114527820B (en) * | 2022-02-15 | 2024-04-12 | 珠海全志科技股份有限公司 | Voltage stabilizer circuit and electronic equipment |
| CN114879794B (en) * | 2022-05-25 | 2023-07-07 | 西安微电子技术研究所 | On-chip capacitor implementation circuit for LDO frequency compensation and LDO circuit |
| CN115454186B (en) * | 2022-09-15 | 2023-05-05 | 芯洲科技(北京)股份有限公司 | Linear voltage regulator for power supply system and power supply system |
| CN115437445B (en) * | 2022-10-20 | 2023-12-15 | 群联电子股份有限公司 | Voltage stabilizing circuit module, memory storage device and voltage control method |
| CN115373458B (en) * | 2022-10-24 | 2022-12-27 | 成都市安比科技有限公司 | LDO power supply with output voltage quick response |
| CN117331395B (en) * | 2023-08-30 | 2024-04-05 | 江苏帝奥微电子股份有限公司 | Limit load jump dynamic acceleration circuit suitable for LDO |
| CN118264210B (en) * | 2024-04-01 | 2024-09-03 | 合肥市山海半导体技术有限公司 | LDO circuit and amplifier loop compensation circuit and method thereof |
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| US7495422B2 (en) * | 2005-07-22 | 2009-02-24 | Hong Kong University Of Science And Technology | Area-efficient capacitor-free low-dropout regulator |
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| CN109710017B (en) * | 2019-02-12 | 2024-03-19 | 麦堆微电子技术（上海）有限公司 | Low-dropout linear voltage regulator system |
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