CN209265312U - Low pressure difference linear voltage regulator system - Google Patents
Low pressure difference linear voltage regulator system Download PDFInfo
- Publication number
- CN209265312U CN209265312U CN201920191569.9U CN201920191569U CN209265312U CN 209265312 U CN209265312 U CN 209265312U CN 201920191569 U CN201920191569 U CN 201920191569U CN 209265312 U CN209265312 U CN 209265312U
- Authority
- CN
- China
- Prior art keywords
- oxide
- semiconductor
- type metal
- connect
- drain terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
A kind of low pressure difference linear voltage regulator system, comprising: error amplifier, the inverting input terminal and reference voltage V of error amplifierREFConnection, the normal phase input end of error amplifier and the output voltage V of LDOOUTConnection；Power tube, the grid end of power tube and the output end of error amplifier connect, and the source of power tube is connect with supply voltage VDD, output voltage V of the drain terminal of power tube as LDOOUT；Transfer efficiency enhances circuit, and transfer efficiency enhances one end of circuit and the normal phase input end of error amplifier and the drain terminal of power tube connects, and transfer efficiency enhances the other end ground connection of circuit；The grid end of slew rate enhancing circuit, slew rate enhancing circuit output end and power tube connects.On the one hand the utility model improves the transient response of LDO using slew rate enhancing circuit for the limitation of Capless LDO on ordinary tablet；On the other hand high conversion efficiency is realized using transfer efficiency enhancing circuit, is conducive to extend the service life of power supply unit.
Description
Technical field
The utility model relates to electricity field more particularly to electric power management circuit, especially a kind of low pressure difference linearity pressure stabilizing
Device system.
Background technique
In the prior art, low pressure difference linear voltage regulator system includes strap two type of outer load capacitance and on piece Capless
Type, the former is effectively improved the mapping of circuit by the outer bulky capacitor (microfarad magnitude) of piece, but needs additional pin, and one
Aspect increases the difficulty of encapsulation, on the other hand increases and manufactures cost.The latter is fully integrated on chip, is suitable for
SOC system can be avoided and increase additional pin, reduce encapsulation difficulty, save cost of manufacture.Although on piece Capless LDO
It avoids using additional pin, but the capacitance of the on-chip capacitance due to using (pico farad grade) is far smaller than the outer capacitor of piece, is answering
When for the load of variation at a high speed, transient response is unable to satisfy the application of high speed circuit, even if some designs are by increasing LDO
Quiescent dissipation, to guarantee mapping that LDO has had, but big power consumption consumes the energy content of battery too fast, greatly subtracts
The weak cruising ability of product.The disadvantage of common Capless LDO has largely limited to the use of on piece LDO.In addition when
The intelligence of preceding electronic equipment, the trend of portability, so that electronic product is almost completely dependent on the confession of the chemical cells such as lithium battery
Electricity, LDO is as electric power management circuit, and the transfer efficiency of higher work can effectively extend the service life of battery, and mesh
In preceding research, the transfer efficiency of LDO circuit work is lower.
Utility model content
In view of the above technical problems, the purpose of this utility model is to provide a kind of low voltage differences for solving above-mentioned technical problem
Linear voltage regulator system.
In order to solve the above technical problems, the low pressure difference linear voltage regulator system of the utility model, comprising:
Error amplifier, the inverting input terminal and reference voltage V of the error amplifierREFConnection, the error are put
The normal phase input end and output voltage V of big deviceOUTConnection；
Power tube, the grid end of the power tube are connect with the output end of the error amplifier, the source of the power tube
It is connect with supply voltage VDD, the drain terminal and LDO output voltage V of the power tubeOUTConnection；
Transfer efficiency enhances circuit, and one end of the transfer efficiency enhancing circuit and the positive of the error amplifier input
The connection of the drain terminal of end and the power tube, the other end ground connection of the transfer efficiency enhancing circuit；
Slew rate enhancing circuit, the slew rate enhancing circuit output end are connect with the output end of the error amplifier；Wherein
The slew rate enhancing circuit includes that overshoot inhibits unit and owe punching to inhibit unit.
The overshoot inhibits the unit to include:
The grid end of 9th p-type metal-oxide-semiconductor, the 9th p-type metal-oxide-semiconductor is connect with bias voltage VBP1, the 9th p-type MOS
The source of pipe is connect with VDD；
The grid end of tenth p-type metal-oxide-semiconductor, the tenth p-type metal-oxide-semiconductor is connect with bias voltage VBP1, the tenth p-type MOS
The source of pipe is connect with VDD；
The grid end of 11st p-type metal-oxide-semiconductor, the 11st p-type metal-oxide-semiconductor is connect with bias voltage VBP1, the 11st P
The source of type metal-oxide-semiconductor is connect with VDD；
12nd p-type metal-oxide-semiconductor, the source of the 12nd p-type metal-oxide-semiconductor and the drain terminal of the 11st p-type metal-oxide-semiconductor connect
It connects, the drain terminal and driving voltage V of the 12nd p-type metal-oxide-semiconductorPGConnection；
The drain terminal of 13rd N-type metal-oxide-semiconductor, the 13rd N-type metal-oxide-semiconductor is connect with the drain terminal of the 9th p-type metal-oxide-semiconductor,
The drain terminal of the 13rd N-type metal-oxide-semiconductor is connect with the grid end of the 13rd N-type metal-oxide-semiconductor, the source of the 13rd N-type metal-oxide-semiconductor
End ground connection；
14th N-type metal-oxide-semiconductor, the drain terminal of the 14th N-type metal-oxide-semiconductor and the drain terminal of the tenth p-type metal-oxide-semiconductor and described
The grid end of 12nd p-type metal-oxide-semiconductor connects, and the grid end of the 14th N-type metal-oxide-semiconductor and the grid end of the 13rd N-type metal-oxide-semiconductor connect
It connects, the source ground connection of the 14th N-type metal-oxide-semiconductor；
First capacitor device, one end of the first capacitor device respectively with the drain terminal of the 9th p-type metal-oxide-semiconductor, the described tenth
The grid end of three N-type metal-oxide-semiconductors and the connection of the grid end of the 14th N-type metal-oxide-semiconductor, the other end output voltage of the first capacitor device
VOUTConnection.
The owe punching inhibits the unit to include:
The grid end of 15th N-type metal-oxide-semiconductor, the 15th N-type metal-oxide-semiconductor is connect with bias voltage VBN1, the 15th N
The source of type metal-oxide-semiconductor is grounded；
The grid end of 16th N-type metal-oxide-semiconductor, the 16th N-type metal-oxide-semiconductor is connect with bias voltage VBN1, the 16th N
The source of type metal-oxide-semiconductor is grounded；
The grid end of 17th N-type metal-oxide-semiconductor, the 17th N-type metal-oxide-semiconductor is connect with bias voltage VBN1, the 17th N
The source of type metal-oxide-semiconductor is grounded；
The source of 18th N-type metal-oxide-semiconductor, the 18th N-type metal-oxide-semiconductor is connect with the 17th N-type metal-oxide-semiconductor drain terminal,
The drain terminal and driving voltage V of the 18th N-type metal-oxide-semiconductorPGConnection；
13rd p-type metal-oxide-semiconductor, the drain terminal of the 13rd p-type metal-oxide-semiconductor and the drain terminal of the 15th N-type metal-oxide-semiconductor connect
It connects, the source of the 13rd p-type metal-oxide-semiconductor is connect with VDD, the drain terminal of the 13rd p-type metal-oxide-semiconductor and the 13rd p-type
The grid end of metal-oxide-semiconductor connects；
14th p-type metal-oxide-semiconductor, the grid end of the 14th p-type metal-oxide-semiconductor and the grid end of the 13rd p-type metal-oxide-semiconductor connect
Connect, the drain terminal of the 14th p-type metal-oxide-semiconductor respectively with the drain terminal and the 18th N-type metal-oxide-semiconductor of the 16th N-type metal-oxide-semiconductor
Grid end connection；
Second capacitor, one end of second capacitor respectively with the grid end of the 13rd p-type metal-oxide-semiconductor and described
The grid end of 14 p-type metal-oxide-semiconductors connects, the other end output voltage V of the first capacitor deviceOUTConnection.
It further include biasing circuit, the biasing circuit includes:
Tenth N-type metal-oxide-semiconductor, the drain terminal and reference voltage V of the tenth N-type metal-oxide-semiconductorREFConnection, the tenth N-type
The source of metal-oxide-semiconductor is grounded, and the grid end of the tenth N-type metal-oxide-semiconductor is connect with bias voltage VBN1；
8th N-type metal-oxide-semiconductor, the source ground connection of the 8th N-type metal-oxide-semiconductor, the grid end and biasing of the 8th N-type metal-oxide-semiconductor
Voltage VBN1 connection；
9th N-type metal-oxide-semiconductor, the source ground connection of the 9th N-type metal-oxide-semiconductor, the drain terminal and VBP of the 9th N-type metal-oxide-semiconductor connect
It connects, the grid end of the 9th N-type metal-oxide-semiconductor is connect with bias voltage VBN1；
The drain terminal of 5th p-type metal-oxide-semiconductor, the 5th p-type metal-oxide-semiconductor is connect with the drain terminal of the 8th N-type metal-oxide-semiconductor, described
The source of 5th p-type metal-oxide-semiconductor is connect with VDD, and the drain terminal of the 5th p-type metal-oxide-semiconductor and the grid end of the 5th p-type metal-oxide-semiconductor connect
It connects, the grid end of the 5th p-type metal-oxide-semiconductor is connect with bias voltage VBP1；
The source of 7th p-type metal-oxide-semiconductor, the 7th p-type metal-oxide-semiconductor is connect with VDD, the grid end of the 7th p-type metal-oxide-semiconductor with
VBP connection；
The source of 6th p-type metal-oxide-semiconductor, the 6th p-type metal-oxide-semiconductor is connect with the drain terminal of the 7th p-type metal-oxide-semiconductor, described
The grid end of 6th p-type metal-oxide-semiconductor is connect with VBP, and the drain terminal of the 6th p-type metal-oxide-semiconductor is connect with bias voltage VBP；
The source of 8th p-type metal-oxide-semiconductor, the 8th p-type metal-oxide-semiconductor is connect with VDD, the grid end of the 8th p-type metal-oxide-semiconductor with
Bias voltage VBP1 connection, the drain terminal of the 8th p-type metal-oxide-semiconductor are connect with bias voltage VBN；
The drain terminal of 12nd N-type metal-oxide-semiconductor, the 12nd N-type metal-oxide-semiconductor is connect with bias voltage VBN, the 12nd N
The grid end of type metal-oxide-semiconductor is connect with bias voltage VBN；
11st N-type metal-oxide-semiconductor, the drain terminal of the 11st N-type metal-oxide-semiconductor and the source of the 12nd N-type metal-oxide-semiconductor connect
It connects, the grid end of the 11st N-type metal-oxide-semiconductor is connect with bias voltage VBN, the source ground connection of the 11st N-type metal-oxide-semiconductor.
The error amplifier includes:
The grid end of 19th N-type metal-oxide-semiconductor, the 19th N-type metal-oxide-semiconductor is connect with bias voltage VBN1, the 19th N
The source of type metal-oxide-semiconductor is grounded；
First N-type metal-oxide-semiconductor, the grid end and V of the first N-type metal-oxide-semiconductorOUTConnection, the source of the first N-type metal-oxide-semiconductor with
The drain terminal of the 19th N-type metal-oxide-semiconductor connects；
Second N-type metal-oxide-semiconductor, the grid end and V of the second N-type metal-oxide-semiconductorREFConnection, the source of the second N-type metal-oxide-semiconductor with
The drain terminal of the 19th N-type metal-oxide-semiconductor connects；
The source of first p-type metal-oxide-semiconductor, the first p-type metal-oxide-semiconductor is connect with VDD, the drain terminal of the first p-type metal-oxide-semiconductor with
The drain terminal of the metal-oxide-semiconductor MN1 connects, and the grid end of the first p-type metal-oxide-semiconductor is connect with bias voltage VBP1；
The source of second p-type metal-oxide-semiconductor, the second p-type metal-oxide-semiconductor is connect with VDD, the drain terminal of the second p-type metal-oxide-semiconductor with
The drain terminal of the second N-type metal-oxide-semiconductor connects, and the grid end of the second p-type metal-oxide-semiconductor is connect with bias voltage VBP1；
Third p-type metal-oxide-semiconductor, the source of the third p-type metal-oxide-semiconductor is connect with the drain terminal of the first p-type metal-oxide-semiconductor, described
The grid end of third p-type metal-oxide-semiconductor is connect with bias voltage VBP；
The source of 4th p-type metal-oxide-semiconductor, the 4th p-type metal-oxide-semiconductor is connect with the drain terminal of the second p-type metal-oxide-semiconductor, described
The grid end of 4th p-type metal-oxide-semiconductor is connect with bias voltage VBP；
The drain terminal of 5th N-type metal-oxide-semiconductor, the 5th N-type metal-oxide-semiconductor is connect with the drain terminal of the third p-type metal-oxide-semiconductor, described
The grid end of 5th N-type metal-oxide-semiconductor is connect with bias voltage VBN；
The drain terminal of 6th N-type metal-oxide-semiconductor, the 6th N-type metal-oxide-semiconductor is connect with the drain terminal of the 4th p-type metal-oxide-semiconductor, described
The grid end of 6th N-type metal-oxide-semiconductor is connect with bias voltage VBN；
Third N-type metal-oxide-semiconductor, the drain terminal of the third N-type metal-oxide-semiconductor is connect with the source of the 5th N-type metal-oxide-semiconductor, described
The grid end of third N-type metal-oxide-semiconductor is connect with the drain terminal of the 5th N-type metal-oxide-semiconductor, the source ground connection of the third N-type metal-oxide-semiconductor；
The drain terminal of 4th N-type metal-oxide-semiconductor, the 4th N-type metal-oxide-semiconductor is connect with the source of the 6th N-type metal-oxide-semiconductor, described
The grid end of 4th N-type metal-oxide-semiconductor is connect with the drain terminal of the 5th N-type metal-oxide-semiconductor, the source ground connection of the 4th N-type metal-oxide-semiconductor.
The current efficiency enhances circuit
The source of induction tube, the induction tube is connect with VDD, and the drain terminal of the induction tube is grounded by resistor R, described
Induction tube grid end and driving voltage VPGConnection；
15th p-type metal-oxide-semiconductor, the source and output voltage V of the 15th p-type metal-oxide-semiconductorOUTConnection, the 15th P
The grid end of type metal-oxide-semiconductor is connect with the drain terminal of the induction tube, the drain terminal ground connection of the 15th p-type metal-oxide-semiconductor；
Muller compensation capacitor, one end of the Muller compensation capacitor and driving voltage VPGConnection, the other end and zeroing
Resistor connection；
Zero-regulator resistor device, one end of the zero-regulator resistor device is connect with the other end of the Muller compensation capacitor, described
The other end and output voltage V of zero-regulator resistor deviceOUTConnection；
Third capacitor, one end of the third capacitor are connect with the source of the 15th p-type metal-oxide-semiconductor, and described
The other end of three capacitors is grounded；
Converting resistor, one end of the converting resistor are connect with the grid end of the 15th p-type metal-oxide-semiconductor, and described turn
Change the other end ground connection of resistor.
The utility model low pressure difference linear voltage regulator system compared with the existing technology, has the advantage that
For the limitation of Capless LDO on ordinary tablet, using slew rate enhancing circuit (Enhanced Slew Rate,
ESR circuit) transient response of LDO is improved, the use of the outer bulky capacitor of piece is on the one hand avoided, packaging cost is saved；
On the other hand in the transient response performance for guaranteeing effectively to improve LDO while low-power consumption；Using constant current source, pass through switch
Charge and discharge are controlled, overcomes and is likely to occur the too strong caused big signal of slew rate enhancing circuit under different process angle, temperature, supply voltage
Oscillation problem.The design for current LDO generally there is lower transfer efficiency problem to be improved simultaneously, effectively reduce
The power consumption of circuit, and structure is simple, easy to accomplish.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other spies of the utility model
Sign objects and advantages will become more apparent upon.
Fig. 1 is the utility model low pressure difference linear voltage regulator system principle diagram；
Fig. 2 is the utility model low pressure difference linear voltage regulator system schematic.
Specific embodiment
The utility model low pressure difference linear voltage regulator system is described in further detail with reference to the accompanying drawing.
As shown in Figure 1 and Figure 2, system is by error amplifier 1, slew rate enhancing circuit (ESR circuit), transfer efficiency enhancing electricity
Road, power tube MpowerComposition.VREFIt is the reference voltage provided by other modules, is often provided by band-gap reference circuit,
VDD is input supply voltage signal, can be voltage letter that is battery offer or generating after DC-DC conversion circuit
Number, VOUTIt is the output signal of LDO, for providing the signal of supply voltage to other circuits.
The specific embodiment of the design is as shown in Fig. 2, but be not limited to the form of Fig. 2.Fig. 2 embodiment is by module biasing circuit
4, error amplifier 1, output power pipe and current efficiency enhance circuit 6, and output voltage overshoot inhibits unit 7, and output voltage is owed
Punching inhibits unit 8 to form.Wherein output voltage overshoot inhibits unit 7 and output voltage owe punching that unit 8 is inhibited to collectively constitute Slew Rate
Enhance circuit, to improve output transient response.
Biasing circuit 4 is by the 8th N-type metal-oxide-semiconductor MN8, the 9th N-type metal-oxide-semiconductor MN9, the tenth N-type metal-oxide-semiconductor MN10, the 11st N-type
Metal-oxide-semiconductor MN11, the 12nd N-type metal-oxide-semiconductor MN12 and the 5th p-type metal-oxide-semiconductor MP5, the 6th p-type metal-oxide-semiconductor MP6, the 7th p-type metal-oxide-semiconductor
MP7, the 8th p-type metal-oxide-semiconductor MP8 composition.Wherein IREFIt is provided by other circuit modules, the 8th N-type metal-oxide-semiconductor MN8, the 9th N-type MOS
Pipe MN9, the tenth N-type metal-oxide-semiconductor MN10, the 11st N-type metal-oxide-semiconductor MN11 source be commonly connected to ground, the 5th p-type metal-oxide-semiconductor MP5,
7th p-type metal-oxide-semiconductor MP7, the 8th p-type metal-oxide-semiconductor MP8 source be commonly connected to VDD, the drain terminal and grid of the tenth N-type metal-oxide-semiconductor MN10
End links together, and constitutes diode connection, gives the 8th N-type metal-oxide-semiconductor MN8, the 9th N-type metal-oxide-semiconductor MN9, the tenth N-type metal-oxide-semiconductor
MN10, the 15th N-type metal-oxide-semiconductor MN15, the 16th N-type metal-oxide-semiconductor MN16, the grid end offer mirror image of the 17th N-type metal-oxide-semiconductor MN17 are inclined
Set voltage VBN1.The drain terminal and grid end of 5th p-type metal-oxide-semiconductor MP5 links together, and constitutes diode connection, gives the first p-type MOS
Pipe MP1, the second p-type metal-oxide-semiconductor MP2, the 8th p-type metal-oxide-semiconductor MP8, the 9th p-type metal-oxide-semiconductor MP9, the tenth p-type metal-oxide-semiconductor MP10, the 11st
The grid end of p-type metal-oxide-semiconductor MP11 provides mirror image bias voltage VBP1.The source of 6th p-type metal-oxide-semiconductor MP6 connects the 7th p-type metal-oxide-semiconductor
The drain terminal of MP7, the grid end and drain terminal of the 6th p-type metal-oxide-semiconductor MP6 and grid end, the 9th N-type metal-oxide-semiconductor MN9 of the 7th p-type metal-oxide-semiconductor MP7
Drain terminal link together, to the 5th N-type metal-oxide-semiconductor MN5, the 6th N-type metal-oxide-semiconductor MN6 grid end provide bias voltage VBN.Tenth
The source of the drain terminal and the 12nd N-type metal-oxide-semiconductor MN12 of one N-type metal-oxide-semiconductor MN11 links together, the 12nd N-type metal-oxide-semiconductor MN12's
Grid end and drain terminal link together with the grid end of the 11st N-type metal-oxide-semiconductor MN11, the drain terminal of the 8th p-type metal-oxide-semiconductor MP8, to MP3, the
The grid end of four p-type metal-oxide-semiconductor MP4 provides bias voltage VBP.
Error amplifier circuit 1 uses Foldable cascade structure, structure that however, it is not limited to this in this example.First N
Type metal-oxide-semiconductor MN1, the second N-type metal-oxide-semiconductor MN2 constitute input to pipe, and drain terminal is connected respectively to current source the first p-type metal-oxide-semiconductor MP1, the
The drain terminal of two p-type metal-oxide-semiconductor MP2, grid end are separately connected VOUT、VREF, source is commonly connected to the 19th N-type metal-oxide-semiconductor of micro-current source
The drain terminal of MN0.Tenth N-type metal-oxide-semiconductor MN10 constitutes micro-current source, and grid end is connected to VBN1, source ground connection, drain terminal and the first N-type
Metal-oxide-semiconductor MN1, the second N-type metal-oxide-semiconductor MN2 link together.The grid end connection of first p-type metal-oxide-semiconductor MP1, the second p-type metal-oxide-semiconductor MP2
Together, and with VBP1 be connected, constitute current source, the first p-type metal-oxide-semiconductor MP1, the second p-type metal-oxide-semiconductor MP2 drain terminal difference MP3,
The source of 4th p-type metal-oxide-semiconductor MP4 links together, and collectively constitutes cascode structure, improves output resistance.5th N-type MOS
Pipe MN5, the 6th N-type metal-oxide-semiconductor MN6 grid end link together, and be connected on VBN, the 5th N-type metal-oxide-semiconductor MN5, the 6th N-type
Drain terminal of the drain terminal of metal-oxide-semiconductor MN6 respectively with MP3, the 4th p-type metal-oxide-semiconductor MP4 links together.Third N-type metal-oxide-semiconductor MN3, the 4th N
The grid end of type metal-oxide-semiconductor MN4 links together, wherein the drain terminal of the grid end of third N-type metal-oxide-semiconductor MN3 and the 5th N-type metal-oxide-semiconductor MN5,
The drain terminal of MP3 links together, third N-type metal-oxide-semiconductor MN3, the 4th N-type metal-oxide-semiconductor MN4 source be connected to ground.Third N-type MOS
The low pressure cascode current that pipe MN3, the 4th N-type metal-oxide-semiconductor MN4, the 5th N-type metal-oxide-semiconductor MN5, the 6th N-type metal-oxide-semiconductor MN6 are constituted
Mirror expands the output voltage range of error amplifier while guaranteeing high output resistance, can use smaller size
Power tube MpowerWhen effective driving voltage V is providedPG, the parasitic capacitance over the ground of the grid end of the power tube of smaller size is small, favorably
In the transient response performance for improving LDO.
Output power stage and transfer efficiency enhance circuit 6, and by power tube Mpower, induction tube Msense, Current Voltage turns
Change resistor R, the 7th N-type metal-oxide-semiconductor MN7, Muller compensation capacitor CM, zero-regulator resistor device Rz, third capacitor CLIt constitutes.Wherein
Third capacitor CLOne end connect with the source of the 15th p-type metal-oxide-semiconductor MP0, third capacitor CLThe other end ground connection, Muller
Compensation capacitor CMAnd zero-regulator resistor device RZThe stability for realizing whole system loop avoids system from forming oscillation.Traditional
There is no transfer efficiency to enhance circuit in LDO structure, passes through induction tube Msense, Current Voltage converting resistor in the utility model
The transfer efficiency that R, the 15th p-type metal-oxide-semiconductor MP0 of PMOS tube are constituted enhances circuit to enhance the current efficiency of LDO, effectively extends and supplies
The service life of electric equipment such as battery etc..Its working principle is that: in LDO load current very little, even 0, power tube Mpower
Grid end voltage it is higher, induction tube M at this timesenseThe electric current very little of induction, VSENSEVoltage is very low, and the 15th p-type metal-oxide-semiconductor MP0 is led
Lead to and provides enough electric current I to power tube Mpowerpower, system has enough phase margins when maintaining low current load, protects
Card system is stablized.When the load current of LDO increases, power tube MpowerIn electric current increase, power tube MpowerGrid end voltage
It reduces.Induction tube MsenseGrid end and the grid end of power tube link together, therefore induction tube MsenseGrid end voltage also with
The increase of output load current and reduce, so as to cause induction tube Msense, branch where Current Voltage converting resistor R electric current
Increase, finally makes VSENSEVoltage increases, and the 15th p-type metal-oxide-semiconductor MP0 gradually enters sub-threshold region by saturation region, works as voltage
It is high to a certain extent when, the 15th p-type metal-oxide-semiconductor MP0 cut-off, is no longer MpowerElectric current I is providedpower.Remember other each branch currents
The sum of be Itotal, output current loading is Iout, transfer efficiency calculation formula Eff=VOUTIout/VIN(Ipower+Iout+Itotal)*
100%(1).Enhance the working mechanism of circuit according to transfer efficiency it is found that Ipower is gradually reduced when load current increases, very
Extremely to 0, then being increased according to formula (1) transfer efficiency efficiency.
Output voltage overshoot inhibits unit 7 and output voltage owe punching that unit 8 is inhibited to collectively constitute slew rate enhancing circuit, realizes
The fast transient response of LDO.
Output voltage overshoot inhibits unit 7, by the 9th p-type metal-oxide-semiconductor MP9, the tenth p-type metal-oxide-semiconductor MP10, the 11st p-type MOS
Pipe MP11, the 12nd p-type metal-oxide-semiconductor MP12, the 13rd N-type metal-oxide-semiconductor MN13 of NMOS tube, the 14th N-type metal-oxide-semiconductor MN14 and the first electricity
Container C1 is constituted, and is realized and is inhibited to the overshoot of output voltage VO UT.9th p-type metal-oxide-semiconductor MP9, the tenth p-type metal-oxide-semiconductor MP10, the tenth
The grid end of one p-type metal-oxide-semiconductor MP11 is commonly connected to VBP1, and drain terminal is respectively connected to grid end and the source of the 13rd N-type metal-oxide-semiconductor MN13
It holds, the source of the drain terminal of the 14th N-type metal-oxide-semiconductor MN14, the 12nd p-type metal-oxide-semiconductor MP12；13rd N-type metal-oxide-semiconductor MN13, the tenth
The grid end of four N-type metal-oxide-semiconductor MN14 links together, and the grid end and drain terminal of the 13rd N-type metal-oxide-semiconductor MN13 links together；Tenth
The drain terminal of four N-type metal-oxide-semiconductor MN14 and the drain terminal of the tenth p-type metal-oxide-semiconductor MP10 link together and export to the 12nd p-type metal-oxide-semiconductor
The grid end of MP12, the 12nd p-type metal-oxide-semiconductor MP12's of control opens and shuts off；One end of first capacitor device C1 and output voltage VOUT
It is connected, the other end is connected with the grid end of the 13rd N-type metal-oxide-semiconductor MN13, the 14th N-type metal-oxide-semiconductor MN14.12nd p-type metal-oxide-semiconductor
The drain terminal of MP12 and the grid end V of power tube MpowerPGIt is connected, the 12nd p-type metal-oxide-semiconductor MP12 is as in overshoot suppression circuit
Switching tube.The working mechanism of overshoot suppression circuit is: when circuit work is in stable state, the tenth p-type metal-oxide-semiconductor MP10 is biased in by force
Linear zone, the grid end of the 12nd p-type metal-oxide-semiconductor MP12 are biased in high potential, and the 12nd p-type metal-oxide-semiconductor MP12 works in cut-off region,
It is disconnected with main circuit, does not influence loop stability；When wink of the electric current that the external loading of circuit needs from high current to low current
When state is mutated, VOUTOvershoot phenomenon will occur, V is detected by the high pass branch of C1OUTOvershoot change and be transferred to the 14th N
The grid end of type metal-oxide-semiconductor MN14 causes the electric current of the tenth p-type metal-oxide-semiconductor MP10, the 14th N-type metal-oxide-semiconductor MN14 branch to increase, and the tenth
The grid end of two p-type metal-oxide-semiconductor MP12 is pulled to low potential, the 12nd p-type metal-oxide-semiconductor MP12 conducting, thus the 11st p-type of current source
Metal-oxide-semiconductor MP11 is charged with grid end of the constant image current to power tube Mpower, and the electric current for providing Mpower reduces,
To inhibit VOUTOvershoot, quickly recover to voltage when stable state；To the charging current of power tube by the design
The electric current of 11 p-type metal-oxide-semiconductor MP11 determines that the electric current of the 11st p-type metal-oxide-semiconductor MP11 is not by process corner, temperature and power supply electricity
The influence of pressure can effectively solve the problem that LDO under low input supply voltage, and slew rate enhancing circuit is working properly, and in height input electricity
Under the voltage of source, big signal oscillating problem caused by slew rate enhancing circuit is too strong, to guarantee that fast transient response LDO can work
In wide input supply voltage range.
Output voltage owe punching inhibits unit 8, by the 13rd p-type metal-oxide-semiconductor MP13 of PMOS tube, the 14th p-type metal-oxide-semiconductor MP14,
The 15th N-type metal-oxide-semiconductor MN15 of NMOS tube, the 16th N-type metal-oxide-semiconductor MN16, the 17th N-type metal-oxide-semiconductor MN17 and the second capacitor C2
It constitutes, realizes to output voltage VOUTOwe punching inhibit.15th N-type metal-oxide-semiconductor MN15, the 16th N-type metal-oxide-semiconductor MN16, the 17th
The grid end of N-type metal-oxide-semiconductor MN17 is commonly connected to VBN1, and drain terminal is respectively connected to grid end and the source of the 13rd p-type metal-oxide-semiconductor MP13
It holds, the source of the drain terminal of the 14th p-type metal-oxide-semiconductor MP14, the 18th N-type metal-oxide-semiconductor MN18；13rd p-type metal-oxide-semiconductor MP13, the tenth
The grid end of four p-type metal-oxide-semiconductor MP14 links together, and the grid end and drain terminal of the 13rd p-type metal-oxide-semiconductor MP13 links together；Tenth
The drain terminal of six N-type metal-oxide-semiconductor MN16 and the drain terminal of the 14th p-type metal-oxide-semiconductor MP14 link together and export to the 18th N-type MOS
The grid end of pipe MN18, the 18th N-type metal-oxide-semiconductor MN18's of control opens and shuts off；One end of second capacitor C2 and output voltage
VOUTIt is connected, the other end is connected with the grid end of the 13rd p-type metal-oxide-semiconductor MP13, the 14th p-type metal-oxide-semiconductor MP14.18th N-type MOS
The drain terminal of pipe MN18 and the grid end V of power tube MpowerPGIt is connected, the 18th N-type metal-oxide-semiconductor MN18 is as in owe punching suppression circuit
Switching tube.The working mechanism of owe punching suppression circuit is: when circuit work is in stable state, the 16th N-type metal-oxide-semiconductor MN16 is biased
In strong linear zone, the grid end of the 18th N-type metal-oxide-semiconductor MN18 is biased in low potential, and the 18th N-type metal-oxide-semiconductor MN18 work is being cut
Only area disconnects with main circuit, does not influence loop stability；When the electric current that the external loading of circuit needs is from low current to high current
Transient state mutation when, VOUTOwe punching phenomenon will occur, V is detected by the high pass branch of C2OUTOwe punching change and be transferred to
The grid end of 14 p-type metal-oxide-semiconductor MP14 causes the electric current of the 14th p-type metal-oxide-semiconductor MP14, the 16th N-type metal-oxide-semiconductor MN16 branch to increase
Greatly, the grid end of the 18th N-type metal-oxide-semiconductor MN18 is pulled to high potential, the 18th N-type metal-oxide-semiconductor MN18 conducting, thus current source the tenth
Seven N-type metal-oxide-semiconductor MN17 are discharged with grid end of the constant image current to power tube Mpower, the electric current for providing Mpower
Reduce, to inhibit VOUTOwe punching, quickly recover to voltage when stable state；Power tube grid end is put in the design
Electric current is determined that the electric current of the 17th N-type metal-oxide-semiconductor MN17 is not by process corner, temperature by the electric current of the 17th N-type metal-oxide-semiconductor MN17
And the influence of supply voltage, can effectively solve the problem that LDO under low input supply voltage, slew rate enhancing circuit works normally, and
Under high input supply voltage, big signal oscillating problem caused by slew rate enhancing circuit is too strong, to guarantee fast transient response
LDO can work in wide input supply voltage range.
The preferred embodiment created to the utility model above is illustrated, but the utility model is created not
It is limited to the embodiment, those skilled in the art can also make under the premise of without prejudice to the utility model creative spirit
Various equivalent variation or replacement, these equivalent variation or replacement are all contained in the claim of this application limited range
It is interior.
Claims (6)
1. a kind of low pressure difference linear voltage regulator system characterized by comprising
Error amplifier, the inverting input terminal and reference voltage V of the error amplifierREFConnection, the error amplifier
Normal phase input end and output voltage VOUTConnection；
Power tube, the grid end of the power tube are connect with the output end of the error amplifier, the source and electricity of the power tube
Source voltage VDD connection, the drain terminal and LDO output voltage V of the power tubeOUTConnection；
Transfer efficiency enhance circuit, one end of transfer efficiency enhancing circuit and the normal phase input end of the error amplifier and
The drain terminal of the power tube connects, the other end ground connection of the transfer efficiency enhancing circuit；
Slew rate enhancing circuit, the slew rate enhancing circuit output end and the output end of the error amplifier and the grid end of power tube
Connection；Wherein the slew rate enhancing circuit includes that overshoot inhibits unit and owe punching to inhibit unit.
2. low pressure difference linear voltage regulator system according to claim 1, which is characterized in that the overshoot inhibits unit packet
It includes:
The grid end of 9th p-type metal-oxide-semiconductor, the 9th p-type metal-oxide-semiconductor is connect with bias voltage VBP1, the 9th p-type metal-oxide-semiconductor
Source is connect with VDD；
The grid end of tenth p-type metal-oxide-semiconductor, the tenth p-type metal-oxide-semiconductor is connect with bias voltage VBP1, the tenth p-type metal-oxide-semiconductor
Source is connect with VDD；
The grid end of 11st p-type metal-oxide-semiconductor, the 11st p-type metal-oxide-semiconductor is connect with bias voltage VBP1, the 11st p-type
The source of metal-oxide-semiconductor is connect with VDD；
The source of 12nd p-type metal-oxide-semiconductor, the 12nd p-type metal-oxide-semiconductor is connect with the drain terminal of the 11st p-type metal-oxide-semiconductor, institute
State the drain terminal and driving voltage V of the 12nd p-type metal-oxide-semiconductorPGConnection；
The drain terminal of 13rd N-type metal-oxide-semiconductor, the 13rd N-type metal-oxide-semiconductor is connect with the drain terminal of the 9th p-type metal-oxide-semiconductor, described
The drain terminal of 13rd N-type metal-oxide-semiconductor is connect with the grid end of the 13rd N-type metal-oxide-semiconductor, and the source of the 13rd N-type metal-oxide-semiconductor connects
Ground；
14th N-type metal-oxide-semiconductor, the drain terminal of the 14th N-type metal-oxide-semiconductor and the drain terminal and the described tenth of the tenth p-type metal-oxide-semiconductor
The grid end of two p-type metal-oxide-semiconductors connects, and the grid end of the 14th N-type metal-oxide-semiconductor is connect with the grid end of the 13rd N-type metal-oxide-semiconductor,
The source of the 14th N-type metal-oxide-semiconductor is grounded；
First capacitor device, one end of the first capacitor device respectively with the drain terminal of the 9th p-type metal-oxide-semiconductor, the 13rd N-type
The grid end of metal-oxide-semiconductor and the connection of the grid end of the 14th N-type metal-oxide-semiconductor, the other end output voltage V of the first capacitor deviceOUTEven
It connects.
3. low pressure difference linear voltage regulator system according to claim 2, which is characterized in that the owe punching inhibits unit packet
It includes:
The grid end of 15th N-type metal-oxide-semiconductor, the 15th N-type metal-oxide-semiconductor is connect with bias voltage VBN1, the 15th N-type
The source of metal-oxide-semiconductor is grounded；
The grid end of 16th N-type metal-oxide-semiconductor, the 16th N-type metal-oxide-semiconductor is connect with bias voltage VBN1, the 16th N-type
The source of metal-oxide-semiconductor is grounded；
The grid end of 17th N-type metal-oxide-semiconductor, the 17th N-type metal-oxide-semiconductor is connect with bias voltage VBN1, the 17th N-type
The source of metal-oxide-semiconductor is grounded；
The source of 18th N-type metal-oxide-semiconductor, the 18th N-type metal-oxide-semiconductor is connect with the 17th N-type metal-oxide-semiconductor drain terminal, described
The drain terminal and driving voltage V of 18th N-type metal-oxide-semiconductorPGConnection；
The drain terminal of 13rd p-type metal-oxide-semiconductor, the 13rd p-type metal-oxide-semiconductor is connect with the drain terminal of the 15th N-type metal-oxide-semiconductor, institute
The source for stating the 13rd p-type metal-oxide-semiconductor is connect with VDD, the drain terminal and the 13rd p-type metal-oxide-semiconductor of the 13rd p-type metal-oxide-semiconductor
Grid end connection；
The grid end of 14th p-type metal-oxide-semiconductor, the 14th p-type metal-oxide-semiconductor is connect with the grid end of the 13rd p-type metal-oxide-semiconductor, institute
State the drain terminal of the 14th p-type metal-oxide-semiconductor grid with the drain terminal of the 16th N-type metal-oxide-semiconductor and the 18th N-type metal-oxide-semiconductor respectively
End connection；
Second capacitor, one end of second capacitor grid end and the described 14th with the 13rd p-type metal-oxide-semiconductor respectively
The grid end of p-type metal-oxide-semiconductor connects, the other end output voltage V of the first capacitor deviceOUTConnection.
4. low pressure difference linear voltage regulator system according to claim 3, which is characterized in that it further include biasing circuit, it is described
Biasing circuit includes:
Tenth N-type metal-oxide-semiconductor, the drain terminal and reference voltage V of the tenth N-type metal-oxide-semiconductorREFConnection, the tenth N-type metal-oxide-semiconductor
Source ground connection, the grid end of the tenth N-type metal-oxide-semiconductor connect with bias voltage VBN1；
8th N-type metal-oxide-semiconductor, the source ground connection of the 8th N-type metal-oxide-semiconductor, the grid end and bias voltage of the 8th N-type metal-oxide-semiconductor
VBN1 connection；
9th N-type metal-oxide-semiconductor, the source ground connection of the 9th N-type metal-oxide-semiconductor, the drain terminal of the 9th N-type metal-oxide-semiconductor are connect with VBP,
The grid end of the 9th N-type metal-oxide-semiconductor is connect with bias voltage VBN1；
The drain terminal of 5th p-type metal-oxide-semiconductor, the 5th p-type metal-oxide-semiconductor is connect with the drain terminal of the 8th N-type metal-oxide-semiconductor, the 5th P
The source of type metal-oxide-semiconductor is connect with supply voltage VDD, the drain terminal of the 5th p-type metal-oxide-semiconductor and the grid end of the 5th p-type metal-oxide-semiconductor
Connection, the grid end of the 5th p-type metal-oxide-semiconductor are connect with bias voltage VBP1；
The source of 7th p-type metal-oxide-semiconductor, the 7th p-type metal-oxide-semiconductor is connect with supply voltage VDD, the grid of the 7th p-type metal-oxide-semiconductor
End is connect with VBP；
The source of 6th p-type metal-oxide-semiconductor, the 6th p-type metal-oxide-semiconductor is connect with the drain terminal of the 7th p-type metal-oxide-semiconductor, the 6th P
The grid end of type metal-oxide-semiconductor is connect with VBP, and the drain terminal of the 6th p-type metal-oxide-semiconductor is connect with bias voltage VBP；
The source of 8th p-type metal-oxide-semiconductor, the 8th p-type metal-oxide-semiconductor is connect with VDD, the grid end and biasing of the 8th p-type metal-oxide-semiconductor
Voltage VBP1 connection, the drain terminal of the 8th p-type metal-oxide-semiconductor are connect with bias voltage VBN；
The drain terminal of 12nd N-type metal-oxide-semiconductor, the 12nd N-type metal-oxide-semiconductor is connect with bias voltage VBN, the 12nd N-type MOS
The grid end of pipe is connect with bias voltage VBN；
The drain terminal of 11st N-type metal-oxide-semiconductor, the 11st N-type metal-oxide-semiconductor is connect with the source of the 12nd N-type metal-oxide-semiconductor, institute
The grid end for stating the 11st N-type metal-oxide-semiconductor is connect with bias voltage VBN, the source ground connection of the 11st N-type metal-oxide-semiconductor.
5. low pressure difference linear voltage regulator system according to claim 4, which is characterized in that the error amplifier includes:
The grid end of 19th N-type metal-oxide-semiconductor, the 19th N-type metal-oxide-semiconductor is connect with bias voltage VBN1, the 19th N-type
The source of metal-oxide-semiconductor is grounded；
First N-type metal-oxide-semiconductor, the grid end and V of the first N-type metal-oxide-semiconductorOUTConnection, the source of the first N-type metal-oxide-semiconductor with it is described
The drain terminal of 19th N-type metal-oxide-semiconductor connects；
Second N-type metal-oxide-semiconductor, the grid end and V of the second N-type metal-oxide-semiconductorREFConnection, the source of the second N-type metal-oxide-semiconductor with it is described
The drain terminal of 19th N-type metal-oxide-semiconductor connects；
The source of first p-type metal-oxide-semiconductor, the first p-type metal-oxide-semiconductor is connect with VDD, the drain terminal of the first p-type metal-oxide-semiconductor with it is described
The drain terminal of metal-oxide-semiconductor MN1 connects, and the grid end of the first p-type metal-oxide-semiconductor is connect with bias voltage VBP1；
The source of second p-type metal-oxide-semiconductor, the second p-type metal-oxide-semiconductor is connect with VDD, the drain terminal of the second p-type metal-oxide-semiconductor with it is described
The drain terminal of second N-type metal-oxide-semiconductor connects, and the grid end of the second p-type metal-oxide-semiconductor is connect with bias voltage VBP1；
Third p-type metal-oxide-semiconductor, the source of the third p-type metal-oxide-semiconductor are connect with the drain terminal of the first p-type metal-oxide-semiconductor, the 3rd P
The grid end of type metal-oxide-semiconductor is connect with bias voltage VBP；
The source of 4th p-type metal-oxide-semiconductor, the 4th p-type metal-oxide-semiconductor is connect with the drain terminal of the second p-type metal-oxide-semiconductor, the 4th P
The grid end of type metal-oxide-semiconductor is connect with bias voltage VBP；
The drain terminal of 5th N-type metal-oxide-semiconductor, the 5th N-type metal-oxide-semiconductor is connect with the drain terminal of the third p-type metal-oxide-semiconductor, the 5th N
The grid end of type metal-oxide-semiconductor is connect with bias voltage VBN；
The drain terminal of 6th N-type metal-oxide-semiconductor, the 6th N-type metal-oxide-semiconductor is connect with the drain terminal of the 4th p-type metal-oxide-semiconductor, the 6th N
The grid end of type metal-oxide-semiconductor is connect with bias voltage VBN；
Third N-type metal-oxide-semiconductor, the drain terminal of the third N-type metal-oxide-semiconductor are connect with the source of the 5th N-type metal-oxide-semiconductor, the 3rd N
The grid end of type metal-oxide-semiconductor is connect with the drain terminal of the 5th N-type metal-oxide-semiconductor, the source ground connection of the third N-type metal-oxide-semiconductor；
The drain terminal of 4th N-type metal-oxide-semiconductor, the 4th N-type metal-oxide-semiconductor is connect with the source of the 6th N-type metal-oxide-semiconductor, the 4th N
The grid end of type metal-oxide-semiconductor is connect with the drain terminal of the 5th N-type metal-oxide-semiconductor, the source ground connection of the 4th N-type metal-oxide-semiconductor.
6. low pressure difference linear voltage regulator system according to claim 1, which is characterized in that the transfer efficiency enhances circuit
Include:
The source of induction tube, the induction tube is connect with VDD, and the drain terminal of the induction tube is grounded by resistor R, the induction
Pipe grid end and driving voltage VPGConnection；
15th p-type metal-oxide-semiconductor, the source and V of the 15th p-type metal-oxide-semiconductorOUTConnection, the grid end of the 15th p-type metal-oxide-semiconductor
It is connect with the drain terminal of the induction tube, the drain terminal ground connection of the 15th p-type metal-oxide-semiconductor；
Muller compensation capacitor, one end of the Muller compensation capacitor and driving voltage VPGConnection, the other end and zero-regulator resistor
Device connection；
Zero-regulator resistor device, one end of the zero-regulator resistor device are connect with the other end of the Muller compensation capacitor, the zeroing
The other end and V of resistorOUTConnection；
Third capacitor, one end of the third capacitor are connect with the source of the 15th p-type metal-oxide-semiconductor, the third electricity
The other end of container is grounded；
Converting resistor, one end of the converting resistor are connect with the grid end of the 15th p-type metal-oxide-semiconductor, the conversion electricity
Hinder the other end ground connection of device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920191569.9U CN209265312U (en) | 2019-02-12 | 2019-02-12 | Low pressure difference linear voltage regulator system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920191569.9U CN209265312U (en) | 2019-02-12 | 2019-02-12 | Low pressure difference linear voltage regulator system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209265312U true CN209265312U (en) | 2019-08-16 |
Family
ID=67585280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920191569.9U Active CN209265312U (en) | 2019-02-12 | 2019-02-12 | Low pressure difference linear voltage regulator system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209265312U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109710017A (en) * | 2019-02-12 | 2019-05-03 | 麦堆微电子技术（上海）有限公司 | A kind of low pressure difference linear voltage regulator system |
| CN112527044A (en) * | 2020-12-02 | 2021-03-19 | 上海维安半导体有限公司 | Transient response enhancement circuit of no-capacitor LDO |
-
2019
- 2019-02-12 CN CN201920191569.9U patent/CN209265312U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109710017A (en) * | 2019-02-12 | 2019-05-03 | 麦堆微电子技术（上海）有限公司 | A kind of low pressure difference linear voltage regulator system |
| CN109710017B (en) * | 2019-02-12 | 2024-03-19 | 麦堆微电子技术（上海）有限公司 | Low-dropout linear voltage regulator system |
| CN112527044A (en) * | 2020-12-02 | 2021-03-19 | 上海维安半导体有限公司 | Transient response enhancement circuit of no-capacitor LDO |
| CN112527044B (en) * | 2020-12-02 | 2022-04-15 | 上海维安半导体有限公司 | Transient response enhancement circuit of no-capacitor LDO |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109710017A (en) | A kind of low pressure difference linear voltage regulator system | |
| CN104460802B (en) | The low pressure difference linear voltage regulator of one self-adaptive current multiple circuit and this circuit integrated | |
| CN102289243B (en) | Complementary metal oxide semiconductor (CMOS) band gap reference source | |
| CN108803761B (en) | LDO circuit that contains high-order temperature compensation | |
| CN109164861A (en) | A kind of low pressure difference linear voltage regulator of fast transient response | |
| CN104407662B (en) | A kind of underloading transient state strengthens the low pressure difference linear voltage regulator of circuit and this circuit integrated | |
| CN108803764B (en) | LDO circuit with fast transient response | |
| CN209265312U (en) | Low pressure difference linear voltage regulator system | |
| CN104460807B (en) | A kind of low pressure difference linear voltage regulator of integrated adaptive reference buffer | |
| CN102707757A (en) | Dynamic discharge circuit and LDO integrated with same | |
| CN102200791A (en) | Low dropout linear regulator structure | |
| CN107092295A (en) | A kind of high Slew Rate fast transient response LDO circuit | |
| CN111930173A (en) | LDO circuit with low quiescent current and quick response and SOC system | |
| CN101609345B (en) | Linear voltage regulator | |
| CN212989976U (en) | LDO circuit, LDO and SOC system | |
| CN219018536U (en) | Dual-power automatic switching circuit | |
| CN107463196B (en) | A kind of LDO circuit improving loop stability | |
| CN202586753U (en) | Inner power supply circuit for wind range power input | |
| CN210005947U (en) | linear constant current driving module circuit | |
| CN215117303U (en) | Voltage generating circuit | |
| CN210005943U (en) | reference voltage source with adjustable output voltage | |
| CN102710136A (en) | Internal power supply circuit for wide-range power input | |
| CN208298052U (en) | A kind of novel slew rate enhancing circuit, low pressure difference linear voltage regulator | |
| CN206877188U (en) | Low-power dissipation power supply power supply circuit | |
| CN112817358A (en) | Novel LDO circuit suitable for large capacity SIM card chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |