CN210005947U

CN210005947U - linear constant current driving module circuit

Info

Publication number: CN210005947U
Application number: CN201921280451.XU
Authority: CN
Inventors: 杨盘柱; 杨小兵; 王壮
Original assignee: Guizhou Chensi Electronics Technology Co Ltd
Current assignee: Guizhou Chensi Electronics Technology Co Ltd
Priority date: 2019-08-08
Filing date: 2019-08-08
Publication date: 2020-01-31
Anticipated expiration: 2029-08-08

Abstract

The utility model discloses an linear constant current drive module circuit, including error amplifier, sampling voltage circuit and low pressure multiple amplifier circuit, the error amplifier output links to each other with the sampling voltage circuit, and the sampling voltage circuit links to each other with low pressure multiple amplifier circuit input, and low pressure multiple amplifier circuit output links to each other with the error amplifier inverting terminal, and low pressure multiple amplifier input links to each other with the sampling resistance of sampling voltage circuit with feedback voltage output Vf, inserts error amplifier.

Description

linear constant current driving module circuit

Technical Field

The utility model relates to an linear constant current drive module circuit belongs to integrated power supply technical field.

Background

The portable electronic products play a crucial role in daily life, and no matter whether the portable electronic products are flat panels, mobile phones, palm computers or other portable electronic products powered by batteries, the portable electronic products have different functional modules, different modules in electronic products may need currents or voltages with different values, and the electronic products cannot normally work without stable currents or voltages.

The traditional linear constant current driving module circuit can be divided into a parallel type (see fig. 2) and a series type (see fig. 3) according to the structure, the parallel type linear constant current driving has the working principle that when the input voltage is increased, the current flowing through an LED is increased, the voltage drop on a sampling resistor is also increased, the feedback voltage enables the output of an error amplifier to be increased, the dynamic resistance of a power tube is reduced, namely the conduction current of the power tube is increased, the voltage drop on a current limiting resistor is increased, and the voltage drop on the LED is reduced, so that the output current of the LED is reduced, and the function of current constancy is realized.

Disclosure of Invention

The utility model aims to solve the technical problem that linear constant current driving module circuits are provided to solve the technical problem that the conversion efficiency of the linear constant current driving module circuit in the prior art is low due to the sampling resistance under the condition of large current.

The utility model adopts the technical scheme that linear constant current drive module circuit, including error amplifier, sampling voltage circuit and low pressure multiple amplifier circuit, the error amplifier output links to each other with sampling voltage circuit, and sampling voltage circuit links to each other with low pressure multiple amplifier circuit input, and low pressure multiple amplifier circuit output links to each other with error amplifier inverting terminal, and low pressure multiple amplifier input links to each other with sampling voltage circuit's sampling resistance with feedback voltage output Vf, inserts error amplifier.

Preferably, the error amplifier includes a resistor R0, a resistor R1, a capacitor C0, an enhancement NMOS MN0, an enhancement NMOS MN1, an enhancement NMOS MN2, an enhancement NMOS MN3, an enhancement NMOS MN4, an enhancement NMOS MN5, an enhancement PMOS MP0, an enhancement PMOS MP1, an enhancement PMOS MP2, an enhancement PMOS MP3, and an enhancement PMOS MP3, wherein a gate of the enhancement PMOS MP3 and a drain of the enhancement PMOS MP3 are connected to a source of the enhancement NMOS MN3, a drain of the enhancement PMOS MP3 is connected to a drain and a gate of the enhancement NMOS MN3, a gate of the enhancement NMOS 3 is connected to a drain of the enhancement PMOS MP3, a drain of the enhancement PMOS 3 is connected to a drain of the enhancement PMOS MP3 and a drain of the enhancement PMOS MP3, a drain of the enhancement NMOS 3 is connected to a gate Vref of the enhancement NMOS 3, and a drain of the enhancement NMOS 3 are connected to a drain of the enhancement NMOS 3, a drain of the enhancement NMOS 3 and a drain of the enhancement NMOS 3 are connected to a drain of the enhancement NMOS 3, the gate of an enhanced PMOS tube MP2 is respectively connected with the gate and the drain of an enhanced PMOS tube MP3, the gate of an enhanced PMOS tube MP9 and the gate of an enhanced PMOS tube MP8, the source is connected with a power supply VDD, the source of the enhanced PMOS tube MP3 is connected with the power supply VDD, the drain is connected with the drain of an enhanced NMOS tube MN3, the gate and the drain of an enhanced PMOS tube MP4 are connected with the gate of the enhanced PMOS tube MP5 and the drain of the enhanced NMOS tube MN4, the source of the MP4 is connected with the power supply VDD, the source of the enhanced PMOS tube MP5 is connected with the power supply VDD, the drain is connected with a resistor R0 and the gate of the enhanced NMOS tube MN5, the source of the enhanced NMOS tube MN0, the source of the enhanced NMOS tube MN1 and the source of the enhanced NMOS tube MN2 are grounded, the drain of the enhanced NMOS tube MN2 is respectively connected with a capacitor C0, a drain of the NL tube MP9 and the drain of the enhanced PMOS tube MP3, and the drain of the NMOS tube MN4 are respectively connected with the drain of the NMOS tube MN4, The resistor R0 is connected with the drain of the enhanced NMOS transistor MN5, the enhanced NMOS transistor MN4 is connected with the source of the enhanced NMOS transistor MN5, the resistor R1 is connected with the capacitor C0, and the source of the enhanced PMOS transistor MP9 is connected with the power supply VDD.

Preferably, the sampling voltage circuit comprises a sampling resistor Rsen and an NLDMOS tube, the end of the sampling resistor Rsen is grounded, the other end is connected with the gate of the enhancement PMOS tube MP6 and the source of the NLDMOS, the drain of the NLDMOS is connected with the load, and the load is connected with the external input voltage.

Preferably, the low-voltage multiple amplifier comprises an enhanced PMOS transistor MP8, an enhanced PMOS transistor MP6, an enhanced PMOS transistor MP7, an enhanced NMOS transistor MN6, an enhanced NMOS transistor MN7, a resistor R2, and a resistor R3, wherein a gate of the enhanced PMOS transistor MP8 is connected to a gate of the enhanced PMOS transistor MP9, a source is connected to a power supply VDD, a drain is connected to a source of the enhanced PMOS transistor MP6 and a source of the enhanced PMOS transistor MP7, a gate of the enhanced PMOS transistor MP7 is connected to a resistor R2, a resistor R2 and a resistor R3 are connected in series, another end of the enhanced PMOS transistor MP7 is grounded, a drain of the enhanced PMOS transistor MP7 is connected to a drain and a gate of the enhanced NMOS transistor MN7, a gate of the enhanced NMOS transistor MN6 is connected to an intermediate node of the resistor R367 and the resistor R3, a gate of the enhanced PMOS transistor MP6 is connected to a source of the sampling Rsen and a drain of the enhanced NMOS transistor MN6, and a drain of the enhanced NMOS transistor MN6 are connected to a drain of the enhanced NMOS transistor MN6 and a drain of the enhanced NMOS 6.

Compared with the prior art, the utility model discloses a linear constant current drive module adopts the voltage proportional amplifier of low pressure modules on the basis of tandem type structure, sampling resistance has been reduced, can reach the method of lifting efficiency, although it can make the static consumption increase of chip to have increased proportional amplifier, nevertheless for the reduction of sampling resistance consumed power all, the static consumption of increase seems very little, concrete process is with sampling voltage access low pressure multiple amplifier input, output access error amplifier, sampling pressure drop Vf compares with the benchmark voltage again after passing through low pressure multiple amplifiers (amplification multiple is A), sampling pressure drop just can reduce A times like this, Vf = I Rs, under the unchangeable condition of electric current, Vf reduces A times, event Rs also reduces A times is resistance/A, sampling resistance reduces like this, the power of consumption also diminishes, whole conversion power has just increased, the linear constant current module of having solved prior art changes the technical problem that efficiency is low because sampling resistance under the heavy current condition.

Drawings

FIG. 1 is a schematic structural view of the present invention;

fig. 2 is a schematic structural diagram (parallel type) of a linear constant current driving module in the prior art.

Fig. 3 is a schematic diagram (series type) of a prior art low dropout linear regulator.

Detailed Description

The present invention will be described with reference to the drawings and the specific embodiments in .

In the embodiment, as shown in fig. 1, linear constant current driving module circuits include an error amplifier, a sampling voltage circuit and a low-voltage multiple amplifier circuit, wherein an output end of the error amplifier is connected with the sampling voltage circuit, the sampling voltage circuit is connected with an input end of the low-voltage multiple amplifier circuit, an output end of the low-voltage multiple amplifier circuit is connected with an inverting end of the error amplifier, and an input end of the low-voltage multiple amplifier circuit is connected with a sampling resistor of the sampling voltage circuit to output Vf feedback voltage to the error amplifier.

Preferably, the error amplifier includes a resistor R0, a resistor R1, a capacitor C0, an enhancement NMOS MN0, an enhancement NMOS MN1, an enhancement NMOS MN2, an enhancement NMOS MN3, an enhancement NMOS MN4, an enhancement NMOS MN5, an enhancement PMOS MP0, an enhancement PMOS MP1, an enhancement PMOS MP2, an enhancement PMOS MP3, and an enhancement PMOS MP3, wherein a gate of the enhancement PMOS MP3 is connected to a drain of the enhancement PMOS MP3 and a source of the enhancement PMOS MP3, a drain of the enhancement PMOS MP3 is connected to a drain and a gate of the enhancement NMOS MN3, a gate of the enhancement NMOS 3 is connected to a drain of the enhancement PMOS MP3, a drain of the enhancement PMOS 3 is connected to a drain of the enhancement PMOS MP3 and a drain of the enhancement PMOS 3, a drain of the enhancement NMOS 3 is connected to a gate voltage Vref, and a gate of the enhancement NMOS MN3 are connected to a drain of the enhancement NMOS 3, a drain of the enhancement NMOS 3 and a drain of the enhancement NMOS 3, the gate of an enhanced PMOS tube MP2 is respectively connected with the gate and the drain of an enhanced PMOS tube MP3, the gate of an enhanced PMOS tube MP9 and the gate of an enhanced PMOS tube MP8, the source is connected with a power supply VDD, the source of the enhanced PMOS tube MP3 is connected with the power supply VDD, the drain is connected with the drain of an enhanced NMOS tube MN3, the gate and the drain of an enhanced PMOS tube MP4 are connected with the gate of the enhanced PMOS tube MP5 and the drain of the enhanced NMOS tube MN4, the source of the MP4 is connected with the power supply VDD, the source of the enhanced PMOS tube MP5 is connected with the power supply VDD, the drain is connected with a resistor R0 and the gate of the enhanced NMOS tube MN5, the source of the enhanced NMOS tube MN0, the source of the enhanced NMOS tube MN1 and the source of the enhanced NMOS tube MN2 are grounded, the drain of the enhanced NMOS tube MN2 is respectively connected with a capacitor C0, a drain of the NL tube MP9 and the drain of the enhanced PMOS tube MP3, and the drain of the NMOS tube MN4 are respectively connected with the drain of the NMOS tube MN4, The resistor R0 is connected with the drain of the enhanced NMOS transistor MN5, the enhanced NMOS transistor MN4 is connected with the source of the enhanced NMOS transistor MN5, the resistor R1 is connected with the capacitor C0, and the source of the enhanced PMOS transistor MP9 is connected with the power supply VDD.

The enhanced PMOS tube MP5, the enhanced PMOS tube MP4, the enhanced NMOS tube MN5, the enhanced NMOS tube and the resistor R0 form a bias circuit of the error amplifier to provide bias current for the error amplifier; the enhanced PMOS tube MP3 and the enhanced PMOS tube MP2 form a current mirror, and provide the current generated by the bias circuit for the input of the error amplifier; the enhanced PMOS transistor MP0 and the enhanced PMOS transistor MP1 are input transistors of the error amplifier, the PMOS transistor has the advantage of low noise ratio, and the enhanced PMOS transistor MP9 and the enhanced NMOS transistor MN2 form a common source amplifier as a second stage of the operational amplifier.

Preferably, the sampling voltage circuit comprises a sampling resistor Rsen and an NLDMOS tube, wherein the end of the sampling resistor Rsen is grounded, the other end is connected with a grid of an enhanced PMOS tube MP6 and a source of the NLDMOS, a drain of the NLDMOS is connected with a load, the load is connected with an external input voltage, and the load (N1) is connected with the external input voltage.

The low-voltage multiple amplifier adopts a resistor R2 and a resistor R3 to form an in-phase proportional amplifier with an operational amplifier, the amplification factor A1 is 10 times, and an enhanced PMOS tube MP8 provides bias current for the low-voltage multiple amplifier; the grid signal Vf of the enhancement type PMOS transistor MP6 is the voltage on the sampling resistor Rsen, which is amplified by the low voltage multiple amplifier and input to the error amplifier, and compared with the reference voltage Vref set in the circuit to control the NLDMOS, so that the load current is in the stable range.

The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and all should be covered within the protection scope of the present invention, therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

The linear constant current driving module circuit is characterized by comprising an error amplifier, a sampling voltage circuit and a low-voltage multiple amplifier circuit, wherein the output end of the error amplifier is connected with the sampling voltage circuit, the sampling voltage circuit is connected with the input end of the low-voltage multiple amplifier circuit, the output end of the low-voltage multiple amplifier circuit is connected with the inverting end of the error amplifier, and the input end of the low-voltage multiple amplifier is connected with a sampling resistor of the sampling voltage circuit to output a feedback voltage Vf to the error amplifier.
2. The linear constant-current drive module circuit as claimed in claim 1, wherein the error amplifier comprises a resistor R, a capacitor C, an enhanced NMOS transistor MN, an enhanced PMOS transistor MP, and an enhanced PMOS transistor MP, wherein a gate of the enhanced PMOS transistor MP is connected to the feedback voltage Vf, a drain of the enhanced PMOS transistor MP is connected to a drain of the enhanced NMOS transistor MN, a gate of the enhanced PMOS transistor MP is connected to a source of the enhanced PMOS transistor MP, a drain of the enhanced PMOS transistor MP is connected to a drain of the enhanced PMOS transistor MP and a source of the enhanced PMOS transistor MP, a gate of the enhanced PMOS is connected to a reference voltage Vref, a drain of the enhanced NMOS transistor MN, a gate of the resistor R is connected to a gate of the enhanced PMOS transistor MP, a drain of the enhanced NMOS transistor MP is connected to a drain of the PMOS, a gate of the enhanced PMOS is connected to a drain of the PMOS, a drain of the NMOS transistor MP is connected to a drain of the enhanced PMOS, a gate of the enhanced PMOS is connected to a drain of the NMOS, a drain of the NMOS transistor MN, a drain of the NMOS is connected to a drain of the NMOS, a drain of the NMOS is connected to a drain of the PMOS is connected to a drain of the NMOS, a drain of the NMOS is connected to a drain of the NMOS, a drain of the PMOS is connected to a drain of the NMOS, a drain of the NMOS is connected to.
3. The linear constant current driving module circuit as claimed in claim 2, wherein the sampling voltage circuit includes a sampling resistor Rsen and an NLDMOS transistor, the end of the sampling resistor Rsen is grounded, the other end is connected to the gate of an enhancement PMOS transistor MP6 and the source of the NLDMOS transistor, the drain of the NLDMOS transistor is connected to the load, and the load is connected to the external input voltage.
4. The linear constant current driving module circuit according to claim 3, wherein the low voltage multiple amplifier includes an enhanced PMOS transistor MP8, an enhanced PMOS transistor MP6, an enhanced PMOS transistor MP7, an enhanced NMOS transistor MN6, an enhanced NMOS transistor MN7, a resistor R2 and a resistor R3, a gate of the enhanced PMOS transistor MP8 is connected to a gate of the enhanced PMOS transistor MP9, a source is connected to a power VDD, a drain is connected to a source of the enhanced PMOS transistor MP6 and a source of the enhanced PMOS transistor MP7, a gate of the enhanced PMOS transistor MP7 is connected to a resistor R2, a resistor R2 and a resistor R3 are connected in series, an additional end of the series is grounded, a drain of the enhanced PMOS transistor MP7 is connected to a drain of the enhanced NMOS transistor MN7 and a drain of the enhanced NMOS transistor MP7, a gate of the NMOS transistor MN7 is connected to an intermediate node of the enhanced PMOS 7 and a drain of the enhanced PMOS transistor MN7, a gate of the enhanced PMOS transistor MP7 is connected to a gate of the enhanced PMOS transistor MN7 and a drain of the enhanced NMOS transistor MN7, and a drain of the enhanced PMOS transistor MN7 are connected to a drain of the enhanced PMOS 7 and a drain of the enhanced PMOS transistor MN 7.