CN105652945B - Low dropout regulator - Google Patents
Low dropout regulator Download PDFInfo
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- CN105652945B CN105652945B CN201610204421.5A CN201610204421A CN105652945B CN 105652945 B CN105652945 B CN 105652945B CN 201610204421 A CN201610204421 A CN 201610204421A CN 105652945 B CN105652945 B CN 105652945B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention belongs to the technical field of power management and particularly relates to a low dropout regulator. Compared with an existing low dropout regulator, the low dropout regulator has the advantages that by additional arrangement of an FNRC (feed-forward noise rejection circuit) which acquires ripple waves of high-frequency input voltage Vin and overlaps to output of an EA (error amplifier) through a summing circuit to control a regulation tube, the input voltage ripple waves under a high frequency is effectively eliminated, and a system PSRR (power supply rejection ratio) under a high frequency is greatly increased.
Description
Technical field
The invention belongs to technical field of power management, and in particular to a kind of low pressure difference linear voltage regulator (Low Dropout
Regulator, LDO).
Background technology
Low pressure difference linear voltage regulator has that low cost, output noise are little, circuit structure is simple, chip occupying area is little and low
The advantages of power consumption, it has also become the class Important Circuit in power management chip.
The essence of LDO be using band-gap reference produce burning voltage and negative feedback control loop obtain one substantially not with
The output voltage of environmental change.Existing typical LDO is as shown in figure 1, specifically include：Adjustment pipe MP1, error amplifier EA,
Resistance-feedback network, load resistance RL, load capacitance CL.Its basic functional principle is：Resistance-feedback network produces feedback voltage,
Error small-signal between feedback voltage and reference voltage is amplified by error amplifier, then adjusted pipe amplifies output, by
This forms negative feedback, it is ensured that output voltage is stablized, as error amplifier amplifies reference voltage V ref clamped to error
The junction point of the R1 and R2 of device, so output voltage has Vout=(1+R1/R2) Vref.
In current thumping majority application, frequently with the framework that LDO is used in series with DC-DC converter, it is both LDO's
Power supply is provided by the output voltage of preceding stage DC-DC changer.The operating frequency of most of dc-dcs exists at present at this stage
Between 100KHz～10MHz, when being powered to LDO using the voltage, a 100KHz on the input voltage of LDO, is also had
Ripple in～10MHz frequency ranges, in order to suppress LDO output end voltages to be affected by input power ripple, usually requires that LDO
There is good power supply ripple rejection ability ratio in 100KHz～10MHz frequency ranges, PSRR (Power is that is to say
Supply Rejection Ratio, PSRR), the less explanation LDO output voltages of the value are affected less by power supply ripple.Although
Loop gain by lifting LDO can improve PSRR at low frequency, make as loop gain declines with frequency in high frequency
It is no longer applicable that this scheme is obtained high frequency PSRR is lifted.Document " C.Zhan and W.H.Ki, " Output-capacitor-
free adaptively biased low-dropout regulator for system-on-chips,”IEEE
Using certainly in Trans.Circuits Syst.I, Reg.Papers, vol.57, no.5, pp.1017-1028, May.2010. "
The mode of biasing is adapted to realizing high PSRR, but design poor efficiency under heavy loads limits the use of the structure.
The content of the invention
The invention aims to solve the problems referred to above that existing low pressure difference linear voltage regulator is present, it is proposed that a kind of
Low pressure difference linearity with feed-forward noise suppression circuit (Feedforward Noise Rejection Circuit, FNRC) is steady
Depressor, it is intended to lift LDO high frequency PSRR performances.
The technical scheme is that：A kind of low pressure difference linear voltage regulator, including the amplification of feed-forward noise suppression circuit, error
Device, summing circuit, adjustment pipe MP, first resistor Rf1, second resistance Rf2 and the first electric capacity CF；
The error amplifier is by the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube
MN4, the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5,
Six PMOSs MP6,3rd resistor R1, the second electric capacity C1, the first current source I1, the second current source I2 and the 3rd current source I3 structures
Into；Wherein, the input termination power of the input of the second current source and the 3rd current source I3；The source electrode of the first PMOS MP1 connects
The outfan of the 3rd current source I3, the grid of the first PMOS MP1 connect external reference voltages Vref, the leakage of the first PMOS MP1
Pole is grounded；The source electrode of the second PMOS MP2 connects the outfan of the second current source I2, the reversed feed of grid of the second PMOS MP2
Pressure, the grounded drain of the second PMOS MP2；The source electrode of the 3rd PMOS MP3 connects power supply, and its grid connects the 4th PMOS MP4
Drain electrode；The source electrode of the 4th PMOS MP4 connects power supply, its grid and drain interconnection；The drain and gate of the first NMOS tube MN1 is mutual
Even, its drain electrode connects the drain electrode of the 3rd PMOS MP3, the source ground of the first NMOS tube MN1；The drain electrode of the 3rd NMOS tube MN3 connects
The drain electrode of the 4th PMOS MP4, the grid of the 3rd NMOS tube MN3 connect the outfan of the second current source I2, the 3rd NMOS tube MN3
Source electrode connects the input of the first current source I1；The source electrode of the 5th PMOS MP5 connects power supply, its grid and drain interconnection；4th
The drain electrode of NMOS tube MN4 connects the drain electrode of the 5th PMOS MP5, and the grid of the 4th NMOS tube MN4 connects the output of the 3rd current source I3
End, the source electrode of the 4th NMOS tube MN4 connect the input of the first current source I1；The output head grounding of the first current source I1；6th
The source electrode of PMOS MP6 connects power supply, and its grid connects the drain electrode of the 5th PMOS MP5；The drain electrode of the second NMOS tube MN2 connects the 6th
The drain electrode of PMOS MP6, the grid of the second NMOS tube MN2 connect the drain electrode of the 3rd PMOS MP3, the source electrode of the second NMOS tube MN2
Ground connection；The junction point of the 6th PMOS MP6 and the second NMOS tube MN2 passes sequentially through 3rd resistor R1 and the second electric capacity C1 is followed by
Ground；
The summing circuit is by the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the 5th NMOS tube MN5
Constitute with the 4th resistance R3；Wherein, the source electrode of the 7th PMOS MP7 is followed by power supply, the 7th PMOS MP7 by the 4th resistance R3
Grid and drain interconnection；The source electrode of the 8th PMOS MP8 connects power supply, and its grid connects the drain electrode of the 9th PMOS MP9；9th
The source electrode of PMOS MP9 connects power supply, its grid and drain interconnection；The drain electrode of the 5th NMOS tube MN5 connects the leakage of the 7th PMOS MP7
Pole and the drain electrode of the 8th PMOS MP8；The grid of the 5th NMOS tube MN5 connects the drain electrode of the 6th PMOS MP6 and the second NMOS tube MN2
The junction point of drain electrode, the source ground of the 5th NMOS tube MN5；
The feed-forward noise suppression circuit by the tenth PMOS MP10, the 11st PMOS MP11, the 6th NMOS tube MN6,
7th NMOS tube MN7, the 8th NMOS tube MN8, the 5th resistance R2, the 6th resistance R4, the 3rd electric capacity C2, the 4th electric capacity C4, the 4th
Current source I4 and the 5th current source I5 is constituted；Wherein, the input termination power of the 4th current source I4 and the 5th current source I5；3rd
The outfan of one the 4th current source I4 of termination of electric capacity C2, the outfan of the 5th current source I5 of another termination of the 3rd electric capacity C2；
5th resistance R2 is in parallel with the 3rd electric capacity C2；The source electrode of the tenth PMOS MP10 connects the outfan of the 4th current source I4, and the tenth
The grid of PMOS MP10 meets external reference voltages Vref；The drain electrode of the 7th NMOS tube MN7 connects the drain electrode of the tenth PMOS MP10,
The grid and drain interconnection of the 7th NMOS tube MN7, the source ground of the 7th NMOS tube MN7；The drain electrode of the 6th NMOS tube MN6 connects
The drain electrode of nine PMOSs MP9, the grid of the 6th NMOS tube MN6 connect the drain electrode of the tenth PMOS MP10, the source of the 6th NMOS tube MN6
Pole is grounded；The source electrode of the 11st PMOS MP11 connects the outfan of the 5th current source I5, and the grid of the 11st PMOS MP11 leads to
Cross the 6th resistance R4 and be followed by external reference voltages Vref；11st PMOS MP11 grid is passed through with the junction point of the 6th resistance R4
4th electric capacity C4 is followed by power supply；8th NMOS tube MN8 misses the drain electrode for connecing the 11st PMOS MP11, the 8th NMOS tube MN8
Grid and drain interconnection, the source ground of the 8th NMOS tube MN8；
The source electrode of adjustment pipe MP connects power supply, and its grid connects the drain electrode of the 7th PMOS MP7, and the drain electrode for adjusting pipe MP is led to successively
It is grounded after crossing first resistor Rf1 and second resistance Rf2, the first electric capacity CF is in parallel with first resistor Rf1；Adjustment pipe MP drain electrodes and the
The junction point of one resistance Rf1 and the first electric capacity CF is used as outfan.
Beneficial effects of the present invention are, compared with existing LDO, add feed-forward noise and eliminate circuit, and FNRC circuits will
The ripple of the input voltage vin of high frequency is gathered and is superimposed upon control adjustment in the output of error amplifier (EA) by summing circuit
Input voltage ripple under high frequency is effectively eliminated so that system PSRR in high frequency is highly improved by pipe.
Description of the drawings
The topology diagram of the existing LDO circuits of Fig. 1；
Fig. 2 LDO circuit topology diagrams for being integrated with FNRC circuits proposed by the present invention；
The electrical block diagram of the LDO during Fig. 3 is of the invention；
LDO error amplifiers PSRR analysis small-signal figures during Fig. 4 is of the invention；
LDO during Fig. 5 is of the invention is in unequally loaded open-loop gain and phase margin analogous diagram；
PSRR performance simulation comparison diagrams of the Fig. 6 with the FNRC and LDO without FNRC；
LDO during Fig. 7 is of the invention PSRR performance simulation comparison diagrams under different loads.
Specific embodiment
Below in conjunction with the accompanying drawings, describe technical scheme in detail：
High power supply rejection performance low pressure difference linear voltage regulator with feed-forward noise suppression circuit proposed by the present invention is
System topology diagram is made up of 4 parts as shown in Figure 2, feed-forward noise suppression circuit (FNRC), summing circuit (Summing), mistake
Difference amplifier (EA) and LDO power adjustment output stage；FNRC modules are made up of high pass filter and trsanscondutance amplifier, high pass
The capacitance terminal of wave filter is connected with Vin, and resistance terminal is connected with external reference voltage V ref, the forward direction of outfan and trsanscondutance amplifier
Input is connected, and the negative input for being cross over amplifier is connected with Vref, and summation module is delivered in the output of FNRC modules；EA is just
To input termination reference voltage V ref, summation module is delivered in the output of EA, and summation module will be the output of FNRC modules defeated with EA
The grid end of adjustment pipe is arrived in output after going out to carry out summation operation, and the source for adjusting pipe connects external input voltage Vin, and drain terminal is used as LDO
Output voltage Vout, first resistor is connected in parallel with the first electric capacity, a termination output voltage Vout other ends and second resistance
It is connected, the other end ground connection of second resistance, negative input of first and second ohmic connection points as EA.
Identify such as in figure, if input voltage vin has ripple information vin (s) (such as figure acceptance of the bid in invention design system
The spike information of knowledge) just detected by FNRC beyond the forbidden band of wave filter, asking after being modulated by trsanscondutance amplifier
It is overlapped with the output signal in circuit with error amplifier, ripple information vin can be caused by reasonable arrange parameter
S () is delivered to the grid of adjustment pipe MP, and then reached the purpose of design for lifting LDO system high-frequency PSRR characteristics.
FNRC and summing circuit are the key points of LDO systems of the present invention, and as shown in Fig. 3 circuit full figures, FNRC includes
PMOS MP10, MP11 and NMOS tube MN6, MN7, MN8 and resistance R2, R4 and electric capacity C2, C4；Wherein MP10 and MP11 are
The input of FNRC meets external reference voltages Vref to pipe, the grid of MP10, and the grid of MP11 connects to be filtered by the high pass that C4 and R4 are constituted
The outfan of ripple device is the centre of C4 and R4, the positive termination input voltage vin of C4, another termination external reference voltages of R4
The source of Vref, MP10 and MP11 meets NMOS tube MN8 that the drain terminal of bias current I4 and I5, MP11 connects grid leak short circuit, MN8 respectively
Source ground connection, the drain terminal of MP10 connects the grid end and drain terminal of MN7, and the grid end of MN6 is connected with the grid end of MN7, the source of MN6 and MN7
End is grounded, and MN6 and MN7 forms current mirror annexation, and the drain terminal of MN6 is exported as the bias current modulation of FNRC modules,
Resistance R2 and electric capacity C2 are connected in parallel between MP10 and the source of MP11, and the positive pole of C2 connects the source of MP11.Summing circuit includes,
PMOS MP7, MP8, MP9 and NMOS tube MN5 and resistance R3；MP9 grid leaks short circuit the bias current modulation in FNRC modules
Output, i.e. the drain terminal of MN6, the grid end of MP8 connect the source of the grid end of MP9, MP8 and MP9 and meet input voltage vin, MP8 and MP9
Form current mirror type of attachment, the source of another termination MP7 of the termination input voltage vins of resistance R3 mono-, MP7 grid leaks short circuit and MP8
Drain terminal connect, the grid end of MN5 connects the output end vo of error amplifier (EA), EA, MN5 sources ground connection, MN5 drain terminals and above-mentioned
The grid end drain terminal of the drain terminal and MP7 of MP8 is connected together as the output of summing circuit.
The setting of FNRC frequency filterings point is the key for lifting PSRR performances, and the frequency is arranged by the C4 in circuit and R4,
Gained ripple passband be：
(1/2πR4C4,∞)
The PSRR characteristics that the rational value for arranging C4 and R4 can just be obtained, on the other hand as C4 and R4 are in piece
Upper integrated, too small frequency filtering point certainly will cause the superfluous big of chip area, between chip area and excellent PSRR characteristics
There is a tradeoff design, be known that PSRR is determined by the loop gain of LDO at low frequency, then exist by the PSRR characteristics of LDO
The bandwidth of the passband of high pass filter and LDO can be existed part in design process to overlap, then be considered by area, this overlaps
Can not be excessive, may be generally disposed between LDO loops dominant pole and bandwidth GBW.
When input voltage ripple information arranges frequency less than FNRC filter segments, the electric current for now being exported by FNRC is
Bias current is biased for Ib2 summing circuits, when input voltage ripple signal vin (s) is higher than the frequency, the ripple signal quilt
FNRC is detected, and the electric current of now FNRC outputs is modulated to：
R3 is set to much larger than 1/gm7 in design, in summing circuit, the ripple information is superimposed upon EA's by amplifying
In output, further control adjusts the grid of pipe MP, and the ripple that setting R3=R2 obtains being superimposed upon in EA outputs in design is：
That is high frequency ripple information vin (s) of input voltage vin is passed to the grid end of adjustment pipe MP, then adjust pipe MP's
Gate source voltage is：
|VGS_MP|=| VO_EA+vin(s)-(Vin+vin(s))|
=Vin-VO_EA
Ripple information is removed, the PSRR characteristics of lift system.
In whole circuit, error amplifier includes, NMOS tube MN1, MN2, MN3, MN4 and PMOS MP1, MP2, MP3, MP4,
MP5, MP6 and resistance R1 and electric capacity C1；Wherein PMOS MP1 and MP2 as EA source with input to pipe, the grid of MP1 connects outer
Portion's reference voltage V ref, the grid end of MP2 connect the drain terminal ground connection of feedback voltage Vfb, MP1 and MP2, and source meets bias current I2 respectively
And I3, while the source of MP1 and MP2 is separately input to grid of the second level to pipe MN4 and MN3 as the output that the first order is amplified
End, the source of MP1 connect the grid end of MN4, and the source of MP2 connects the source of the grid end of MN3, MN3 and MN4 and is connected tail current source I1,
The drain terminal of MN3 connects the grid end and drain terminal of MP4, and the grid end of MP3 is connected to form current mirror type of attachment, the leakage of MN4 with the grid end of MP4
The grid end and drain terminal of termination MP5, the grid end of the grid end and MP5 of MP6 are connected to form the type of attachment of current mirror, MP3, MP4, MP5,
The source of MP6 connects input voltage vin, and the drain terminal of MP3 connects the grid end and drain terminal of MN1, and the grid end of MN2 connects the grid end of MN1, MN1 and
MN2 sources are grounded, and MN1 and MN2 forms current mirror type of attachment, and the drain terminal connection of the drain terminal and MN2 of MP6 is amplified as error
The output end vo of device, EA, resistance R1 and electric capacity C1 are connected on Vo, as loop compensation between EA and GND.The power adjustment of LDO
Export and including adjustment pipe MP, first resistor Rf1, second resistance Rf2 and the first electric capacity CF；The output of summing circuit connects tune
The grid of homogeneous tube MP, used as gate control signal, the source of MP meets input power Vin, and the drain terminal of MP meets first resistor Rf1 and Rf2
Be connected in series to ground, and used as the voltage output end of LDO, the first electric capacity CF is in parallel with first resistor Rf1, first resistor Rf1 and the
As feedback voltage point Vfb between two resistance Rf2.
The design of error amplifier is the key of low frequency PSRR optimizations, in the present invention the PSRR of designed error amplifier
Analysis small-signal model is as shown in figure 4, two input is shorted to ground, it is assumed that diode come the MOS device for condensing mode is
The small resistor and current mirror of 1/gm is current source circuit.If all devices are matched, now iMN3=iMN4 and roP6=
roP3.Small-signal AC ripple vin (s) that Vin can then be obtained is transferred to the outfan such as following formula of EA in EA：
Derive from above-mentioned ac small signal and can draw, the AC ripple information of input voltage there will not be in EA
The outfan of EA.
Fig. 5 is the open-loop gain emulation in plug-in 4 μ F electric capacity, is produced at unit gain in output par, c R1 and C1 of EA
One zero point improves the lower phase margin information of heavy duty, and the GBW of system is 336kHz in maximum load 25mA as seen in Figure 5
Lower phase margin is more than 45 °；Fig. 6 is the PSRR performance simulation comparison diagrams with the FNRC and LDO without FNRC under 25mA, can
To find out that system PSRR performance is effectively improved 10dB in Mid Frequency by the LDO with FNRC, LDOPSRR is significantly improved
Performance；Fig. 7 is PSRR performance simulation comparison diagrams under different loads, and with the reduction of load current, PSRR performances are from two sides
Face is lifted, and one is that the DC current gain for adjusting pipe MP becomes more uncorrelated to Iload, and the two is active load in summing circuit
(R3+1/gmP7) change, in, under heavy duty, 1/gmP7 is much smaller than R3, and now summing circuit load essentially is fixed
Value, but when in very underloading, MP7 will be into cut-off region, and now 1/gmP7 can not be ignored, and result in system loop gain
Lifted, also just improve PSRR performances.
Claims (1)
1. a kind of low pressure difference linear voltage regulator, including feed-forward noise suppression circuit, error amplifier, summing circuit, adjustment pipe MP,
First resistor Rf1, second resistance Rf2 and the first electric capacity CF；
The error amplifier by the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4,
First PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th
PMOS MP6,3rd resistor R1, the second electric capacity C1, the first current source I1, the second current source I2 and the 3rd current source I3 are constituted；
Wherein, the input termination power of the input and the 3rd current source I3 of the second current source I2；The source electrode of the first PMOS MP1 connects
The outfan of three current source I3, the grid of the first PMOS MP1 connect external reference voltages Vref, the drain electrode of the first PMOS MP1
Ground connection；The source electrode of the second PMOS MP2 connects the outfan of the second current source I2, the reversed feedthrough voltage of grid of the second PMOS MP2,
The grounded drain of the second PMOS MP2；The source electrode of the 3rd PMOS MP3 connects power supply, and its grid connects the leakage of the 4th PMOS MP4
Pole；The source electrode of the 4th PMOS MP4 connects power supply, its grid and drain interconnection；The drain and gate interconnection of the first NMOS tube MN1,
Its drain electrode connects the drain electrode of the 3rd PMOS MP3, the source ground of the first NMOS tube MN1；The drain electrode of the 3rd NMOS tube MN3 connects the 4th
The drain electrode of PMOS MP4, the grid of the 3rd NMOS tube MN3 connect the outfan of the second current source I2, the source electrode of the 3rd NMOS tube MN3
Connect the input of the first current source I1；The source electrode of the 5th PMOS MP5 connects power supply, its grid and drain interconnection；4th NMOS tube
The drain electrode of MN4 connects the drain electrode of the 5th PMOS MP5, and the grid of the 4th NMOS tube MN4 connects the outfan of the 3rd current source I3, and the 4th
The source electrode of NMOS tube MN4 connects the input of the first current source I1；The output head grounding of the first current source I1；6th PMOS MP6
Source electrode connect power supply, its grid connects the drain electrode of the 5th PMOS MP5；The drain electrode of the second NMOS tube MN2 connects the 6th PMOS MP6
Drain electrode, the grid of the second NMOS tube MN2 connect the drain electrode of the 3rd PMOS MP3, the source ground of the second NMOS tube MN2；6th
The junction point of PMOS MP6 and the second NMOS tube MN2 is grounded after passing sequentially through 3rd resistor R1 and the second electric capacity C1；
The summing circuit is by the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the 5th NMOS tube MN5 and
Four resistance R3 are constituted；Wherein, the source electrode of the 7th PMOS MP7 is followed by power supply, the grid of the 7th PMOS MP7 by the 4th resistance R3
Pole and drain interconnection；The source electrode of the 8th PMOS MP8 connects power supply, and its grid connects the drain electrode of the 9th PMOS MP9；9th PMOS
The source electrode of MP9 connects power supply, its grid and drain interconnection；The drain electrode of the 5th NMOS tube MN5 connects the drain electrode of the 7th PMOS MP7 and
The drain electrode of eight PMOSs MP8；The grid of the 5th NMOS tube MN5 connects the drain electrode of the 6th PMOS MP6 with the drain electrode of the second NMOS tube MN2
Junction point, the source ground of the 5th NMOS tube MN5；
The feed-forward noise suppression circuit by the tenth PMOS MP10, the 11st PMOS MP11, the 6th NMOS tube MN6, the 7th
NMOS tube MN7, the 8th NMOS tube MN8, the 5th resistance R2, the 6th resistance R4, the 3rd electric capacity C2, the 4th electric capacity C4, the 4th electric current
Source I4 and the 5th current source I5 is constituted；Wherein, the input termination power of the 4th current source I4 and the 5th current source I5；3rd is electric
Hold the outfan of a 4th current source I4 of termination of C2, the outfan of the 5th current source I5 of another termination of the 3rd electric capacity C2；The
Five resistance R2 are in parallel with the 3rd electric capacity C2；The source electrode of the tenth PMOS MP10 meets the outfan of the 4th current source I4, the tenth PMOS
The grid of pipe MP10 meets external reference voltages Vref；The drain electrode of the 7th NMOS tube MN7 connects the drain electrode of the tenth PMOS MP10, and the 7th
The grid and drain interconnection of NMOS tube MN7, the source ground of the 7th NMOS tube MN7；The drain electrode of the 6th NMOS tube MN6 connects the 9th
The drain electrode of PMOS MP9, the grid of the 6th NMOS tube MN6 connect the drain electrode of the tenth PMOS MP10, the source electrode of the 6th NMOS tube MN6
Ground connection；The source electrode of the 11st PMOS MP11 connects the outfan of the 5th current source I5, and the grid of the 11st PMOS MP11 passes through
6th resistance R4 is followed by external reference voltages Vref；The junction point of the 11st PMOS MP11 grid and the 6th resistance R4 is by the
Four electric capacity C4 are followed by power supply；The drain electrode of the 8th NMOS tube MN8 connects the drain electrode of the 11st PMOS MP11, the 8th NMOS tube MN8
Grid and drain interconnection, the source ground of the 8th NMOS tube MN8；
The source electrode of adjustment pipe MP connects power supply, and its grid connects the drain electrode of the 7th PMOS MP7, and the drain electrode for adjusting pipe MP passes sequentially through the
It is grounded after one resistance Rf1 and second resistance Rf2, the first electric capacity CF is in parallel with first resistor Rf1；The MP drain electrodes of adjustment pipe are electric with first
The junction point of resistance Rf1 and the first electric capacity CF is used as outfan.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610204421.5A CN105652945B (en) | 2016-04-01 | 2016-04-01 | Low dropout regulator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610204421.5A CN105652945B (en) | 2016-04-01 | 2016-04-01 | Low dropout regulator |
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| CN105652945A CN105652945A (en) | 2016-06-08 |
| CN105652945B true CN105652945B (en) | 2017-05-03 |
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| CN201610204421.5A Expired - Fee Related CN105652945B (en) | 2016-04-01 | 2016-04-01 | Low dropout regulator |
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108227801A (en) * | 2016-12-10 | 2018-06-29 | 北京同方微电子有限公司 | A kind of low pressure difference linear voltage regulator of high PSRR |
| CN107544606B (en) * | 2017-10-17 | 2019-02-22 | 清华大学 | A kind of high PSRR low pressure difference linear voltage regulator |
| EP3709123A1 (en) * | 2019-03-12 | 2020-09-16 | ams AG | Voltage regulator, integrated circuit and method for voltage regulation |
| CN109960306B (en) * | 2019-04-19 | 2020-08-18 | 海光信息技术有限公司 | Low dropout linear regulator |
| CN110794910B (en) * | 2019-11-14 | 2021-08-13 | 芯原微电子(上海)股份有限公司 | Low dropout voltage regulator circuit and method thereof |
| CN111522383A (en) * | 2020-05-20 | 2020-08-11 | 上海维安半导体有限公司 | Dynamic bias current boosting method applied to ultra-low power LDO (low dropout regulator) |
| CN114217660B (en) * | 2021-12-15 | 2023-11-10 | 芯河半导体科技(无锡)有限公司 | LDO circuit system without external output capacitor |
| CN114253334B (en) * | 2021-12-21 | 2023-08-18 | 上海山景集成电路股份有限公司 | Linear voltage stabilizer |
| CN115173854B (en) * | 2022-09-06 | 2022-11-29 | 英彼森半导体(珠海)有限公司 | Self-adaptive MOS transistor threshold voltage reduction circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6541946B1 (en) * | 2002-03-19 | 2003-04-01 | Texas Instruments Incorporated | Low dropout voltage regulator with improved power supply rejection ratio |
| CN103019291B (en) * | 2012-12-21 | 2015-10-21 | 上海华虹宏力半导体制造有限公司 | Low differential voltage linear voltage stabilizer circuit |
| CN104391533A (en) * | 2014-11-12 | 2015-03-04 | 记忆科技(深圳)有限公司 | High-PSRR (power supply rejection ratio) LDO (low dropout regulator) circuit |
| CN204576331U (en) * | 2015-04-20 | 2015-08-19 | 无锡中星微电子有限公司 | Low difference voltage regulator |
| CN105183063A (en) * | 2015-09-23 | 2015-12-23 | 成都华微电子科技有限公司 | Low-dropout regulator with broadband high power supply rejection ratio |
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