CN215117303U - Voltage generating circuit - Google Patents
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- CN215117303U CN215117303U CN202121621636.XU CN202121621636U CN215117303U CN 215117303 U CN215117303 U CN 215117303U CN 202121621636 U CN202121621636 U CN 202121621636U CN 215117303 U CN215117303 U CN 215117303U
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Abstract
The utility model provides a voltage generating circuit, strengthen electric capacity including operational amplifier circuit, compensation network, driver stage and bleeder circuit and transient response, operational amplifier circuit's output and compensation network's input are connected, and compensation network's output is connected with driver stage and bleeder circuit's input, and driver stage and bleeder circuit's output passes through equivalent load resistance and equivalent load capacitance output voltage, transient response strengthen electric capacity respectively with operational amplifier circuit and driver stage and bleeder circuit connect. The utility model can be compatible with capacitor-free and capacitor-equipped applications, namely, the load capacitor is not restricted, and the capacitor-free application can be selected and used on occasions with less strict transient response requirements, thereby saving the cost; in the application occasion with strict transient response requirement, the capacitor can be externally hung; when a capacitor-free structure is used, a transient response strengthening circuit is designed and added, so that the transient response time in the capacitor-free application is prolonged; when no capacitor is applied, the faults generated in the starting process are reduced.
Description
Technical Field
The utility model relates to a power supply circuit technical field especially relates to a voltage generation circuit.
Background
The power supply is an indispensable component in electronic products, the power supply type used in circuit application is mainly divided into a low dropout linear voltage regulator (LDO) and a switch power supply, and the LDO circuit does not use an inductor with large area overhead and has the characteristics of small output ripple and the like, so that the LDO circuit is widely applied. The LDOs can be classified into capacitive LDOs and non-capacitive LDOs according to load capacitance, and the LDOs are characterized in that:
the capacitor LDO: the external capacitors are generally 1uF or more, the transient response is good, the starting fault is small, but the output needs to independently package PIN PINs, and the PCB level external capacitors are needed, so that the cost is increased;
no capacitance LDO: the external capacitor is not needed, a PIN PIN is not needed to be packaged, the internal part is directly connected, the cost is saved, the load capacitor is generally pF-nF grade, the transient response is poor, the design is not good, and the fault is easy to generate during starting.
Therefore, it is necessary to provide a voltage generating circuit with high compatibility and capable of adapting to a capacitor LDO and a capacitor-less LDO.
SUMMERY OF THE UTILITY MODEL
To the defect that exists among the prior art, the utility model aims to provide a voltage generating circuit, compatible strong can adapt to electric capacity LDO and do not have electric capacity LDO.
In order to achieve the above purpose, the utility model adopts the following specific technical scheme:
a voltage generation circuit comprises an operational amplifier circuit, a compensation network, a driving stage, a voltage division circuit and a transient response strengthening capacitor, wherein the output end of the operational amplifier circuit is connected with the input end of the compensation network, the output end of the compensation network is connected with the input ends of the driving stage and the voltage division circuit, the output ends of the driving stage and the voltage division circuit output voltage through an equivalent load resistor and an equivalent load capacitor, and the transient response strengthening capacitor is respectively connected with the operational amplifier circuit, the driving stage and the voltage division circuit.
Preferably, the operational amplifier circuit includes a current source IS, NMOS transistors NM1 to NM4, and PMOS transistors PM1 to PM4, the PMOS transistors PM1 and PM2 are input pair transistors, the current source IS connected to PM1 and PM2, the NM1 and NM3, the NM2 and NM4, and the PM3 and PM4 are mirror pair transistors.
Preferably, the ratio of width to length of the PMOS transistors PM1 to PM2 is 1:1, and the ratio of width to length of the NM1 to NM3, the ratio of width to length of the NM2 to NM4, and the ratio of width to length of the PM3 to PM4 are 1:1, 1: N, and 1: N, respectively.
Preferably, the compensation network comprises a resistor R0, a capacitor C0 and a capacitor C1, one end of the resistor R0 is connected with a common terminal of PM4 and NM4, the other end of the resistor R0 is connected with one end of a capacitor C0, the other end of the capacitor C0 is grounded, one end of the capacitor C1 is connected with a common terminal of PM4 and NM4, and the other end of the capacitor C1 is grounded.
Preferably, the driving stage and the voltage divider circuit include an NMOS transistor NM5, a resistor R1, and a resistor R2, a gate of the NMOS transistor NM5 is connected to the compensation network, a source of the NMOS transistor NM5 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the resistor R2, the other end of the resistor R2 is grounded, a common terminal of the resistor R1 and the resistor R2 is connected to one end of a transient response enhancement capacitor C3, and the other end of the transient response enhancement capacitor C3 is connected to a common terminal of the NM2 and the NM 4.
Preferably, the equivalent load capacitance is formed by a parasitic capacitance of an internal integrated circuit in a non-capacitive application.
Preferably, the CL of the capacitor-less LDO circuit has an equivalent capacitance of the order of nF.
Preferably, the equivalent load capacitor is composed of an external capacitor, a packaging capacitor and an internal circuit parasitic capacitor when a capacitor is applied.
Preferably, the CL of the capacitive LDO circuit has an equivalent capacitance of the order of μ F.
The beneficial effects of the utility model reside in that:
1. the capacitor-free and capacitor-containing application can be compatible, namely the load capacitor is not constrained, and the capacitor-free application can be selected on occasions with less strict transient response requirements, so that the cost is saved; in the application occasion with strict transient response requirement, the capacitor can be externally hung;
2. when a capacitor-free structure is used, a transient response strengthening circuit is designed and added, so that the transient response time in the capacitor-free application is prolonged;
3. when no capacitor is applied, the faults generated in the starting process are reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of a voltage generating circuit according to the present invention;
in the figure, 1-operational amplifier circuit, 2-compensation network, 3-driving stage and voltage divider circuit, and 4-transient response reinforced capacitor
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, other embodiments obtained by a person of ordinary skill in the art without creative work all belong to the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "vertical", "upper", "lower", "horizontal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
As shown in fig. 1, the utility model provides a voltage generation circuit, strengthen electric capacity 4 including operational amplifier circuit 1, compensation network 2, driver stage and bleeder circuit 3 and transient response, operational amplifier circuit's output with the input of compensation network is connected, the output of compensation network with driver stage and bleeder circuit's input is connected, driver stage and bleeder circuit's output passes through equivalent load resistance and equivalent load capacitance output voltage, transient response strengthen electric capacity respectively with operational amplifier circuit and driver stage and bleeder circuit connect.
Preferably, the operational amplifier circuit includes a current source IS, NMOS transistors NM1 to NM4, and PMOS transistors PM1 to PM4, the PMOS transistors PM1 and PM2 are input pair transistors, the current source IS connected to PM1 and PM2, the NM1 and NM3, the NM2 and NM4, and the PM3 and PM4 are mirror pair transistors. The width-length ratio of the PMOS tube PM1 to the PM2 is 1:1, and the width-length ratio of the NM1 to the NM3, the width-length ratio of the NM2 to the NM4, and the width-length ratio of the PM3 to the PM4 are 1:1, 1: N and 1: N respectively. VREF is the positive end of the operational amplifier and is connected with the output of a reference voltage source, VDIV is the reverse end of the operational amplifier and is connected with the voltage division output of R1 and R2, and the width-to-length ratio (W/L) is designed in the circuitPM4＝N*(W/L)PM3，(W/L)NM4＝N*(W/L)NM2And the current flowing through a PM4 source stage is N times of the current flowing through a PM3 source stage, so that the slew rate of a VOA point is improved, and the transient response capability is improved.
Preferably, the compensation network comprises a resistor R0, a capacitor C0 and a capacitor C1, one end of the resistor R0 is connected with a common terminal of PM4 and NM4, the other end of the resistor R0 is connected with one end of a capacitor C0, the other end of the capacitor C0 is grounded, one end of the capacitor C1 is connected with a common terminal of PM4 and NM4, and the other end of the capacitor C1 is grounded. The main purpose is to ensure the stability of the LDO and ensure that a loop is stable and does not oscillate when the LDO works normally.
Preferably, the driving stage and the voltage divider circuit include an NMOS transistor NM5, a resistor R1, and a resistor R2, a gate of the NMOS transistor NM5 is connected to the compensation network, a source of the NMOS transistor NM5 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the resistor R2, the other end of the resistor R2 is grounded, a common terminal of the resistor R1 and the resistor R2 is connected to one end of a transient response enhancement capacitor C3, and the other end of the transient response enhancement capacitor C3 is connected to a common terminal of the NM2 and the NM 4.
Preferably, the equivalent load capacitance is formed by a parasitic capacitance of an internal integrated circuit in a non-capacitive application. The CL of the non-capacitive LDO circuit has an equivalent capacitance of the order of nF.
Preferably, the equivalent load capacitor is composed of an external capacitor, a packaging capacitor and an internal circuit parasitic capacitor when a capacitor is applied. The equivalent capacitance of the CL of the capacitive LDO circuit is in the order of μ F.
The transient response enhanced capacitor C3 mainly has the main functions of detecting the transient change of the output voltage of VOUT through the voltage division points of the resistors R1 and R2, and VOA can quickly respond to the transient change trend of VOUT through a feedback loop, so that the transient response capability of LDO in the application without capacitor is improved;
the driving stage and the voltage division circuit mainly comprise an NOMS driving stage NM5, a resistor R1 and a resistor R2, the main function is to combine with an operational amplifier circuit to generate the output voltage of the LDO, when the whole loop is stably established, VREF is VDIV, and the output voltage is as follows:
it is following right the utility model provides a voltage generation circuit carries out the analysis:
1) and circuit stability analysis:
the poles-zero in the circuit are specified as follows:
wherein ω isZIs a circuit zeroPoint, ωp1、ωp2Two main poles of the circuit, rOP4And rON4PM4 and NM4 small signal drain-source equivalent impedances, g, of MOS transistormN5To drive the transconductance of the tube NM5, the other poles are outside the unity gain bandwidth.
When no capacitor is applied, the equivalent capacitance of the load CL consists of the parasitic capacitance of the internal circuit, a large-scale SOC circuit is adopted, the equivalent capacitance of the CL of the no-capacitor LDO circuit is in nF magnitude, and at the moment, omega is omegap1<ωp2<ωZAnd the other poles are outside the unit gain bandwidth, so that the stability of the LDO can be ensured.
When the capacitance is applied, the equivalent capacitance of CL is in the mu F order, and then omegap2<ωp1<ωZAnd other poles are outside the unit gain bandwidth, so that the stability of the LDO can be ensured.
2) Transient response analysis:
when having the electric capacity to apply, external capacitor is at mu F magnitude, and its big electric capacity charge amount of capacitance can guarantee the good effect of transient response, and this patent explains mainly to the transient response when having no electric capacity to apply, and concrete theory of operation is as follows:
if the equivalent load RL transient change is a heavy load, namely RL equivalent impedance transient becomes small, VOUT can cause transient decline due to insufficient bandwidth of the whole loop, VDIV after voltage division can also transiently decline, VDIV < VREF of the operational amplifier circuit at the moment, current i1 charges capacitors C0 and C1, and therefore grid voltage VOA of a driving tube NM5 is increased, driving capacity of NM5 is increased, current is provided for outputting VOUT, transient decline voltage is compensated, and the whole loop is built and stabilized again.
If the equivalent load RL transient state changes to the light load, RL equivalent impedance transient state becomes big promptly, VOUT can cause the transient state to rise because whole loop bandwidth is not enough this moment, VDIV after the partial pressure also can the transient state rise, VDIV > VREF of operational amplifier circuit this moment, electric capacity C0 and C1 discharge through electric current i2, thereby make the grid voltage VOA of drive tube NM5 reduce, reduce NM 5's driving capability, reduce output VOUT drive current, the voltage that the compensation transient state rises, thereby whole loop is established once more and is stable.
As described above, the transient response of the capacitor-less LDO is mainly determined and the charging/discharging speed of the VOA point is determined. When the transient change of VOUT is in the order of mus, the transient response is mainly determined by the bandwidth and the slew rate of the operational amplifier circuit.
When RL IS heavily loaded, VDIV transient IS reduced, and most of the current of current source IS mainly flowing through PM1 and NM1 branches, since NM3 mirrors NM1 current twice, NM3 and PM3 branch currents are equal to those of PM1 and NM1 branches, assuming Ip. When this patent design, make (W/L) PM4 (N is (W/L) PM 3) to make VOA point charge flow i1 be N times Ip, improved the speed of charging greatly, and other branches are one time mirror image, have reduced the consumption.
Secondly, when RL IS light load, VDIV transient rise, most of current of the current source IS mainly flows through PM2 and NM2 branch circuits, and if Ip IS assumed, when the current source IS designed, the (W/L) NM4 IS set to N (W/L) NM2, and since NM4 IS 4N times of mirror image NM2 current, the discharge current i2 at VOA point IS N times of Ip, the discharge speed IS greatly improved, and other branch circuits are all one time of mirror image, so that the power consumption IS reduced.
When VOUT transient variation is below 100ns, the bandwidth and slew rate of the operational amplifier circuit are limited, and the VOA charging and discharging speed is accelerated mainly through the transient response reinforced capacitor.
When RL is heavy load, VOUT is reduced transiently, VDIV is reduced transiently through resistance voltage division, and because the charge of the capacitor C3 cannot be suddenly changed, when VDIV connected to the right plate of the C3 is reduced transiently, the left plate of the C3 is also reduced transiently, so that the grid voltage of the NM4 is reduced transiently. At this time, when the gate of the NM4 is lowered, the VOA is supplied with a transient charging current by the PM4 of the comparator circuit composed of the local circuits NM4 and PM4 of the operational amplifier, and since the comparator circuit composed of the NM4 and PM4 has only two devices, the bandwidth and slew rate of the comparator circuit are far greater than those of the operational amplifier, so that the transient response capability below 100ns is improved.
Secondly, when RL is light load, VOUT rises transiently, VDIV also rises transiently through resistance voltage division, and because the charge of the capacitor C3 can not change suddenly, when the voltage VDIV connected to the right plate of the C3 rises transiently, the left plate of the C3 also rises transiently, so that the grid voltage of the NM4 rises transiently. At this time, NM4 is considered to be only a switching tube, and the switching speed is much higher than the bandwidth and slew rate of the operational amplifier, thereby improving the transient response capability below 100ns magnitude.
3) And fault suppression analysis:
the main failure generation reason is that the charge of the drain and drain capacitors CDGN5 and CSDP4 of the drain and drain capacitors CDGN5 and PM4 of NM5 at VOA cannot be changed transiently during transient power-up, and the capacitance value CDGN5> > CSDP4 is determined by the main CDGN5 of transient failure due to the large requirement of driving capability and the large parasitic capacitance of NM5 during circuit design. When the power supply AVD is powered on transiently, the drain voltage of NM5 rises transiently, when the power-on speed is very fast, the charge of the CDGN5 cannot change suddenly, so that the gate voltage of NM5 rises transiently, and the time constant determined by the bandwidth of the whole loop is far larger than the transient power-on speed, so that NM5 works in a similar switching state, the gate voltage rises transiently along with the power supply voltage, the output VOUT is upward failed, the stable speed is reduced, and even the voltage withstanding problem of a later-stage circuit is caused.
When the circuit is designed, a capacitor C1 and a capacitor C2 are introduced, the capacitance values are large, when the circuit does not work, the charges are 0, the lower plate is grounded, the upper plate voltage is also 0, when the power supply is powered on transiently, the charges of the capacitors C0 and C1 cannot change suddenly, the capacitance values are larger than CDGN5, the grid voltage of NM5 rises gradually from a lower value instead of changing along with the power supply voltage AVD, and therefore the output voltage VOUT also rises gradually from a low voltage, and the generation of faults is effectively inhibited.
The beneficial effects of the utility model reside in that:
1. the capacitor-free and capacitor-containing application can be compatible, namely the load capacitor is not constrained, and the capacitor-free application can be selected on occasions with less strict transient response requirements, so that the cost is saved; in the application occasion with strict transient response requirement, the capacitor can be externally hung;
2. when a capacitor-free structure is used, a transient response strengthening circuit is designed and added, so that the transient response time in the capacitor-free application is prolonged;
3. when no capacitor is applied, the faults generated in the starting process are reduced.
In light of the foregoing description of the preferred embodiments of the present invention, those skilled in the art can now make various alterations and modifications without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (9)
1. A voltage generation circuit is characterized by comprising an operational amplification circuit, a compensation network, a driving stage, a voltage division circuit and a transient response strengthening capacitor, wherein the output end of the operational amplification circuit is connected with the input end of the compensation network, the output end of the compensation network is connected with the input ends of the driving stage and the voltage division circuit, the output ends of the driving stage and the voltage division circuit output voltage through an equivalent load resistor and an equivalent load capacitor, and the transient response strengthening capacitor is respectively connected with the operational amplification circuit, the driving stage and the voltage division circuit.
2. The voltage generation circuit of claim 1, wherein the operational amplifier circuit comprises a current source IS, NMOS transistors NM 1-NM 4 and PMOS transistors PM 1-PM 4, the PMOS transistors PM1 and PM2 are input pair transistors, the current source IS respectively connected with PM1 and PM2, the NM1 and NM3, the NM2 and NM4, and the PM3 and PM4 are mirror pair transistors.
3. The voltage generation circuit of claim 2, wherein the ratio of width to length of the PMOS transistors PM1 to PM2 is 1:1, and the ratio of width to length of the NM1 to NM3, the ratio of width to length of the NM2 to NM4, and the ratio of width to length of the PMOS transistors PM3 to PM4 are 1:1, 1: N, and 1: N, respectively.
4. The voltage generation circuit of claim 2, wherein the compensation network comprises a resistor R0, a capacitor C0, and a capacitor C1, one end of the resistor R0 is connected to the common terminal of PM4 and NM4, the other end of the resistor R0 is connected to one end of a capacitor C0, the other end of the capacitor C0 is connected to ground, one end of the capacitor C1 is connected to the common terminal of PM4 and NM4, and the other end of the capacitor C1 is connected to ground.
5. The voltage generation circuit of claim 2, wherein the driving stage and the voltage divider circuit comprise an NMOS transistor NM5, a resistor R1, and a resistor R2, a gate of the NMOS transistor NM5 is connected to the compensation network, a source of the NMOS transistor NM5 is connected to one end of a resistor R1, another end of the resistor R1 is connected to one end of a resistor R2, another end of the resistor R2 is grounded, a common terminal of the resistor R1 and the resistor R2 is connected to one end of a transient response enhancement capacitor C3, and another end of the transient response enhancement capacitor C3 is connected to a common terminal of the NM2 and the NM 4.
6. A voltage generation circuit according to claim 1, wherein the equivalent load capacitance is formed by the parasitic capacitance of the internal integrated circuit when no capacitance is applied.
7. The voltage generation circuit of claim 6, wherein the CL of the capacitor-less LDO circuit has an equivalent capacitance on the order of nF.
8. The voltage generation circuit of claim 1, wherein the equivalent load capacitor comprises an external capacitor, a package capacitor, and an internal circuit parasitic capacitor when a capacitor is applied.
9. The voltage generation circuit of claim 8, wherein the CL of the capacitive LDO circuit has an equivalent capacitance of the order of μ F.
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| CN202121621636.XU CN215117303U (en) | 2021-07-16 | 2021-07-16 | Voltage generating circuit |
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| CN202121621636.XU CN215117303U (en) | 2021-07-16 | 2021-07-16 | Voltage generating circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117543972A (en) * | 2024-01-10 | 2024-02-09 | 深圳市微源半导体股份有限公司 | Fast dynamic response switching converter circuit, switching power supply and electronic device |
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2021
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117543972A (en) * | 2024-01-10 | 2024-02-09 | 深圳市微源半导体股份有限公司 | Fast dynamic response switching converter circuit, switching power supply and electronic device |
| CN117543972B (en) * | 2024-01-10 | 2024-03-26 | 深圳市微源半导体股份有限公司 | Fast dynamic response switching converter circuit, switching power supply and electronic device |
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Effective date of registration: 20231030 Address after: Unit 709, 7th Floor, Building E, Xiamen Center, No. 567 Haicang Avenue, Haicang District, Xiamen City, Fujian Province, 361000 Patentee after: Xiamen Hexin Semiconductor Co.,Ltd. Address before: Room 403-4, 4 / F, Tsinghua information port complex, North District, high tech Industrial Park, Xili street, Nanshan District, Shenzhen, Guangdong 518000 Patentee before: Mico Microelectronics (Shenzhen) Co.,Ltd. |