CN101471631B - Cmos audio operational amplifier - Google Patents
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Abstract
A CMOS audio operational amplifier comprises an input stage of a folding cascode, a double-ended-to-single-ended current mirror, a Class AB floating bias, a biasing circuit, a push-pull common source output stage and a NMOS(M27), wherein, a drain electrode of the NMOS(M27) is connected with a signal input terminal of the double-ended-to-single-ended current mirror, a grid electrode of the NMOS(M27) is connected with a voltage bias terminal of the Class AB floating bias, and a source electrode of the NMOS(M27) is connected with a signal output terminal of the input stage of the folding cascode. The invention adds the NMOS device to the CMOS audio amplifying circuit in the prior art so as to isolate the fluctuation of the power voltage, and a method for ensuring equal voltages of the output terminals of the folding cascade is used, so that the anti-RFI (radio frequency interference) problem of the CMOS audio amplifying circuit is solved. The amplifier can be applied to the field of audio operational amplification, for example, the amplifier can be used as an operational amplifying circuit of a microphone input signal in a hand-free call control circuit with sound control switching.
Description
Technical field
The present invention relates to CMOS analog integrated circuit design field, particularly the CMOS audio operational amplifier.
Background technology
The employing bipolar process design that audio operational amplifier of the prior art has; The amplifier of the microphone input signal that is used for acoustic control switching hand-free call control circuit for example shown in Figure 1; Wherein: L1 is a reference voltage input; Transistor Q6, Q7 and resistance R 2 constitute current biasing circuit, are the bias currents that provide at different levels; Resistance R 1 is formed differential input stage with transistor Q5, Q1, Q1b, Q3, Q3b, Q2 and Q4; Wherein transistor Q5 is a constant-current source; It is right that transistor Q1 and Q3 form the difference input, and transistor Q1b and Q3b are isocon, make that the quiescent current of transistor Q1 and Q3 is 1/4* (IQ1+IQ1b); Thereby obtain suitable differential pair gain, transistor Q2 and Q4 form the current mirror load of differential pair; Resistance R 1, transistor Q11 and Q11b and resistance R 6, transistor Q22 have formed two-stage and have penetrated a grade follower; Transistor Q9, Q8, Q18, Q14 and Q20 form the output stage of full NPN tubular construction, to reach the purpose of optimizing bandwidth and phase margin, also provide the one-level common emitter simultaneously and amplify; The effect of transistor Q16 and R3 is to prevent intermodulation distortion; Capacitor C 1 and resistance R 11 provide the compensation of frequency response.
When each device shown in the figure takes off the listed parameter of face table 1,
| The device mark | Parameter value | The device mark | Parameter value |
| Q1 | m＝0.25 | Q3 | m＝0.25 |
| Q1b | m＝0.75 | Q3b | m＝0.75 |
| Q5 | m＝0.5 | Q11 | m＝0.5 |
| R1 | 1.6KΩ | R2 | 12.5KΩ |
| R3 | 2.697KΩ | R4 | 680Ω |
| R5 | 450Ω | R6 | 1.75KΩ |
| R11 | 200Ω |
The Specifeca tion speeification index of this circuit is following:
Open-loop gain (Open Loop Gain)=92.44dB;
Unity gain bandwidth (GB)=1.53MHz;
Allow phase distortion (Phase Margin): 61degree.
CMOS technology has become the main flow manufacturing process of integrated circuit now, therefore is necessary to adopt CMOS technology that original circuit is designed again.As shown in Figure 2; Be the circuit diagram of CMOS audio operational amplifier in the prior art, it comprises: the unsteady biasing circuit of Class AB that the folded common source and common grid input stage of being made up of PMOS M1～M4 and NMOS M9～M12, the both-end of being made up of PMOS M15～M18 change the one-terminal current mirror, is made up of PMOS M13, NMOS M14, PMOS M20, PMOS M201, PMOS M21～M22, NMOS M19, NMOS M191 and NMOS M23～M24, the biasing circuit of being made up of PMOS M5～M6 and NMOS M7～M8, recommend the common source output stage by what PMOS M25 and NMOS M26 and resistance R 1, R2 and capacitor C 1, C2 formed.
It has the advantage that realizes the system integration more easily with respect to the audio operational amplifier of aforementioned bipolar process of the prior art, but it also has some defectives, and bigger etc. like input offset voltage, this is a CMOS audio operational amplifier problem demanding prompt solution.
In addition, in the communication applications field, anti-radio frequency interference problem also is one of right subject matter of designer's demand side.
Summary of the invention
To the problems referred to above; One of the object of the invention is exactly to optimize CMOS audio frequency of the prior art to amplify arithmetic unit; Reduce its input offset voltage; Another purpose is to improve PSRR (the being PSRR Power supply rejection ratio) performance index of circuit, to improve the ability of anti-radio frequency interference.
Therefore; The present invention proposes a kind of CMOS audio operational amplifier; Comprise: folded common source and common grid input stage, both-end change one-terminal current mirror, Class AB unsteady biasing, biasing circuit, recommend common source output stage and a NMOS M27; The drain electrode of said NMOS M27 links to each other with the signal input part that said both-end changes the one-terminal current mirror; The grid of said NMOS M27 links to each other with the voltage bias end of the unsteady biasing of said Class AB, and the source electrode of said NMOS M27 links to each other with the signal output part of said folded common source and common grid input stage.
Increased a N type cmos device in the present invention's CMOS audio amplifier circuit in the prior art; Through its buffer action to mains fluctuations; And make the means that the voltage of folded common source and common grid output equates, thereby solved the anti-radio frequency interference problem of CMOS audio amplifier circuit.The present invention can be used in the audio operational amplification sector, as switching the operational amplification circuit of the microphone input signal in the hand-free call control circuit as acoustic control.
Description of drawings
Fig. 1 is for utilizing the circuit diagram of the audio operational amplifier of bipolar technology in the prior art;
Fig. 2 is for utilizing the circuit diagram of CMOS audio operational amplifier in the prior art;
Fig. 3 is the circuit diagram of CMOS audio operational amplifier of the present invention;
Fig. 4 is the embodiment circuit diagram of CMOS audio operational amplifier of the present invention;
Fig. 5 is the AC characteristic simulation result of the embodiment of CMOS audio operational amplifier of the present invention;
Fig. 6 is the PSRR simulation result of embodiment of the audio operational amplifier of CMOS technology of the present invention;
Fig. 7 is common-mode rejection ratio (CMRR) simulation result of embodiment of the audio operational amplifier of CMOS technology of the present invention.
Embodiment
Below in conjunction with description of drawings embodiment of the present invention.In this explanation; CMOS comprises N type CMOS (NMOS) and P type CMOS (PMOS), hereinafter, when the type of lay special stress on CMOS, is referred to as NMOS or PMOS; Ordinary circumstance summary is referred to as CMOS, can learn its particular type with reference to the CMOS parameter list in this embodiment when needing.
As shown in Figure 3, CMOS audio operational amplifier of the present invention comprises: folded common source and common grid input stage, both-end change one-terminal current mirror, Class AB unsteady biasing circuit, biasing circuit, recommend common source output stage and a NMOS M27.
Specify the circuit design process of the embodiment of audio operational amplifier of the present invention below.
According to the requirement that hand-free call system microphone amplifier is switched in acoustic control, can set following parameter index:
● offset voltage:＜50mV
● dc open-loop gain:＞80dB
● unity gain bandwidth:＞3MHz
● output high level driving force: Vdd=5V, during Iout=-1mA, Vout＞3.7V
● output low level driving force: Vdd=5V, during Iout=1mA, Vout＜200mV
● total harmonic distortion level: 0.15%
The above circuit requirement of following basis comes design circuit.This audio operational amplifier can adopt 1.2 microns bipolar CMOS technologies of Belling (Belling 1.2um Bi CMOS) to design.
At first need choose suitable circuit structure, consider the open-loop gain requirement of 80dB, adopt dual-stage amplifier proper.
Choosing of input stage structure; The common mode electrical level of considering this application generally is (system's common mode electrical level exchanges ground, is generally the half the of supply voltage) confirmed; So common-mode input range is not had special requirement, therefore can select for use the PMOS differential pair tube to constitute input stage.Why adopt the PMOS differential pair tube to be because can the substrate of differential pair tube be connected to the common source end like this, thereby eliminate substrate bias effect, improve the linearity.And; Input stage can also adopt the cascade structure of folded common source and common grid; The advantage of this structure is the gain that can provide higher and the bigger input and output amplitude of oscillation, and settling time and higher unity gain bandwidth fast, and the frequency compensation of this structure also can be allowed a choice in addition.
Output stage can adopt the common source configuration of recommending that approximate full amplitude of oscillation output can be provided, and its bias mode adopts the unsteady bias structure of Class AB.The unsteady bias structure of Class AB has flexible design, can reduce characteristics such as intermodulation distortion.CMOS M13 and M14 are the NMOS of parallel connection and the unsteady biasing that the PMOS pipe is formed, and CMOS M19, M191, M21 and M22 have formed the biasing circuit of CMOS M13, and CMOS M20, M201, M23 and M24 have formed the biasing circuit of CMOS M14.The effect of NMOS M27 is that the drain terminal voltage of CMOS M9 and M11 is equated; Also isolated simultaneously of the influence of the grid voltage of CMOS M15 and M16 when mains fluctuations, thereby played the effect of optimization PSRR performance, the anti-radio frequency interference ability of raising CMOS M9.
Aspect the frequency compensation mode, can adopt the Miller resistance capacitance structure of efferent duct, to realize the limit separation and to eliminate the RHP purpose at zero point.
In addition, in the biasing of whole amplifier, can adopt the automatic biasing cascodes, to improve the PSRR of amplifier.
Therefore, obtain the circuit structure of embodiment as shown in Figure 4.
Wherein input stage is the folded common source and common grid input stage, and it is made up of PMOS M1～M4 and NMOS M9～M12; Wherein: the source electrode of PMOS M1 and M2 links to each other, and the drain electrode of PMOS M1 connects the drain electrode of M10, and the drain electrode of M2 connects the drain electrode of M12, constitutes the difference input to pipe, and PMOS M3 and M4 constitute the cascode current source, as the tail current of input to pipe; M9～M12 grid links to each other, and connects gate bias voltage; The source electrode of M10 and M12 connects power supply ground, and the drain electrode of M10 connects the source electrode of M9, and the drain electrode of M12 connects the source electrode of M11; The drain electrode of M9 connects the source electrode of M27, and the drain electrode of M11 connects the drain electrode of M13 and the source electrode of M14.
Said both-end changes the one-terminal current mirror and is made up of PMOS M15～M18; Wherein the annexation of PMOS M15～M18 is: each grid of M15, M16, M17 and M18 is connected and is connected with the drain electrode of M27 mutually; Wherein M15, M16 connect for the automatic biasing cascade; M17, M18 connect for the automatic biasing cascade, and M15～M18 constitutes the automatic biasing common-source common-gate current mirror.And said NMOS M27 with the annexation of said PMOS M15～M18 is: the drain electrode of M27 links to each other with the input (leakage of M15, grid) of the automatic biasing common-source common-gate current mirror that is made up of M15～M18.
Said Class AB floats to setover and is made up of PMOS M13, NMOS M14, PMOS M20, PMOS M201, PMOS M21～M22, NMOS M19, NMOS M191 and NMOSM23～M24; Wherein the annexation of each device is: M21, M22 are that the lamination of two grid leak short circuit PMOS connects; M23, M24 are that the lamination of two grid leak short circuit NMOS connects; M20, M201 connect for the automatic biasing cascade, and M19, M191 connect for the automatic biasing cascade.The drain electrode of M23 links to each other with the drain electrode of M201, and the drain electrode of M191 links to each other with the drain electrode of M21.The grid of M13 links to each other with the drain electrode of M191, and the grid of M14 links to each other with the drain electrode of M201.The source electrode of M13 links to each other with the drain electrode of M14, and the drain electrode of M13 links to each other with the source electrode of M14.And the grid level of said NMOS M27 links to each other with the grid level of said NMOS M14, and the relation between the breadth length ratio of said NMOS M27 and said NMOS M14 is designed to make that the drain terminal voltage of NMOS M9 and NMOS M11 equates simultaneously.
Said biasing circuit is made up of PMOS M5～M6 and NMOS M7～M8; Wherein the annexation of each device is: M7, M8 are that cascade connects, and M5, M6 connect for the automatic biasing cascade.And the grid of said NMOS M7～M8 is the bias voltage output, and it is connected to unsteady biasing of said Class AB and said folded common source and common grid input stage, for it provides bias voltage.
The said common source output stage of recommending is made up of PMOS M25 and NMOS M26 and resistance R 1, R2 and capacitor C 1, C2; Its annexation is: M25, M26 drain electrode link to each other, for recommending output; The source electrode of M25 connects VDD, and the PMOS efferent duct control signal end that grid connects the unsteady biasing of Class AB is the source electrode of PMOS M13; M26 source electrode connect GND, it is the source electrode of NMOS M14 that grid connects the float NMOS efferent duct control signal end of biasing of Class AB.
Confirmed circuit structure, next the breadth length ratio of designs C metal-oxide-semiconductor.The characteristic parameter of the Belling 1.2um BiCMOS technology that adopts in the present embodiment is following:
Minimum breadth length ratio is that W/L is 1.2um; μ
NC
Ox≈ 68.7; μ
pC
Ox≈ 21.2; Vthn ≈ 0.7; Vthp ≈ 0.8;
At first confirm the size of input stage.Consider that system does not all have special requirement to common-mode input range and switching rate (slew rate) in this enforcement, so the quiescent current of input stage is relatively loose to the dimensional requirement of pipe with input.Can choose static tail current source at this is 20 micromicroamperes (20uA).Consider the requirement that increases open-loop gain and unity gain bandwidth, can the input pipe breadth length ratio suitably be done greatly, so that bigger input stage mutual conductance (Gm) to be provided.Thermal noise, flicker noise and imbalance that simultaneously bigger mutual conductance and grid area also can improve input stage.Therefore can designing input, pipe is of a size of breadth length ratio is 40um/2um, and import mutual conductance and be about 92uS this moment.
Next design folded-cascode circuit.The electric current of CMOS M9 and M10 can not be zero when the large signal operation in order to make, and is 1.2 times of input stage tail current so get the quiescent current of CMOS M10 and M12, i.e. 24uA.CMOS M15～M18 forms the automatic biasing common-source common-gate current mirror to realize differential-to-single-ended conversion, and its breadth length ratio has no special requirements, and is identical with the input stage tail current source.
Next design the unsteady biasing of efferent duct and Class AB.In order to obtain phase margin preferably, the mutual conductance of general output stage is more than ten times of input stage mutual conductance.Yet consider and frequency of utilization to compensate, so 500uS is got in the mutual conductance of output pmos.Then can get by the mutual conductance formula:
Because CMOS M17 and M18 are cascodes, so the grid potential of CMOS M25 is less to the current mirror influence of CMOS M15～M18, so there is not special requirement.Therefore can get I
25=50uA, then S
25=118.(I
25Expression is numbered the drain terminal electric current of the metal-oxide-semiconductor of M25, S
25Expression is numbered the breadth length ratio of the metal-oxide-semiconductor of M25, and the implication of simileys hereinafter by that analogy)
When static, the electric current that flows through among float offset CMOS M13 and the M14 is:
The unsteady bias loop of noticing PMOS pipe is that following relation is arranged between electric current and the breadth length ratio of CMOS M13, M25 and M21, M22:
And can be when designs C lass AB setovers so that when output pmos drives load, in output NMOS pipe, keep a little electric current (getting 5uA); Like this when load transfers the driving of NMOS pipe to from being driven by the PMOS pipe; Just eliminate NMOS pipe by turn-offing the process of opening, thereby further optimized intermodulation distortion.In order to realize this purpose, then need satisfy following relation:
(1) formula and (2) formula simultaneous can solve: S
13=6.1
If get I
21=I
22=5uA then solves: S
21=S
22=6.74
Unsteady bias loop CMOS M14, M26, M23 and the M24 of NMOS pipe has identical characteristic with the unsteady bias loop of PMOS pipe, and in order to satisfy I
13=I
14, I
25=I
26, the breadth length ratio of the pipe in these two loops need satisfy following relation:
S
26Can try to achieve by following equality:
Thereby can confirm by (3) formula: S
14=1.88, S
23=S
24=2.08
Carry out frequency compensated design at last, adopt the combination of efferent duct Miller electric capacity and resistance, Miller electric capacity is got 1pF, and the value of zero-regulator resistor is 1/GmII, is 1.13K through emulation, and wherein GmII is the mutual conductance of output stage.
The parameter list of the type of each CMOS pipe and size is following in the circuit of Fig. 4: (u is the micron unit, and m is the number of the metal-oxide-semiconductor of parallel connection)
| Transistor (type) | Size (width/length) | Transistor (type) | Size (width/length) |
| M1(PMOS) | 20u/2u，m＝2 | M16(PMOS) | 9u/4u |
| M2(PMOS) | 20u/2u，m＝2 | M17(PMOS) | 9u/4u，m＝2 |
| M3(PMOS) | 9u/4u | M18(PMOS) | 9u/4u |
| M4(PMOS) | 9u/4u | M19(NMOS) | 4u/4u |
| M5(PMOS) | 9u/4u | M191(NMOS) | 4u/4u，m＝2 |
| M6(PMOS) | 9u/4u | M20(PMOS) | 2.5u/4u |
| M7(NMOS) | 15.8u/4u，m＝2 | M201(PMOS) | 2.5u/4u，m＝2 |
| M8(NMOS) | 15.8u/4u | M21(PMOS) | 8.1u/1.2u |
| M9(NMOS) | 15u/4u，m＝2 | M22(PMOS) | 8.1u/1.2u |
| M10(NMOS) | 15u/4u | M23(NMOS) | 2.5u/1.2u |
| M11(NMOS) | 15u/4u，m＝2 | M24(NMOS) | 2.5u/1.2u |
| M12(NMOS) | 15u/4u | M25(PMOS) | 14.16u/1.2u，m＝10 |
| M13(PMOS) | 7.32u/1.2u | M26(NMOS) | 21.92u/2.4u，m＝4 |
| M14(NMOS) | 2.256u/1.2u | M27(NMOS) | 4.5u/1.2u |
| M15(PMOS) | 9u/4u，m＝2 |
Through emulation, the quiescent current of the CMOS audio operational amplifier that above-mentioned design is accomplished is 166uA, and dc open-loop gain is 89.4dB; Unity gain bandwidth is 5.58MHz, and phase margin is 61 degree, and PSRR is-89.8dB under the 217Hz frequency; Input 10% to the CMRR under the pipe mismatch situation is-80dB; Output low level is 65mV under the 1mA output current condition, and the output high level is 4.89V, and THD (being total harmonic distortion Total harmonic distortion) is 66m%.Each item index all meets design requirement.
As shown in Figure 5, the AC characteristic simulation result of the audio operational amplifier that above-mentioned design is accomplished is: DC current gain (DC gain): 89.4dB; Phase margin (PM): 61degree; Unity gain bandwidth (GB): 5.58MHz.
As shown in Figure 6, the PSRR simulation result of above-mentioned audio operational amplifier is: when 217Hz be-89.8dB.
As shown in Figure 7, the CMRR simulation result of above-mentioned audio operational amplifier is: be under the situation of 10% mismatch when input stage, for-80dB.
Audio operational amplifier circuit of the present invention can be used for acoustic control and switches in the hand-free call control circuit to realize the amplification of microphone input signal, also can be used for other audio frequency amplification sectors.
Foregoing only is to exemplary description of the present invention, and those skilled in the art can make modification to the present invention under the situation that does not depart from spirit of the present invention, and these modifications also should be regarded as dropping within protection scope of the present invention.Protection scope of the present invention is not limited to above-mentioned embodiment, but is defined by the claims.
Claims (1)
1.CMOS audio operational amplifier; It is characterized in that; Comprise: folded common source and common grid input stage, both-end change one-terminal current mirror, Class AB unsteady biasing, biasing circuit, recommend common source output stage and a NMOS M27; The drain electrode of said NMOS M27 links to each other with the signal input part that said both-end changes the one-terminal current mirror; The grid of said NMOS M27 links to each other with the voltage bias end of the unsteady biasing of said Class AB, and the source electrode of said NMOS M27 links to each other with the signal output part of said folded common source and common grid input stage; Wherein:
Said folded common source and common grid input stage is made up of PMOS M1～M4 and NMOS M9～M12; The source electrode of M1 and M2 links to each other, and the drain electrode of M1 connects the drain electrode of M10, and the drain electrode of M2 connects the drain electrode of M12, constitutes the difference input to pipe, and M3 and M4 constitute the cascode current source, as the tail current of said input to pipe; M9～M12 grid links to each other, and connects gate bias voltage; The source electrode of M10 and M12 connects power supply ground, and the drain electrode of M10 connects the source electrode of M9, and the drain electrode of M12 connects the source electrode of M11; The drain electrode of M9 connects the source electrode of M27, and the drain electrode of M11 connects the drain electrode of M13 and the source electrode of M14;
Said both-end changes the one-terminal current mirror and is made up of PMOS M15～M18; Each grid of PMOS M15～M18 connects mutually and is connected with the drain electrode of M27, and M15, M16 connect for the automatic biasing cascade, and M17, M18 connect for the automatic biasing cascade, and M15～M18 constitutes the automatic biasing common-source common-gate current mirror; The drain electrode of M15 links to each other with the drain electrode of M27;
Said Class AB floats to setover and is made up of PMOS M13, NMOS M14, PMOS M20, PMOS M201, PMOS M21～M22, NMOS M19, NMOS M191 and NMOS M23～M24; M21, M22 are that the lamination of two grid leak short circuit PMOS connects; M23, M24 are that the lamination of two grid leak short circuit NMOS connects; M20, M201 connect for the automatic biasing cascade, and M19, M191 connect for the automatic biasing cascade; The drain electrode of M23 links to each other with the drain electrode of M201, and the drain electrode of M191 links to each other with the drain electrode of M21; The grid of M13 links to each other with the drain electrode of M191, and the grid of M14 links to each other with the drain electrode of M201; The source electrode of M13 links to each other with the drain electrode of M14, and the drain electrode of M13 links to each other with the source electrode of M14; The grid level of M14 links to each other with the grid level of M27, and simultaneously the relation between the breadth length ratio of M27 and M14 is designed to make that the drain voltage of M9 and M11 equates;
Said biasing circuit is made up of PMOS M5～M6 and NMOS M7～M8; M7, M8 are that cascade connects, and M5, M6 connect for the automatic biasing cascade, and the grid of M7～M8 is the bias voltage output, and it is connected to unsteady biasing of said Class AB and said folded common source and common grid input stage, for it provides bias voltage;
The said common source output stage of recommending is made up of PMOS M25 and NMOS M26 and resistance R 1, R2 and capacitor C 1, C2; M25, M26 drain electrode link to each other, for recommending output; The source electrode of M25 connects VDD, and the PMOS efferent duct control signal end that grid connects the unsteady biasing of said Class AB is the source electrode of PMOS M13; M26 source electrode connect GND, it is the source electrode of NMOS M14 that grid connects the float NMOS efferent duct control signal end of biasing of Class AB.
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| CN116436410B (en) * | 2023-04-11 | 2023-11-17 | 许昌学院 | Amplifying integrated circuit applied to electric automobile charge-discharge control system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5933055A (en) * | 1996-02-15 | 1999-08-03 | Matsushita Electric Industrial Co., Ltd. | Operational amplifier operable with high performance even at a low voltage |
| CN1607724A (en) * | 2003-10-13 | 2005-04-20 | 三星电子株式会社 | Class AB rail-to-rail operational amplifier |
| CN1996749A (en) * | 2006-01-06 | 2007-07-11 | 恩益禧电子股份有限公司 | Differential amplifier, data driver and display device |
-
2007
- 2007-12-29 CN CN2007101738658A patent/CN101471631B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5933055A (en) * | 1996-02-15 | 1999-08-03 | Matsushita Electric Industrial Co., Ltd. | Operational amplifier operable with high performance even at a low voltage |
| CN1607724A (en) * | 2003-10-13 | 2005-04-20 | 三星电子株式会社 | Class AB rail-to-rail operational amplifier |
| CN1996749A (en) * | 2006-01-06 | 2007-07-11 | 恩益禧电子股份有限公司 | Differential amplifier, data driver and display device |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2002-368557A 2002.12.20 |
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| Publication number | Publication date |
|---|---|
| CN101471631A (en) | 2009-07-01 |
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