CN100505524C - Limiting amplifiers - Google Patents

Abstract

A limiting amplifier with an input stage with dc offset cancellation, identical gain stages, an output buffer and a feedback filter. The input stage receives a differential input signal and outputs a first intermediate differential signal. The gain stages are cascaded to amplify the first intermediate differential signal and generate a second intermediate differential signal, amplified by the output buffer to produce an output signal. The feedback filter provides a dc offset voltage of the output signal to the input stage for the dc offset cancellation. The input stage comprises a resistor network coupled between a pair of input nodes and a power line and comprising a common resistor, a pair of load resistors and a shunt resistor. The load resistors share a common terminal connected to the common resistor that is connected to the power line. The shunt resistor has two terminals respectively connected to the load resistors.

Description

Limiting amplifier

Technical field

The present invention relates generally to a kind of limiting amplifier, is particularly to a kind of limiting amplifier that is applied to optical communication.

Background technology

High speed limiting amplifier (limiting amplifier) has important role in wire communication, in order to amplify small-signal to transmit the data recovery circuit (datarecovery circuit) of bigger output amplitude to the back level.Fig. 1 represents traditional wired communication system, and diode 12 is exported light signals to receiver by driver/modulator 14 via optical fiber 15.Optical diode 16 detects these light signals to produce low current signal, and it can be converted to voltage signal by trans-impedance amplifier (transimpedance amplifier) 18, and the amplitude of this voltage signal is generally several or dozens of millivolt.This weak voltage signal demand limiting amplifier 20 from trans-impedance amplifier 18 amplifies, and handles to obtain high-speed digital data so that full width (full-swing) signal to frequency and data recovery circuit (CDR) 22 to be provided.Limiting amplifier 20 be prepended to or after be connected to equalizer (figure show).

Traditional sparrow is upright-and brave cypress (Cherry-Hopper) amplifier has been applied in the limiting amplifier data transfer rate with acquisition 40Gbps in heterojunction bipolar technology (heterojunction bipolar technology), however power dissipation is bigger.In complementary metal oxide semiconductors (CMOS) (hereinafter to be referred as CMOS) technology, possible solution is to use have inductance overshooting wide-band amplifier and the distributed amplifier (DA) or the concatenation type distributed amplifier (CDA) of (inductive peaking).The bandwidth of distributed amplifier is enough, but it is low to gain.Therefore, industry need find the limiting amplifier with low-power consumption, high-gain and high bandwidth now.

Summary of the invention

Therefore, the invention provides a kind of limiting amplifier that can address the above problem.

The embodiment of the invention provides a kind of limiting amplifier, has input stage, a plurality of gain stage, output buffer stage and feedback filter.Input stage can be carried out the elimination of direct voltage deviation, can receive differential input signal and export the first intermediate differential wave.All gain stages are all identical, and serial connection is to amplify the first intermediate differential wave and to produce the second intermediate differential wave.The output buffer stage is amplified the second intermediate differential wave and is produced output signal.Feedback filter provides direct voltage deviation to the above-mentioned input stage of output signal to eliminate in order to carry out the direct voltage deviation.

In one embodiment, input stage comprises the resistor network that is coupled between a pair of input and the power line.Above-mentioned resistor network comprises: shared resistance, load resistance and shunt resistance.Shared resistance is coupled to power line.Load resistance is coupled to the shared end points of shared resistance.Shunt resistance has two-end-point, is coupled to load resistance respectively.

In another embodiment, each gain stage comprises a pair of ladder type inductor-capacitor low pass filter, each ladder type inductor-capacitor low pass filter comprises that the first inductor-capacitor network is to receive amplifying signal, the second inductor-capacitor network is connected to after the first inductor-capacitor network, and the node of above-mentioned first, second inductor-capacitor network that is connected to prime ladder type inductor-capacitor low pass filter is to output signal to back level ladder type inductor-capacitor low pass filter.

In another embodiment, above-mentioned output buffer stage comprises differential amplifier, FT frequency multiplier and negative feedback framework.Differential amplifier is as the input of above-mentioned output buffer stage.The FT frequency multiplier is contacted to differential amplifier.The negative feedback framework is connected between the input of the output of above-mentioned FT frequency multiplier and above-mentioned FT frequency multiplier.

Limiting amplifier of the present invention is realizing having high-gain when the high bandwidth amplitude limit amplifies, and can reduce the power consumption of system.

Description of drawings

Fig. 1 represents traditional wired communication system.

Fig. 2 is the schematic diagram of the limiting amplifier that example is executed according to the present invention.

Fig. 3 is the input stage 42 shown in Figure 2 and the schematic diagram of feedback filter 48.

Fig. 4 is the ladder type inductor-capacitor Bart schematic diagram of low pass filter watt now on one 4 rank.

Fig. 5 is the ladder type inductor-capacitor Bart schematic diagram of the transfer function of low pass filter watt now on one 4 rank.

Fig. 6 is one 4 notch cuttype inductor-capacitor Bart schematic diagram of the pole location of low pass filter watt now.

Fig. 7 is the schematic diagram of a pair of concatenation type distributed amplifier.

Fig. 8 is the schematic diagram according to the small-signal model of the serial connection amplifier of Fig. 7.

Fig. 9 is the schematic diagram according to the output impedance frequency response of Fig. 8.

Figure 10 is the schematic diagram of the circuit framework of single gain level.

Figure 11 is the schematic diagram of the output buffer stage of Fig. 2.

Figure 12 shows the schematic diagram of analog result of the output buffer stage of Figure 11.

Figure 13 shows the schematic diagram of the frequency response of measured limiting amplifier.

Embodiment

The feature of limiting amplifier comprises: input susceptibility, gain, bandwidth, noise margin, direct voltage deviation and output voltage amplitude.Use a high speed limiting amplifier in the embodiment of the invention with concatenation type distributed amplifier.Fig. 2 represents the limiting amplifier 40 that example is executed according to the present invention, comprises having the input stage 42 that DC deviation is eliminated function gain stage 44, output buffer stage 46, and feedback filter 48.Input stage 42 receives differential wave V _InAnd export the first intermediate differential wave V _Im1A plurality of gain stages 44 are same architecture, and series connection is to amplify the first intermediate differential wave V _Im1To produce the second intermediate differential wave V _Im2 Output buffer stage 46 is amplified the second intermediate differential wave V _Im2To produce output signal V _OutFeedback filter 48 provides output signal V _OutDirect voltage deviation to input stage 42 eliminate as DC deviation.The serial connection number of gain stage 44 satisfies the requirement of required gain, bandwidth and low input noise.

According to another embodiment of the present invention, five gain stages 44 use the concatenation type distributed amplifier can reach best amplification effect.Resistance R _FAnd capacitor C _FDetecting the direct voltage deviation of output, and corresponding voltage deviation is eliminated and is implemented on input stage 42 to stablize limiting amplifier 40 as the low path of feedback filter 48.Each gain stage 44 is used concatenation type distributed amplifiers, be configured to the Bart watt now filter construction (Butterworth filter structure) to increase bandwidth.Output buffer stage 46 use the Improvement type sparrows upright-brave cypress amplifier to be to provide high speed data transfer.

Limiting amplifier 40 as shown in Figure 2 will be described in detail as follows.

Fig. 3 is the input stage 42 shown in Figure 2 and the schematic diagram of feedback filter 48.Differential to M ₁M ₂(differential pair) uses low pass filter (each is made of resistance R F and capacitor C F) with sensing limiting amplifier output signal V _OutThe direct voltage deviation.This input matching network comprises a plurality of interior transformers (on-chip transformer) L _iAnd resistor network 52.

Each transformer L _iBe connected to corresponding input end 50 and corresponding resistance R ₁Between, as the center tap transformer so that central contact 54 to be provided, in order to export the first intermediate differential wave V _Im1Each transformer L _iHas symmetry how much (as T molded lines circles) to promote bandwidth.

Resistor network 52 is coupled to power line V _DDAnd between the input 50, must satisfy the balance between 50 ohm of Broadband Matching and the input DC deviation.Resistance R ₃As shared resistance, in order to adjust Dc bias.Resistance R ₁Be load resistance, the shared resistance R that is connected to ₃Common end points, and resistance R ₂Be shunt resistance, its two ends are connected to corresponding resistance R respectively ₁Resistance R ₁With R ₂The in parallel placement to guarantee that 50 ohm source levels connect and mitigation resistance difference.Increase resistance R ₃Can reduce resistance R to input matching circuit ₁With R ₂Required resistance value to reduce parasitic capacitance and to promote bandwidth.

The direct voltage deviation of input 42 is eliminated the feedback oscillator that design focuses on feedback filter 48 feedbacks.Owing to add by resistance R in the feedback filter 48 _FAnd capacitor C _FConstitute low pass filter, the whole structure of limiting amplifier 40 can form the response of high pass feedback frequency.For the amplifier of high-gain, the feedback oscillator of low-frequency band must cause oscillation problem to avoid noise constantly to tire out to increase to amplify by the feedback filter feedback less than 1.

For broadband and high-gain are provided, and overcome transistorized cut-off frequency restriction, can be in conjunction with several broadband technologys, comprise Bart's offered load watt now, concatenation type distributed amplifier, and active feedback.Every The Application of Technology and feature and the gain stage 44 that is realized are as described below.

The tradition wide-band amplifier is used the inductance overshooting to increase by bandwidth 80% or more with the increase transfer of data.For the bandwidth that extends, Bart watt now filter can be applied in the wide-band amplifier.Fig. 4 represents one 4 notch cuttype inductor-capacitor Bart low pass filter 54 watt now, uses two inductance L ₁And L ₂, and two capacitor C ₃And C ₄, and have one 4 rank transfer function:

$\left|\frac{V_2}{V_S}(s=\mathrm{j\&omega;})\right|=\frac{\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="C200710139029E00161.png,C200710139029E00171.png"\; state="\{\{state\}\}">K</figure-callout>}}{\sqrt{1+{\mathrm{\&epsiv;}}^2{\left(\frac{\mathrm{\&omega;}}{{\mathrm{\&omega;}}_C}\right)}^{2N}}}---\left(1\right)$

The limit of this transfer function is positioned at

$s={\mathrm{\&epsiv;}}^{\frac{1}{N}}\&CenterDot;\exp \left(j\frac{2M+N-1}{2N}\mathrm{\&pi;}\right)M=\mathrm{1,2},\&CenterDot;\&CenterDot;\&CenterDot;,N---\left(2\right)$

K=R wherein _L/ (R _L+ R _S), N is 4 (exponent numbers of filter), ω _CBe respectively cut-off frequency and attenuation coefficient with ε.Fig. 5 represents the figure of this transfer function, significantly, is being lower than ω _CPassband in have maximally-flat and linear phase response.Fig. 6 represents one 4 notch cuttype inductor-capacitor Bart pole location of low pass filter watt now.These 4 limits are positioned at ω _CUnit circle on, on left half-plane, equi-spaced apart is arranged.ω _CBe L ₁-C ₃-C ₄The frequency of oscillation of network.In order to produce Bart's watt frequency response now, the standard value of assembly (that is inductance, electric capacity and resistance) is shown in the table 1.

Table 1

Fig. 7 represents a pair of concatenation type distributed amplifier, and each concatenation type distributed amplifier has ladder type inductor-capacitor network as load, and has output V _mCapacitor C ₃Be Metal-oxide-semicondutor pipe (hereinafter to be referred as metal-oxide-semiconductor) M _G1Or M _G2Drain electrode-base stage (drain-to-bulk) parasitic capacitance, capacitor C ₄Be metal-oxide-semiconductor M _G3Or M _G4The gate-to-source parasitic capacitance.Inductance L ₂The inductance coefficent increase can introduce the inductance loss that more gains are produced with the compensating signal path.The small-signal model of the serial connection amplifier of Fig. 8 presentation graphs 7.Inductor-capacitor network 60 comprises capacitor C ₃And inductance L ₁, be coupled to Control current source I _S(also can be expressed as from metal-oxide-semiconductor M _G1/ M _G2The amplifying signal that comes).Inductor-capacitor network 62 comprises capacitor C ₄And inductance L ₂, be coupled in after the inductor-capacitor network 60.Node V _mConnect inductor- capacitor network 60 and 62, output signal to back level concatenation type distributed amplifier (comprising another ladder type inductor-capacitor low pass filter).The output impedance frequency response of the small-signal module of Fig. 8 can be expressed as following formula:

$\frac{V_1}{I_s}\left(s\right)=\frac{{\mathrm{<figure-callout\; id="2"\; label="sL"\; filenames="C200710139029E00161.png,C200710139029E00171.png"\; state="\{\{state\}\}">sL</figure-callout>}}_2+R_L}{s^4{L}_1{L}_2{C}_3{\mathrm{<figure-callout\; id="4"\; label="C"\; filenames="C200710139029E00181.png,C200710139029E00202.png"\; state="\{\{state\}\}">C</figure-callout>}}_4+s^3{R}_L{L}_1{C}_3{\mathrm{<figure-callout\; id="4"\; label="C"\; filenames="C200710139029E00181.png,C200710139029E00202.png"\; state="\{\{state\}\}">C</figure-callout>}}_4+s^2(L_1{\mathrm{<figure-callout\; id="3"\; label="C"\; filenames="C200710139029E00171.png,C200710139029E00191.png"\; state="\{\{state\}\}">C</figure-callout>}}_3+L_2{\mathrm{<figure-callout\; id="4"\; label="C"\; filenames="C200710139029E00181.png,C200710139029E00202.png"\; state="\{\{state\}\}">C</figure-callout>}}_4+C_3{C}_4)+s{R}_L({\mathrm{<figure-callout\; id="3"\; label="C"\; filenames="C200710139029E00171.png,C200710139029E00191.png"\; state="\{\{state\}\}">C</figure-callout>}}_3+C_4)+1}---\left(3\right)$

In order to obtain Bart's watt response now, R _LSet for

$R_L=\sqrt{\frac{L_1}{({\mathrm{<figure-callout\; id="3"\; label="C"\; filenames="C200710139029E00171.png,C200710139029E00191.png"\; state="\{\{state\}\}">C</figure-callout>}}_3+C_4)/2}}---\left(4\right)$

As transistor M _G3And M _G4Capacitor C _GDWhen producing Miller enlarge-effect (Miller effect), C ₄Will be greater than C ₃In frequencies omega _COn, can produce gain peak overshooting (gain peak), its size as following formula:

$\left|\frac{V_1}{I_S}(s=j{\mathrm{\&omega;}}_C)\right|=\frac{C_4}{{\mathrm{<figure-callout\; id="3"\; label="C"\; filenames="C200710139029E00171.png,C200710139029E00191.png"\; state="\{\{state\}\}">C</figure-callout>}}_3}\&times;\sqrt{{\mathrm{<figure-callout\; id="2"\; label="R\; L"\; filenames="C200710139029E00161.png,C200710139029E00171.png"\; state="\{\{state\}\}">R</figure-callout>}}_L^{}+{\mathrm{\&omega;}}_C^2{\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="C200710139029E00161.png,C200710139029E00171.png"\; state="\{\{state\}\}">L</figure-callout>}}_2^2}---\left(5\right)$

For instance, if C ₄=2*C ₃, L ₁=2*L ₂, then can obtain output impedance frequency response as shown in Figure 9, show that available three dB bandwidth is extending nearly about 3.8 times, wherein ω _CBe L ₁-C ₃-C ₄The frequency of oscillation of network.Relatively, parallel connection and series inductance overshooting technology are at ω _CGain loss be:

$\left|\frac{V_1}{I_S}(s=j{\mathrm{\&omega;}}_C)\right|=\frac{C_3}{{\mathrm{<figure-callout\; id="4"\; label="C"\; filenames="C200710139029E00181.png,C200710139029E00202.png"\; state="\{\{state\}\}">C</figure-callout>}}_4}\&times;\sqrt{{\mathrm{<figure-callout\; id="2"\; label="R\; L"\; filenames="C200710139029E00161.png,C200710139029E00171.png"\; state="\{\{state\}\}">R</figure-callout>}}_L^{}+{\mathrm{\&omega;}}_C^2{\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="C200710139029E00161.png,C200710139029E00171.png"\; state="\{\{state\}\}">L</figure-callout>}}_2^2}---\left(6\right)$

Bandwidth extension multiplying power then significantly is contracted to 2.3 times.

At last, according to one embodiment of the invention, gain stage 44 is in conjunction with the concatenation type distributed amplifier, and the Bart is network watt now, transformer in active feedback and the sheet.Figure 10 represents the circuit framework of gain stage 44, comprises two differential amplifiers in conjunction with active feedback.

Constant current source I _S1Provide Dc bias to the first differential amplifier (to comprise a pair of metal-oxide-semiconductor M _G1And M _G2), and a pair of ladder type inductor-capacitor low pass filter (each comprises inductance L ₁, L ₂And resistance R _L).Similarly, constant current source I _S2Provide Dc bias to the second differential amplifier (to comprise a pair of metal-oxide-semiconductor M _G3And M _G4), and a pair of ladder type inductor-capacitor low pass filter (each comprises inductance L ₃, L ₄And resistance R _L).Second differential amplifier serial connection is to first differential amplifier.Though Figure 10 does not demonstrate any electric capacity, metal-oxide-semiconductor (M _G1-M _G6And the metal-oxide-semiconductor of subsequent gain level) can provide parasitic capacitance, as gate-to-source electric capacity and drain electrode-base capacity, supply ladder type inductor-capacitor low pass filter required component.For example, M in first differential amplifier _G1Drain electrode-base capacity and second differential amplifier in M _G3Gate-to-source electric capacity be two electric capacity of ladder type inductor-capacitor low pass filter.In addition, different with transmission line is, asymmetrical interior transformer 64 and 66 (that is L ₁=2*L ₂, L ₃=2 ^*L ₄) in order to reduce long distance consume and to help this differential layout.In order precisely to predict this transformer, the EM simulator can be used to obtain model accurately.

Active feedback framework 68 comprises metal-oxide-semiconductor M _G5And M _G6And current source I _S3, with the node V of second differential amplifier _mOutput signal negative feedback to the second differential amplifier (metal-oxide-semiconductor M _G3And M _G4) input.Useful is that active feedback framework 68 does not cause load to second differential amplifier and promotes the gain-bandwidth product of gain stage 44.

Simulation result shows that the gain that the framework of this embodiment provides is that 8dB and bandwidth are 35GHz.Gain-bandwidth product has been improved 3.8 times.Simultaneously, utilize the interior asymmetric transformer of sheet to save about 50% area, can obtain chip layout closely than traditional inductance.

Figure 11 is the schematic diagram of the output buffer stage 46 of Fig. 2, show sparrow upright-combination of brave cypress amplifier and characteristic frequency frequency multiplier (FT frequency multiplier).As is known to the person skilled in the art, sparrow is upright-and brave cypress amplifier is a differential amplifier, and two-stage and negative feedback framework that it has series connection are connected between the input and output of back level.Figure 11 represents the prime of differential amplifier, comprises metal-oxide-semiconductor M _B1And M _B2, and resistance R _B1M in the prime _B1And M _B2Grid in order to receive intermediate differential wave V from the gain stage 44 (Fig. 2) of afterbody _Im2The back level is the FT frequency multiplier, comprises metal-oxide-semiconductor M _B3And M _B4, M _B5And M _B6, resistance R _B2, and transformer L in a plurality of symmetrical matrix ₀The input of FT frequency multiplier is M _B3And M _B4Grid.The negative feedback framework has two resistance R _B2, each resistance R _B2Be connected between the input and output of FT frequency multiplier.Transformer L in each symmetrical matrix ₀Be connected to resistance R _B2Central contact, and symmetrical matrix in transformer L ₀An end be connected to resistance R _B1, the other end then produces output signal V _Out

The output buffer stage 46 of Figure 11 provides following several benefits.Use sparrow to stand-brave cypress amplifier in FT frequency multiplier front, can reduce capacitive load gain stage.Because the FT frequency multiplier uses big input transistors, its big input capacitance is alleviated by the resistance feedback path of Wei Li-brave cypress amplifier, and also can reduce in the time constant of internal node.Because transformer can be used to receive parasitic capacitance in the symmetrical matrix, output bandwidth thereby be extended.Single-ended and differential output amplitude design is at 300mVpp and 600m Vpp.

Figure 12 represents the simulation result of the output buffer stage 46 of Figure 11, points out arithmetic speed at 40Gb/s, and the cutting edge of a knife or a sword of 0.8ps is to the cutting edge of a knife or a sword disturbance, and differential amplitude 600m Vpp.

Limiting amplifier is manufactured in 0.13 micron CMOS processing procedure according to an embodiment of the invention.Figure 13 represents the frequency response of measured limiting amplifier, points out the differential gain S of the wide and 38dB of the band passband of 26.2GHz _DD21In 45GHz, input coupling S _DD11With output coupling S _DD22Respectively be lower than-7dB and-10dB, be enough to verify that this limiting amplifier can be operated in the working at high speed of 35Gb/s.

One embodiment of the present of invention provide the CMOS limiting amplifier of 35Gb/s, use the concatenation type distributed amplifier, and the Bart is network watt now, the interior transformer of active feedback and sheet, and can reach differential gain is that 38dB and bandwidth are 26.2GHz.With respect to other traditional amplifying circuit, it does not need high voltage, high flow rate power and huge chip area, therefore can have advantage at a high speed.

Input stage 42 can be in conjunction with the gain stage beyond this specification, output buffer stage and active feedback filter.Similarly, gain stage 44 or output buffer stage 46 also can be in conjunction with other assemblies in the limiting amplifier beyond this specification.

Claims (15)

1. limiting amplifier comprises:

Input stage can be carried out the direct voltage deviation and be eliminated, and receives differential input signal and exports the first intermediate differential wave;

A plurality of gain stages, above-mentioned gain stage serial connection is to amplify the above-mentioned first intermediate differential wave and to produce the second intermediate differential wave;

The output buffer stage is amplified the above-mentioned second intermediate differential wave and is produced output signal; And

Feedback filter provides direct voltage deviation to the above-mentioned input stage of above-mentioned output signal to eliminate in order to carry out the direct voltage deviation;

Wherein above-mentioned input stage comprises the resistor network that is coupled between input node and the power line, and above-mentioned resistor network comprises:

Shared resistance is coupled to said power;

Load resistance is coupled to the shared end points of above-mentioned shared resistance; And

Shunt resistance has two-end-point, is respectively coupled to above-mentioned load resistance.

2. limiting amplifier according to claim 1, it is characterized in that, above-mentioned input stage also comprises a pair of centre tap inductance, each centre tap inductance is coupled in the above-mentioned input node in the input node of centre tap inductance correspondence therewith and the above-mentioned load resistance therewith between the load resistance of centre tap inductance correspondence, and above-mentioned a pair of centre tap inductance provides central contact to export the above-mentioned first intermediate differential wave.

3. limiting amplifier according to claim 2 is characterized in that, each above-mentioned centre tap inductance is an interphase reactor transformer.

4. limiting amplifier according to claim 3 is characterized in that, each above-mentioned interphase reactor transformer is how much symmetries.

5. limiting amplifier according to claim 2 is characterized in that, above-mentioned output buffer stage has a pair of output node to produce above-mentioned output signal, and above-mentioned input stage comprises differential to the direct voltage deviation in order to the above-mentioned output signal of sensing.

6. limiting amplifier comprises:

Input stage can be carried out the direct voltage deviation and be eliminated, and receives differential input signal and exports the first intermediate differential wave;

A plurality of identical gain levels, serial connection is to amplify the above-mentioned first intermediate differential wave and to produce the second intermediate differential wave;

The output buffer stage is amplified the above-mentioned second intermediate differential wave to produce output signal; And

Feedback filter provides direct voltage deviation to the above-mentioned input stage of above-mentioned output signal to eliminate for the direct voltage deviation;

Wherein each above-mentioned gain stage comprises a pair of ladder type inductor-capacitor low pass filter, each above-mentioned ladder type inductor-capacitor low pass filter comprises that the first inductor-capacitor network is to receive amplifying signal, be connected to the second inductor-capacitor network of the above-mentioned first inductor-capacitor network, and the node of above-mentioned first, second inductor-capacitor network that is connected to prime ladder type inductor-capacitor low pass filter is to output signal to back level ladder type inductor-capacitor low pass filter.

7. limiting amplifier according to claim 6 is characterized in that, each above-mentioned gain stage comprises:

First amplifier has above-mentioned prime ladder type inductor-capacitor low pass filter;

Second amplifier has above-mentioned back level ladder type inductor-capacitor low pass filter; And

The active feedback framework, with the output signal negative feedback of above-mentioned second amplifier to above-mentioned second amplifier input terminal.

8. limiting amplifier according to claim 6 is characterized in that, first inductance in the above-mentioned first inductor-capacitor network and second inductance in the second inductor-capacitor network constitute transformer.

9. limiting amplifier according to claim 8 is characterized in that, above-mentioned transformer is an asymmetric interior transformer.

10. limiting amplifier according to claim 9 is characterized in that, the inductance ratio of above-mentioned first inductance and above-mentioned second inductance is 2.

11. limiting amplifier according to claim 6 is characterized in that, each gain stage comprises:

First amplifier comprises first MOS (metal-oxide-semiconductor) transistor, and above-mentioned first MOS (metal-oxide-semiconductor) transistor has drain electrode-base stage parasitic capacitance as first electric capacity that is arranged in above-mentioned prime ladder type inductor-capacitor low pass filter; And

Second amplifier comprises second MOS (metal-oxide-semiconductor) transistor, and above-mentioned second MOS (metal-oxide-semiconductor) transistor has the gate-to-source parasitic capacitance as second electric capacity that is arranged in above-mentioned prime ladder type inductor-capacitor low pass filter.

12. a limiting amplifier comprises:

Input stage can be carried out the direct voltage deviation and be eliminated, and receives differential input signal and exports the first intermediate differential wave;

A plurality of identical gain levels, serial connection is to amplify the above-mentioned first intermediate differential wave and to produce the second intermediate differential wave;

The output buffer stage is amplified the above-mentioned second intermediate differential wave and is produced output signal; And

Feedback filter provides direct voltage deviation to the above-mentioned input stage of above-mentioned output signal to eliminate in order to carry out the direct voltage deviation;

Wherein above-mentioned output buffer stage comprises:

Differential amplifier is as the input of above-mentioned output buffer stage;

The characteristic frequency frequency multiplier is connected serially to above-mentioned differential amplifier; And

The negative feedback framework is connected between the output and input of above-mentioned characteristic frequency frequency multiplier.

13. limiting amplifier according to claim 12 is characterized in that, above-mentioned negative feedback framework comprises resistance, is connected between the above-mentioned input of the above-mentioned output of above-mentioned characteristic frequency frequency multiplier and above-mentioned characteristic frequency frequency multiplier.

14. limiting amplifier according to claim 12, it is characterized in that, above-mentioned FT frequency multiplier comprises a pair of transformer, each above-mentioned transformer comprises the centre tap inductance, above-mentioned centre tap inductance has central contact and two-end-point, above-mentioned central contact is as the output of above-mentioned negative feedback framework, and one of above-mentioned two-end-point is connected to the ohmic load of above-mentioned characteristic frequency frequency multiplier, and another of above-mentioned two-end-point produces above-mentioned output signal.

15. limiting amplifier according to claim 14, it is characterized in that, each above-mentioned transformer has first inductance, above-mentioned first inductance is between one of above-mentioned two-end-point and above-mentioned central contact, and second inductance, above-mentioned second inductance is between another and above-mentioned central contact of above-mentioned two-end-point, and the inductance ratio of above-mentioned first inductance and above-mentioned second inductance is 1.

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