CN114696771A - Common mode transient interference suppression circuit and isolator - Google Patents
Common mode transient interference suppression circuit and isolator Download PDFInfo
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- CN114696771A CN114696771A CN202210249947.0A CN202210249947A CN114696771A CN 114696771 A CN114696771 A CN 114696771A CN 202210249947 A CN202210249947 A CN 202210249947A CN 114696771 A CN114696771 A CN 114696771A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/06—Frequency selective two-port networks including resistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/001—Details of arrangements applicable to more than one type of frequency demodulator
- H03D3/002—Modifications of demodulators to reduce interference by undesired signals
Abstract
The invention discloses a common mode transient interference suppression circuit and an isolator, wherein the common mode transient interference suppression circuit comprises: the common-mode detection circuit comprises a first-stage high-pass filter, a second-stage high-pass filter, a signal demodulation circuit and a common-mode detection circuit, wherein the first-stage high-pass filter, the second-stage high-pass filter, the signal demodulation circuit and the common-mode detection circuit are connected in series; the first-stage high-pass filter and the second-stage high-pass filter are used for sequentially filtering input signals of the signal receiving end, outputting differential signals and providing a current leakage channel when common-mode transient interference occurs; the common mode detection circuit is used for detecting the differential signal, generating a common mode transient detection result signal and outputting the common mode transient detection result signal to the signal demodulation circuit; and the signal demodulation circuit is used for demodulating the differential signal according to the common-mode transient detection result signal to obtain an original signal. The scheme of the invention can effectively inhibit the signal decoding abnormality caused by the common mode transient interference and improve the common mode transient interference resistance of the isolator.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a common-mode transient interference suppression circuit and an isolator.
Background
The isolator is an intermediate circuit between a signal output end and a signal receiving end, and is usually used for solving the problem of non-common ground at two sides of the isolator, so that circuits in different voltage domains can keep communication, and meanwhile, the circuits in different voltage domains can be prevented from mutual interference. When the reference ground on the isolator side is jittered, common mode glitches are generated, which may affect the accuracy of the isolated channel transmission signal.
The scheme for dealing with common mode transient interference in the conventional isolator is to use a differential structure and an ON-OFF Keying (OOK) encoding mode, and a schematic structural diagram of the conventional isolator is shown in fig. 1, the isolator mainly includes a transmitting circuit 1 and a receiving circuit 2, differential outputs of a signal modulation circuit 101 of the transmitting circuit 1 are respectively connected with an isolation capacitor Ciso1 and a Ciso3, the isolation capacitors Ciso2 and Ciso4 are connected with a node Vin1 and a node Vin2 of the receiving circuit 2, the node Vin1 is respectively connected with a capacitor C1 and a resistor R1, the node Vin2 is respectively connected with a capacitor C2 and a resistor R2, differential signals transmitted by the capacitor C1 and the capacitor C2 are respectively connected with input terminals VINN and VINP of a differential amplifier 102, and are respectively connected with resistors R3 and R4. When common-mode interference occurs between the signal transmitting terminal ground TGND and the signal receiving terminal ground RGND, the capacitors C1, C2 and the resistors R1, R2, R3, R4 play a role of reducing the common-mode interference, but since the common-mode input range of the differential structure is limited, when the common-mode interference is large, the input common-mode voltage of the differential amplifier 102 may exceed the input common-mode voltage range, resulting in an error of the transmission signal.
Disclosure of Invention
The embodiment of the invention provides a common mode transient interference suppression circuit and an isolator, which can effectively suppress signal decoding abnormity caused by common mode transient interference and improve the common mode transient interference resistance of the isolator.
The embodiment of the invention provides a common mode transient interference suppression circuit, which comprises: the common-mode detection circuit comprises a first-stage high-pass filter, a second-stage high-pass filter, a signal demodulation circuit and a common-mode detection circuit, wherein the first-stage high-pass filter, the second-stage high-pass filter, the signal demodulation circuit and the common-mode detection circuit are connected in series;
the first-stage high-pass filter and the second-stage high-pass filter are used for sequentially filtering input signals of a signal receiving end, outputting differential signals and providing a current discharge channel when common-mode transient interference occurs;
the common mode detection circuit is used for detecting the differential signal, generating a common mode transient detection result signal and outputting the common mode transient detection result signal to the signal demodulation circuit;
and the signal demodulation circuit is used for demodulating the differential signal according to the common-mode transient detection result signal to obtain an original signal.
Optionally, the common mode detection circuit comprises: the device comprises a current filling detection unit, a current pumping detection unit and a logic processing unit;
the current-pouring detection unit is used for detecting whether current is poured into the signal receiving end from the signal sending end and outputting a current-pouring detection result to the logic processing unit;
the current extraction detection unit is used for detecting whether current flows from the signal receiving terminal to the signal sending terminal and outputting a current extraction detection result to the logic processing unit;
and the logic processing unit is used for processing the current pouring detection result and the current pumping detection result and outputting the common-mode transient detection result signal.
Optionally, the signal demodulation circuit includes: a threshold adjusting unit, a signal demodulating unit and a buffer BUF1 which are connected in sequence;
the threshold adjusting unit is used for adjusting a demodulation threshold according to the common mode transient detection result signal;
the signal demodulation unit is used for demodulating the differential signal according to the adjusted demodulation threshold value to obtain an original signal;
the buffer BUF1 is used for converting the analog signal output by the signal demodulation unit into a digital signal and increasing the driving capability.
Optionally, the first stage high pass filter includes: the first isolation capacitor Ciso2 and the fourth isolation capacitor Ciso4 are connected in series, and the first resistor R1 and the second resistor R2 are connected in series; the upper pole plates of the second isolation capacitor Ciso2 and the fourth isolation capacitor Ciso4 are respectively connected with a signal sending end, the lower pole plate of the second isolation capacitor Ciso2 is simultaneously connected to one end of the first resistor R1 and the first input end of the common mode detection circuit, and the lower pole plate of the fourth isolation capacitor Ciso4 is simultaneously connected to one end of the second resistor R2 and the second input end of the common mode detection circuit; the common end of the first resistor R1 and the second resistor R2 is connected to the reference ground RGND of the signal receiving end;
the second stage high pass filter comprises: the first capacitor C1, the second capacitor C2, the third resistor R3 and the fourth resistor R4 which are connected in series; the upper electrode plates of the first capacitor C1 and the second capacitor C2 are respectively connected with the lower electrode plates of the second isolation capacitor Ciso2 and the fourth isolation capacitor Ciso4, the lower electrode plate of the first capacitor C1 is connected with one end of the third resistor R3, the lower electrode plate of the second capacitor C2 is connected with one end of the fourth resistor R4, and the common end of the third resistor R3 and the fourth resistor R4 is connected to the common mode level Vcm.
Optionally, the current draw detection unit includes: a pull-down current source I1, a first PMOS transistor P1 and a second PMOS transistor P2; a source electrode of the first PMOS transistor P1 and a source electrode of the second PMOS transistor P2 are respectively connected to a power supply VDD of the receiving circuit, a gate electrode of the first PMOS transistor P1 is connected to a first input end of the common mode detection circuit through a third capacitor C3 and is connected to the power supply VDD through a fifth resistor R5, a gate electrode of the second PMOS transistor P2 is connected to a second input end of the common mode detection circuit through a fifth capacitor C5 and is connected to the power supply VDD through a seventh resistor R7, a drain electrode of the first PMOS transistor P1 and a drain electrode of the second PMOS transistor P2 are respectively connected to the pull-down current source I1, and the pull-out current detection result is output;
the sink current detection unit includes: a pull-up current source I2, a first NMOS transistor N1 and a second NMOS transistor N2; the source of the first NMOS transistor N1 and the source of the second NMOS transistor N2 are respectively connected to the reference ground RGND of the receiving circuit, the gate of the first NMOS transistor N1 is connected to the first input terminal of the common mode detection circuit through a fourth capacitor C4 and is connected to the reference ground RGND of the receiving circuit through a sixth resistor R6, the gate of the second NMOS transistor N2 is connected to the second input terminal of the common mode detection circuit through a sixth capacitor C6 and is connected to the reference ground RGND of the receiving circuit through an eighth resistor R8, the drain of the first NMOS transistor N1 and the drain of the second NMOS transistor N2 are respectively connected to the pull-up current source I2, and the sink current detection result is output.
Optionally, the logic processing unit includes: a first inverter INV1 and an OR gate OR 1;
the output of the pull-down current source I1 is connected to one input terminal of an OR gate OR 1; the output of the pull-up current source I2 is connected to the input end of the first inverter INV1, and the output end of the first inverter INV1 is connected to the other input end of the OR gate OR 1; OR gate OR1 outputs the common mode transient detection result signal.
Optionally, the threshold adjusting unit includes: the second inverter INV2, the NOR gate NOR1, the AND gate AND1, the fifth NMOS transistor N703 AND the sixth NMOS transistor N702;
one input end of the AND gate AND1 is connected to the output end VOUT of the buffer BUF1, AND the other input end of the AND gate AND1 is connected to the output end of the common mode detection circuit;
the input end of the second inverter INV2 is connected to the output end of the common mode detection circuit;
one input end of the NOR gate NOR1 is connected to the output end of the buffer BUF1, and the other input end of the NOR gate NOR1 is connected to the output end of the second inverter INV 2;
the source of the fifth NMOS transistor N703 is connected to the first current source I701, the gate of the fifth NMOS transistor N703 is connected to the output terminal of the AND gate AND1, AND the drain of the fifth NMOS transistor N703 serves as an output terminal VON of the threshold adjustment unit;
the source of the sixth NMOS transistor N702 is connected to the second current source I702, the gate of the sixth NMOS transistor N702 is connected to the output terminal of the NOR gate NOR1, and the drain of the sixth NMOS transistor N702 serves as the other output terminal VO of the threshold adjustment unit.
Optionally, the signal demodulation unit includes: a third PMOS tube P700, a fourth PMOS tube P701, a third NMOS tube N700, a fourth NMOS tube N701, and a tail current source I703;
the source electrode of the third PMOS tube P700 and the source electrode of the fourth PMOS tube P701 are both connected with the power supply VDD, the drain electrode and the grid electrode of the third PMOS tube P700 are in short circuit connection with one output end VON of the threshold adjusting unit, the grid electrode of the fourth PMOS tube P701 is connected with one output end VON of the threshold adjusting unit, and the drain electrode of the fourth PMOS tube P701 is connected with the other output end VO of the threshold adjusting unit;
the source electrode of the third NMOS tube N700 and the source electrode of the fourth NMOS tube N701 are connected with a tail current source I703, and one end of the tail current source I703 is grounded; the gate of the third NMOS transistor N700 is used for inputting the differential signal, and the drain of the third NMOS transistor N700 is connected to an output terminal VON of the threshold adjustment unit; the grid electrode of the fourth NMOS tube N701 is used for inputting a demodulation threshold voltage Vref, and the drain electrode of the fourth NMOS tube N701 is connected to the other output end VO of the threshold adjusting unit;
an input of the buffer BUF1 is connected to the other output VO of the threshold adjustment unit.
Optionally, the third NMOS transistor N700 is composed of two NMOS structural units, and the gates of the two NMOS structural units are different, and the source and the drain are shorted to each other.
An embodiment of the present invention further provides an isolator, where the isolator includes: a transmission circuit 1 and a reception circuit 2; the transmitting circuit 1 comprises a signal modulation circuit, a first isolation capacitor Ciso1 and a third isolation capacitor Ciso3, wherein the output of the signal modulation circuit is respectively connected to the lower plates of the first isolation capacitor Ciso1 and the third isolation capacitor Ciso 3; the receiving circuit 2 comprises a common mode transient interference suppression circuit as claimed in any one of claims 1 to 9.
Optionally, the receiving circuit 2 further includes: a differential amplifier disposed between the second stage high pass filter and the signal demodulation circuit.
The common mode transient interference suppression circuit and the isolator provided by the embodiment of the invention have the advantages that the common mode transient interference detection circuit is arranged, and the common mode transient interference detection circuit respectively detects the currents generated by the positive and negative common mode transient interference, so that the common mode transient event can be distinguished from normal signal transmission, the common mode transient interference can be accurately detected, and meanwhile, the transmission of signals without the common mode transient interference is not influenced. When the common-mode transient interference is detected, the threshold voltage of the demodulation circuit is compensated, so that the equivalent threshold voltage follows the change trend of the signal, the signal decoding abnormity caused by the common-mode transient interference can be restrained, and the common-mode transient interference resistance of the isolator is improved.
Drawings
Fig. 1 is a schematic structural diagram of an isolator employing a differential structure in the prior art;
FIG. 2 is a diagram illustrating common mode transient interference and the resulting common mode current waveform in an isolator using a differential structure according to the prior art;
FIG. 3 is a schematic block diagram of a common mode transient interference suppression circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a specific structure of a common mode transient interference suppression circuit according to an embodiment of the present invention;
FIG. 5 is a functional block diagram of a common mode detection circuit in an embodiment of the present invention;
FIG. 6 is a schematic diagram of a specific structure of a common mode detection circuit according to an embodiment of the present invention;
FIG. 7 is a functional block diagram of a signal demodulation circuit in an embodiment of the present invention;
fig. 8 is a schematic diagram of a specific structure of a signal demodulation circuit according to an embodiment of the present invention;
fig. 9 is a flowchart of the operation of the signal demodulation circuit in the embodiment of the present invention;
FIG. 10 is a schematic diagram of a construction of an isolator according to an embodiment of the invention;
FIG. 11 is a diagram of a detection waveform of the common mode detection circuit according to the embodiment of the present invention;
FIG. 12 is a waveform diagram of a conventional isolator when subjected to a common mode transient;
figure 13 is a waveform diagram of an isolator according to an embodiment of the present invention when subjected to a common mode transient.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanying figures are described in detail below.
The following description sets forth numerous specific details, such as examples of specific systems, components, methods, etc., in order to provide a better understanding of several embodiments of the present invention. It will be apparent, however, to one skilled in the art that at least some embodiments of the invention may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are not presented in simple block diagram format in order to avoid unnecessarily obscuring the present invention. Accordingly, the specific details set forth are merely exemplary. Particular implementations may vary from these exemplary details and still be contemplated to be within the scope of the present invention.
For a capacitance isolation type isolator, when ground potentials on two sides of the isolator are transient, a voltage domain of a transmitting circuit or a receiving circuit is changed, so that voltage mutation occurs on two sides of an isolation capacitor, and a common-mode current I is generated at two ends of the isolation capacitorCMTAs shown in fig. 2, the common mode current ICMTIs calculated as follows:
during the rise of the signal transmitting terminal ground TGND, the generated current will flow from the transmitting circuit 1 to the receiving circuit 2 via the isolation capacitance, and during the fall of the signal transmitting terminal ground TGND, the generated current will flow from the receiving circuit 2 to the transmitting circuit 1, as shown in fig. 2.
For the traditional isolator adopting a differential structure, when the common-mode interference is large, errors occur in transmission signals, and therefore, the embodiment of the invention provides a common-mode transient interference suppression circuit and an isolator, wherein a common-mode detection circuit is added.
Fig. 3 is a schematic structural diagram of a common mode transient interference suppression circuit according to an embodiment of the invention.
The common mode transient interference suppression circuit comprises: a first stage high-pass filter 205, a second stage high-pass filter 206, a signal demodulation circuit 203, and a common mode detection circuit 204 disposed between the first stage high-pass filter 205 and the second stage high-pass filter 206. For convenience of description, one connection point of the common mode detection circuit 204 is labeled as Vin1, which will be referred to as the first input terminal Vin1 of the common mode detection circuit 204 in the following description, and the other connection point is labeled as Vin2, which will be referred to as the second input terminal Vin2 of the common mode detection circuit 204 in the following description. Wherein:
the first-stage high-pass filter 205 and the second-stage high-pass filter 206 are used for sequentially filtering input signals of a signal receiving end, outputting differential signals and providing a current leakage channel when common-mode transient interference occurs;
the common mode detection circuit 204 is configured to DETECT the differential signal, generate a common mode transient detection result signal CMT _ DETECT, and output the common mode transient detection result signal CMT _ DETECT to the signal demodulation circuit 203;
the signal demodulation circuit 203 is configured to demodulate the differential signal according to the common mode transient detection result signal to obtain an original signal.
Fig. 4 is a schematic diagram showing a specific structure of a common mode transient interference suppression circuit according to an embodiment of the present invention.
In this embodiment, the signal transmitting terminal transmits the differential output signal to the signal receiving terminal through the first and third isolation capacitors Ciso1 and Ciso3, the signal transmitting terminal ground is TGND, and the signal receiving terminal ground is RGND.
Referring to fig. 3 and 4 together, the first stage high pass filter 205 includes: the second isolation capacitor Ciso2, the fourth isolation capacitor Ciso4, the first resistor R1 and the second resistor R2 which are connected in series; the upper pole plates of the second isolation capacitor Ciso2 and the fourth isolation capacitor Ciso4 are respectively connected with the upper pole plates of the first isolation capacitor Ciso1 and the third isolation capacitor Ciso3 of the signal sending end, the lower pole plate of the second isolation capacitor Ciso2 is simultaneously connected to one end of the first resistor R1 and the first input terminal Vin1 of the common mode detection circuit 204, and the lower pole plate of the fourth isolation capacitor Ciso4 is simultaneously connected to one end of the second resistor R2 and the second input terminal Vin2 of the common mode detection circuit 204; the common terminal of the first resistor R1 and the second resistor R2 is connected to the reference ground RGND of the signal receiving terminal. The second stage high pass filter 206 includes: the first capacitor C1, the second capacitor C2, the third resistor R3 and the fourth resistor R4 which are connected in series; the upper electrode plates of the first capacitor C1 and the second capacitor C2 are respectively connected with the lower electrode plates of the second isolation capacitor Ciso2 and the fourth isolation capacitor Ciso4, the lower electrode plate of the first capacitor C1 is connected with one end of the third resistor R3, the lower electrode plate of the second capacitor C2 is connected with one end of the fourth resistor R4, and the common end of the third resistor R3 and the fourth resistor R4 is connected to the common mode level Vcm.
As shown in fig. 5, which is a schematic block diagram of a common mode detection circuit in an embodiment of the present invention, in this example, the common mode detection circuit 204 includes: a sink current detection unit 401, a drain current detection unit 402, and a logic processing unit 403. Wherein:
the sink current detection unit 401 is configured to detect whether a current is sunk from the signal sending end to the signal receiving end, and output a sink current detection result to the logic processing unit 403;
the pumping current detection unit 402 is configured to detect whether a current flows from the signal receiving terminal to the signal sending terminal, and output a pumping current detection result to the logic processing unit 403;
the logic processing unit 403 is configured to process the sink current detection result and the sink current detection result, and output the common mode transient detection result signal CMT _ DETECT.
Fig. 6 shows a specific structure diagram of the common mode detection circuit in the embodiment of the present invention.
Referring to fig. 5 and 6 together, the pumping current detection unit 402 includes: a pull-down current source I1, a first PMOS transistor P1 and a second PMOS transistor P2. The source of the first PMOS transistor P1 and the source of the second PMOS transistor P2 are respectively connected to a power supply VDD of the receiving circuit, the gate of the first PMOS transistor P1 is connected to the first input terminal Vin1 of the common mode detection circuit through a third capacitor C3 and is connected to the power supply VDD through a fifth resistor R5, the gate of the second PMOS transistor P2 is connected to the second input terminal Vin2 of the common mode detection circuit through a fifth capacitor C5 and is connected to the power supply VDD through a seventh resistor R7, and the drain of the first PMOS transistor P1 and the drain of the second PMOS transistor P2 are respectively connected to a pull-down current source I1 to output the pull-out current detection result.
With continued reference to fig. 5 and 6, the sink current detection unit 401 includes: a pull-up current source I2, a first NMOS transistor N1 and a second NMOS transistor N2. The source of the first NMOS transistor N1 and the source of the second NMOS transistor N2 are respectively connected to the reference ground RGND of the receiving circuit, the gate of the first NMOS transistor N1 is connected to the first input terminal Vin1 of the common mode detection circuit through a fourth capacitor C4 and is connected to the reference ground RGND of the receiving circuit through a sixth resistor R6, the gate of the second NMOS transistor N2 is connected to the second input terminal Vin2 of the common mode detection circuit through a sixth capacitor C6 and is connected to the reference ground RGND of the receiving circuit through an eighth resistor R8, and the drain of the first NMOS transistor N1 and the drain of the second NMOS transistor N2 are respectively connected to a pull-up current source I2 to output the sink current detection result.
As shown in fig. 6, the other terminal of the pull-down current source I1 is connected to the ground RGND, and the other terminal of the pull-up current source I2 is connected to the power supply VDD.
In fig. 6, I4 and I3 respectively represent the currents generated by the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the second NMOS transistor N2, where I4 and I3 are both 0 in the absence of common mode glitch, and I4 and I3 are not 0 in the presence of common mode glitch.
The pull-down current source I1 and the pull-up current source I2 correspond to two threshold values, and the potential at the node A, B depends on the magnitude relationship between I4 and I1 and between I2 and I3.
With continued reference to fig. 5 and 6, logical processing unit 403 includes: the first inverter INV1 and the OR gate OR 1. Wherein, the output of the pull-down current source I1 is connected to one input terminal of the OR gate OR 1; an output of the pull-up current source I2 is connected to an input end of the first inverter INV1, and an output end of the first inverter INV1 is connected to another input end of the OR gate OR 1; the OR gate OR1 outputs the common mode transient detection result signal CMT _ DETECT.
Fig. 7 is a schematic block diagram of a signal demodulation circuit according to an embodiment of the present invention;
the signal demodulation circuit 203 includes: a threshold adjusting unit, a signal demodulating unit, and a buffer BUF1, which are signal-connected in this order. Wherein:
the threshold adjusting unit 231 is configured to adjust a demodulation threshold according to the common mode transient detection result signal;
the signal demodulating unit 232 is configured to demodulate the differential signal according to the adjusted demodulation threshold to obtain an original signal;
the buffer BUF1 is configured to convert the analog signal output by the signal demodulation unit 232 into a digital signal and increase the driving capability.
Fig. 8 is a schematic diagram showing a specific structure of the signal demodulation circuit.
Referring to fig. 7 and 8 together, the threshold adjusting unit 231 includes: the second inverter INV2, the NOR gate NOR1, the AND gate AND1, AND the fifth NMOS transistor N703 AND the sixth NMOS transistor N702. One input end of the AND gate AND1 is connected to the output end of the buffer BUF1, the output signal of the buffer BUF1 is recorded as VOUT, AND the other input end of the AND gate AND1 is connected to the output end of the common mode detection circuit, that is, the common mode transient detection result signal CMT _ DETECT is input. An input end of the second inverter INV2 is connected to an output end of the common mode detection circuit, that is, the common mode transient detection result signal CMT _ DETECT is input. One input end of the NOR gate NOR1 is connected to the output end of the buffer BUF1, and the other input end of the NOR gate NOR1 is connected to the output end of the second inverter INV 2. The source of the fifth NMOS transistor N703 is connected to the first current source I701, the gate of the fifth NMOS transistor N703 is connected to the output terminal of the AND gate AND1, AND the drain of the fifth NMOS transistor N703 is used as an output terminal VON of the threshold adjustment unit 231. The source of the sixth NMOS transistor N702 is connected to the second current source I702, the gate of the sixth NMOS transistor N702 is connected to the output terminal of the NOR gate NOR1, and the drain of the sixth NMOS transistor N702 is used as the other output terminal VO of the threshold adjustment unit 231.
With continued reference to fig. 7 and 8, the signal demodulation unit 232 includes: a third PMOS transistor P700, a fourth PMOS transistor P701, a third NMOS transistor N700, a fourth NMOS transistor N701, and a tail current source I703. The source electrode of the third PMOS transistor P700 and the source electrode of the fourth PMOS transistor P701 are both connected to the power supply VDD, the drain electrode and the gate electrode of the third PMOS transistor P700 are shorted to one output terminal VON of the threshold adjusting unit 231, the gate electrode of the fourth PMOS transistor P701 is connected to one output terminal VON of the threshold adjusting unit 231, and the drain electrode of the fourth PMOS transistor P701 is connected to the other output terminal VO of the threshold adjusting unit 231. The source electrode of the third NMOS tube N700 and the source electrode of the fourth NMOS tube N701 are connected with a tail current source I703, and one end of the tail current source I703 is grounded; the gate of the third NMOS transistor N700 is used for inputting the differential signal Vsignal, and the drain of the third NMOS transistor N700 is connected to an output terminal VON of the threshold adjustment unit 231; the gate of the fourth NMOS transistor N701 is used to input the demodulation threshold voltage Vref, and the drain of the fourth NMOS transistor N701 is connected to the other output terminal VO of the threshold adjustment unit 231.
An input of the buffer BUF1 is connected to the other output VO of the threshold adjustment unit 231.
It should be noted that, in practical applications, the third NMOS transistor N700 may be composed of two NMOS structural units, and the gates of the two NMOS structural units are different, and the source and the drain are shorted with each other. Correspondingly, the differential signal Vsignal may also be formed by a set of differential signals, and respectively connected to the gate terminals of the two NMOS structural units forming the third NMOS transistor N700.
The operation of the signal demodulation circuit is described in detail below with reference to fig. 8.
When the common mode detection signal CMT _ DETECT output by the common mode detection circuit 204 is at a low level, the high level common mode detection signal CTRL _ H output through the AND gate AND1 AND the low level common mode detection signal CTRL _ L output through the second inverter NV2 AND the not gate NOR1 are both at a low level, so that the fifth NMOS transistor N703 AND the sixth NMOS transistor N702 are both in an off state. At this time, a core decoding comparator composed of a third NMOS transistor N700, a fourth NMOS transistor N701, a third PMOS transistor P700, a fourth PMOS transistor P701, and a tail current source I703 is not interfered. In this case, when the differential signal Vsignal is greater than the demodulation threshold voltage Vref, the node VO is high; when the differential signal Vsignal is less than the demodulation threshold voltage Vref, the node VO is low.
When the common mode detection signal CMT _ DETECT output by the common mode detection circuit 204 is at a high level, if the output signal VOUT of the buffer BUF1 is at a high level, the high-level common mode detection signal CTRL _ H is at a high level, the low-level common mode detection signal CTRL _ L is at a low level, at this time, the fifth NMOS transistor N703 is turned on, the first current source I701 provides an additional pull-down current source for the node VON, and as viewed from the output node, the first current source I701 generates a negative offset voltage superimposed on the demodulation threshold voltage Vref, so that Vref + Vos is lowered, where Vos represents an offset voltage, thereby making it more difficult for the output node VO of the core decoding comparator to invert to a low level. If the transmitted signal is inverted from high level to low level at this time, the comparator can still be inverted normally when the differential signal Vsignal is less than Vref + Vos. Therefore, the capability of resisting common mode transient interference when the signal demodulation circuit 203 transmits a high level is improved, and the output signal is not influenced to be turned into a low level due to the change of the input signal.
When the common mode detection signal CMT _ DETECT output by the common mode detection circuit 204 is at a high level, if the output signal VOUT of the buffer BUF1 is at a low level at this time, the common mode detection signal CTRL _ H is at a low level, the low-level common mode detection signal CTRL _ L is at a high level, at this time, the sixth NMOS tube N702 is turned on, the second current source I702 provides an additional pull-down current for the output node VO of the comparator, so that a larger pull-up current is required to pull up the node VO, the second current source I702 generates a positive offset voltage superimposed on the demodulation threshold voltage Vref, so that Vref + VOs is raised, and the output node VO of the comparator is more difficult to be inverted to a high level. If the transmitted signal is inverted from low level to high level at this time, the comparator can still be inverted normally when the differential signal Vsignal is greater than Vref + Vos. Therefore, the ability of the signal demodulation circuit 203 to resist common mode transient interference when transmitting low level is improved, and the output signal is not affected to be inverted to high level due to the change of the input signal.
The magnitude of the offset voltage is set by the first current source I701 and the second current source I702, and needs to be designed according to the matching degree and the gain of the differential amplifier in front of the signal demodulation circuit, and no fixed requirement is made.
Fig. 9 shows a flowchart of the operation of the signal demodulation circuit in the embodiment of the present invention, which includes the following steps:
in step 901, it is determined whether a common mode glitch is detected, i.e., whether the common mode detection signal CMT _ DETECT is at a high level. If so, go to step 902; otherwise, step 903 is executed.
In step 902, the decoding threshold is not compensated, i.e., the differential signal Vsignal is demodulated according to the demodulation threshold voltage Vref.
In step 903, it is determined whether the output signal VOUT of the buffer BUF1 is low. If so, go to step 904; otherwise, step 905 is performed.
In step 904, the low-level common-mode detection signal CTRL _ L is valid, i.e., at a high level, the sixth NMOS transistor N702 is turned on, the pull-down compensation is performed on the output node VO, the VOUT is maintained in a low-level state, the equivalent threshold voltage is raised, i.e., the differential signal Vsignal is demodulated according to the raised demodulation threshold voltage.
In step 905, the high-level common-mode detection signal CTRL _ H is valid, that is, at a high level, the fifth NMOS transistor N703 is turned on, the pull-down compensation is performed on the output node VON, the output nodes VO and VOUT are maintained in a high-level state, the equivalent threshold voltage is decreased, and the differential signal Vsignal is demodulated according to the decreased demodulation threshold voltage.
Correspondingly, an embodiment of the present invention further provides an isolator, as shown in fig. 10, which is a schematic structural diagram of the isolator.
The isolator includes: a transmission circuit 1 and a reception circuit 2. The transmitting circuit 1 comprises a signal modulation circuit 201, a first isolation capacitor Ciso1 and a third isolation capacitor Ciso3, wherein the output of the signal modulation circuit 201 is respectively connected to the lower plates of the first isolation capacitor Ciso1 and the third isolation capacitor Ciso 3; the receiving circuit 2 includes the common mode transient interference suppression circuit, and the upper plates of the second and fourth isolation capacitors Ciso2 and Ciso4 in the receiving circuit 2 are respectively connected to the upper plates of the first and third isolation capacitors Ciso1 and Ciso3 in the transmitting circuit 1.
Further, the receiving circuit 2 may further include: a differential Amplifier (AMP)202 provided between the second-stage high-pass filter and the signal demodulation circuit 203.
The working principle of the isolator provided by the embodiment is explained in the following with reference to fig. 10.
Referring to fig. 10, the signal modulation circuit 201 OOK-encodes the input signal IN, that is, outputs an OSC (Oscillator) signal during a period IN which the input signal IN is high, outputs a set of differential signals 180 ° out of phase to the first and third isolation capacitors Ciso1 and Ciso3 IN a differential configuration, and outputs a low signal during a period IN which the input signal IN is low. The differential signal passes through the first capacitor C1 and the second capacitor C2 and then is input to the input terminals VINN and VINP of the differential amplifier 202, and the common-mode voltage Vcm connected between the third resistor R3 and the fourth resistor R4 provides the input common-mode voltage required by the differential amplifier 202. The differential signal is amplified by the differential amplifier 202 and then input to the signal demodulation circuit 203, and the signal demodulation circuit 203 restores the original signal and outputs a signal VOUT.
The common mode detection circuit 204 determines whether common mode transient interference occurs by detecting whether the potentials of the node Vin1 and the node Vin2 have large sudden changes, outputs a common mode detection signal CMT _ DETECT to the signal demodulation circuit 203 when the common mode transient interference occurs, compensates the threshold voltage of the signal demodulation circuit 203, enables the equivalent threshold voltage to follow the change trend of the signal, and improves the common mode transient interference resistance of the signal demodulation circuit 203, so that signal decoding abnormality caused by the common mode transient interference can be suppressed, and the common mode transient interference resistance of the isolator can be improved.
Referring to fig. 5, when the common mode transient interference occurs, there are two states, i.e., the transmitting circuit 1 injects current into the receiving circuit 2 and the transmitting circuit 1 draws current from the receiving circuit 2, which correspond to two stages of rising and falling of TGND, respectively. The current pouring detection unit 401 and the current drawing detection unit 402 in the common mode detection circuit 204 are respectively used for detecting two states of current poured into and current drawn out from the receiving circuit 2 through the isolation capacitor, so that the detection of the rising edge and the falling edge of the TGND at the signal sending end can be realized, and the detection of the positive common mode transient interference and the negative common mode transient interference is realized. The logic processing unit 403 is used for integrating the output signals of the sink current detection unit 401 and the sink current detection unit 402, and outputting a final common mode detection signal CMT _ DETECT.
Fig. 11 shows a detection waveform diagram of the common mode detection circuit, and the operation of the common mode detection circuit will be described in detail with reference to fig. 5, 6, 10 and 11.
Referring to the detection waveform diagram of the common mode detection circuit shown in fig. 11:
when the forward common mode transient interference occurs at time T1, the common mode current generated by the common mode transient interference flows from the transmitting circuit 1 to the receiving circuit 2, the current flowing into the receiving circuit 2 is partially discharged through the first resistor R1 and the second resistor R2, and the voltages of the node Vin1 and the node Vin2 are raised, and the maximum voltages of the node Vin1 and the node Vin2 are ICMTR1, when the current flowing through the first capacitor C1 and the second capacitor C2 flows to the signal receiving terminal RGND through the third resistor R3 and the fourth resistor R4, the voltages at the two input terminals of the differential amplifier, i.e., the node VINN and the node VINP, are increased, so that the current flowing through the first capacitor C1 and the second capacitor C2 is decreased, the current flowing through the first resistor R1 and the second resistor R2 is gradually increased, and finally the voltages at the node Vin1 and the node Vin2 are gradually close to the maximum value ICMTR1, then most of the current generated by the common mode transient interference will flow into the receiving terminal ground RGND through the first resistor R1 and the second resistor R2.
When the common mode glitch is over at time T3, the current injected into the receiving circuit 2 gradually decreases, and the voltages at the node Vin1 and the node Vin2 gradually decrease to 0V.
When negative common mode transient interference occurs at time T5, the common mode current generated by the common mode transient interference flows from the receiving circuit 2 to the transmitting circuit 1, and the minimum value of the voltages at the node Vin1 and the node Vin2 is-ICMT*R1。
When the common mode glitch ends at time T7, the common mode current flowing from the receiving circuit 2 to the transmitting circuit 1 gradually decreases, and the voltages of the node Vin1 and the node Vin2 gradually increase to 0V, as shown in fig. 10.
From the above analysis and fig. 10, it can be seen that: when common mode transient interference occurs, the signals of the node Vin1 and the node Vin2 are approximately square waves and the pulse width is approximately the duration of the common mode transient interference, the time when the subsequent differential amplification circuit 202 and the signal demodulation circuit 203 are affected most is the time when a large current flows through the first capacitor C1 and the second capacitor C2, namely the time when the common mode transient interference starts and ends, and in the time period of the common mode transient interference, after the signals of the node Vin1 and the node Vin2 approach the maximum values, the current flowing through the first capacitor C1 and the second capacitor C2 is reduced, and the subsequent differential amplification circuit 202 and the signal demodulation circuit 203 are affected less.
When the forward common mode transient interference occurs, at the time T1 when the common mode transient interference starts, the node Vin1 and the node Vin2 are at the rising edge, and respectively drain the current to the signal receiving end ground RGND through the fourth capacitor C4 and the sixth resistor R6, and the sixth capacitor C6 and the eighth resistor R8, and when the current flowing through the sixth resistor R6 and the eighth resistor R8 causes the voltage drop to be larger than VthNThe pull-down current I3 is generated, and when I3 is larger than the reference current I2, the output node B is inverted from high level to low level, and a high level pulse continuing from the time T1 to the time T2 is generated in the output signal CMT _ DETECT. At time T3 when the common mode transient interference ends, Vin1 and Vin2 are at the falling edge, and the current is respectively drawn through capacitor C3 and resistor R5 and capacitor C5 and resistor R7, and when the voltage generated by the current coupled through C3 and C5 on resistor R5 and resistor R7 is greater than VthPWhen I4 is greater than the reference current I1, the pull-up current I4 is generated, and the output node a is inverted from low to high, and a high-level pulse lasting from the time T3 to the time T4 is generated in the output common mode detection signal CMT _ DETECT.
When negative common mode transient occurs, at time T5 when common mode transient starts, the node Vin1 and the node Vin2 are at the falling edge, and draw currents through the third capacitor C3 and the fifth resistor R5, and the fifth capacitor C5 and the seventh resistor R7, respectively, when the voltage drop caused by the currents flowing through the fifth resistor R5 and the seventh resistor R7 is greater than VthP, the pull-up current I4 is generated, and when the pull-up current I4 is greater than the reference current I1, the output node a is inverted from low level to high level, and a high level pulse lasting from time T5 to time T6 is generated on the output signal CMT _ ect. At time T7 when the common mode transient interference ends, the node Vin1 and the node Vin2 are at a rising edge, and respectively drain currents to the signal receiving end ground RGND through the fourth capacitor C4 and the sixth resistor R6, and the sixth capacitor C6 and the eighth resistor R8, when the voltage generated across the sixth resistor R6 and the eighth resistor R8 by the current coupled through the fourth capacitor C4 and the sixth capacitor C6 is greater than VthN, a pull-down current I3 is generated, and when the pull-down current I3 is greater than the reference current I2, the output node B is inverted from a high level to a low level, and a high level pulse lasting from time T7 to time T8 is generated on the output common mode detection signal CMT _ DETECT.
When no common mode transient interference occurs, no current passes through the coupling capacitor, the first PMOS transistor P1 and the second PMOS transistor P2, and the first NMOS transistor N1 and the second NMOS transistor N2 are all in an off state, no pull-up current I4 and no pull-down current I3 are generated, the reference current I1 pulls down the output node a to a low level, the reference current I2 pulls up the output node B to a high level, and the common mode detection signal CMT _ det output by the common mode detection circuit 204 is at a low level.
Fig. 12 is a waveform diagram of a conventional isolator when subjected to a common mode transient, and fig. 13 is a waveform diagram of an isolator according to an embodiment of the present invention when subjected to a common mode transient. The ability of the isolator provided by the embodiment of the present invention to resist common mode transient interference is further illustrated by comparing waveforms of the conventional isolator and the isolator provided by the embodiment of the present invention.
Referring to fig. 1 and 12, at time T1 to T4, the transmission signal is low, forward common mode glitch occurs at time T1 to T3, the transmitting circuit sinks current to the receiving circuit, the voltage of the node Vin1 and the node Vin2 rises at time T1 to T3 when the common mode glitch continues, and sinks or draws current to the common mode voltage Vcm through the capacitor C1 and the capacitor C2 at the time of the rising edge T1 and the falling edge T3 respectively, so that the common mode voltage of the input terminals VINN and VINP of the differential amplifying circuit rises at time T1, decreases beyond the input common mode voltage range of the differential amplifier circuit 202 at time T3, resulting in an error in the amplified signal, a jitter in the differential signal Vsignal, the demodulation threshold voltage Vref of the signal demodulation circuit is exceeded at times T1 to T2 and T3 to T4, so that the decoded output VOUT is erroneous, jumping from low to high.
At the time T4 to T5, although there is a difference in the ground potential between the two sides of the isolator, no sudden change occurs, no common mode current flows between the transmission circuit and the reception circuit, and the differential amplification circuit AMP202 of the reception circuit operates normally.
At times T5 to T8, the transmission signal is at a low level, negative common mode transient interference occurs at times T5 to T7, the transmission circuit draws current from the reception circuit, the voltages of the node Vin1 and the node Vin2 decrease at times T5 to T7 when the common mode transient interference continues, and the current is respectively drawn and injected to the common mode voltage Vcm through the capacitor C1 and the capacitor C2 at times T5 and T7 at falling edges, so that the common mode voltages at the input terminals VINN and VINP of the differential amplification circuit decrease at time T5, increase at time T7, exceed the input common mode voltage range of the differential amplification circuit, which causes an error in the amplified signal, the differential signal Vsignal jitters, and exceed the threshold voltage Vref of the signal demodulation circuit at times T5 to T6 and T7 to T8, which causes an error in the output VOUT of the signal demodulation circuit to flip to a high level from a low level.
At the time T9 to T12, the transmission signal is at a high level, the forward common mode transient interference occurs at the time T9 to T11, the transmitting circuit sinks current into the receiving circuit, the voltages of the node Vin1 and the node Vin2 rise at the time T9 to T11 when the common mode transient interference continues, and respectively sinks and draws current into the common mode voltage Vcm through the capacitor C1 and the capacitor C2 at the time of the rising edge T9 and at the time of the falling edge T11, so that the common mode voltage of the input terminals VINN and VINP of the differential amplifying circuit rises at time T9, at time T11, the voltage drops and exceeds the input common mode voltage range of the differential amplifier circuit, resulting in an error in the amplified signal, a smaller amplitude of the differential signal Vsignal input to the signal demodulation circuit, being lower than the demodulation threshold voltage Vref of the signal demodulation circuit at times T9 through T10 and at times T11 and T12, the output VOUT of the signal demodulation circuit is caused to be in error, and is inverted from high to low.
At the time T12 to T13, although the ground potentials on both sides of the isolator are different, no sudden change occurs, no common mode current flows between the transmitting circuit and the receiving circuit, and the differential amplifying circuit of the receiving circuit operates normally.
During the period from T13 to T16, the transmission signal is at a high level, negative common mode transient interference occurs at times from T13 to T15, the transmission circuit draws current from the reception circuit, the voltages of the node Vin1 and the node Vin2 decrease at times from T13 and T15 when the common mode transient interference continues, current is respectively drawn and sunk to the common mode voltage Vcm through the capacitor C1 and the capacitor C2 at the time of falling edge T13 and at the time of rising edge T15, so that the common mode voltages at the input terminals VINN and VINP of the differential amplification circuit decrease at time from T13, increase at time from T15, exceed the input common mode voltage range of the differential amplification circuit, and cause an error of the amplified signal, the differential signal Vsignal jitters, and are lower than the demodulation threshold voltage Vref of the signal demodulation circuit at times from T13 to T14 and from T15 to T16, which causes an error of the output VOUT of the signal demodulation circuit, and the output VOUT is inverted from a high level to a low level.
Referring to fig. 10 and 13, at times T1 to T4, the transmission signal is at a low level, forward common mode glitch occurs at times T1 to T3, the transmitting circuit 1 injects current into the receiving circuit 2, voltages of the node Vin1 and the node Vin2 rise at times T1 to T3 when the common mode glitch continues, and current is injected or extracted to the common mode voltage Vcm through the capacitor C1 and the capacitor C2 at times T1 and T3 respectively, so that the common mode voltages at the input terminals VINN and VINP of the differential amplifying circuit 202 rise at times T1, fall at times T3, exceed the input common mode voltage range of the differential amplifying circuit 202, cause an error in the amplified signal, the differential signal Vsignal jitters, and may exceed the threshold voltage Vref of the signal demodulating circuit 203 at times T1 to T2 and times T3 to T4. The common mode detection circuit 204 detects common mode transient interference in a time period from T1 to T4, outputs a high level pulse lasting to a time point T2 at a time point T1, and outputs a high level pulse lasting to a time point T4 at a time point T3, because the output VOUT of the signal demodulation circuit at the previous time point is at a low level, the high level common mode detection signal CTRL _ H outputs a low level, the low level common mode detection signal CTRL _ L is effective at time points T1 to T2 and T3 to T4, and outputs a high level, a positive offset voltage is generated to be superposed on the demodulation threshold voltage Vref, so that even if the differential signal Vsignal increases, the Vsignal < Vref + Vos can be satisfied, the node VO maintains a low level, and the output VOUT of the signal demodulation circuit maintains a low level.
At the time T4 to T5, although the ground potentials on both sides of the isolator are different, no sudden change occurs, no common mode current flows between the transmitting circuit and the receiving circuit, and the differential amplifying circuit 202 of the receiving circuit 2 operates normally.
At times T5 to T8, the transmission signal is at a low level, negative common mode transient interference occurs at times T5 to T7, the transmitting circuit 1 draws current from the receiving circuit 2, the voltages of the node Vin1 and the node Vin2 decrease at times T5 to T7 when the common mode transient interference continues, and current is drawn or injected to the common mode voltage Vcm through the capacitor C1 and the capacitor C2 at times T5 and T7 respectively, so that the common mode voltages at the input terminals VINN and VINP of the differential amplifying circuit 202 decrease at time T5, increase at time T7, exceed the input common mode voltage range of the differential amplifying circuit 202, and cause an error in the amplified signal, the differential signal Vsignal jitters, and may exceed the demodulation threshold voltage Vref of the signal demodulation circuit 203 at times T5 to T6 and T7 to T8. The common mode detection circuit 204 detects common mode transient interference in a time period from T5 to T8, outputs a high level pulse lasting to a time point T6 at a time point T5, outputs a high level pulse lasting to a time point T8 at a time point T7, outputs a low level of the high level common mode detection signal CTRL _ H because the output VOUT of the signal demodulation circuit at the previous time point is at a low level, outputs a high level when CTRL _ L is valid at a time point T5 to T6 and a time point T7 to T8, generates a positive offset voltage to be superimposed on the demodulation threshold voltage Vref, enables the differential signal Vsignal to satisfy Vsignal < Vref + Vos even if the differential signal Vsignal is increased, and maintains a low level at the node VO, thereby maintaining the output VOUT of the signal demodulation circuit at a low level.
At times T9 to T12, the transmission signal is at a high level, forward common mode transient interference occurs at times T9 to T11, the transmitting circuit 1 injects current into the receiving circuit 2, the voltages of the node Vin1 and the node Vin2 rise at times T9 to T11 when the common mode transient interference continues, and injects or extracts current to the common mode voltage Vcm through the capacitor C1 and the capacitor C2 at times T9 and T11 respectively, so that the common mode voltages of the input terminals VINN and VINP of the differential amplifying circuit 202 rise at times T9, fall at times T11, exceed the input common mode voltage range of the differential amplifying circuit 202, which causes an error in the amplified signal, the differential signal jitters, and may be lower than the demodulation threshold voltage Vref of the signal demodulating circuit 203 at times T9 to T10 and times T11 to T12. The common mode detection circuit 204 detects common mode transient interference in a time period from T9 to T12, outputs a high level pulse lasting to a time point T10 at a time point T9, and outputs a high level pulse lasting to a time point T12 at a time point T11, because the output VOUT of the signal demodulation circuit at the previous time point is high, the low level common mode detection signal CTRL _ L outputs a low level, the high level common mode detection signal CTRL _ H is effective at the time points T9 to T10 and T11 to T12, and outputs a high level, a negative offset voltage is generated to be superposed on the demodulation threshold voltage Vref, so that even if the differential signal Vsignal is reduced, the Vsignal > Vref + Vos can be satisfied, the node VO maintains a high level, and the output VOUT of the signal demodulation circuit maintains a high level.
At the time T12 to T13, although the ground potentials on both sides of the isolator are different, no sudden change occurs, no common mode current flows between the transmitting circuit and the receiving circuit, and the differential amplifying circuit 202 of the receiving circuit operates normally.
At times T13 to T16, the transmission signal is at a high level, negative common mode glitch occurs at times T13 to T15, the transmitting circuit 1 draws current from the receiving circuit 2, the voltages of the node Vin1 and the node Vin2 decrease at times T13 to T15 when the common mode glitch continues, and current is respectively drawn or injected to the common mode voltage Vcm through the capacitor C1 and the capacitor C2 at times T13 and T15 when the common mode glitch continues, so that the common mode voltages at the input terminals VINN and VINP of the differential amplifying circuit 202 decrease at time T13, increase at time T15, exceed the input common mode voltage range of the differential amplifying circuit 202, and cause an error in the amplified signal, the differential signal Vsignal jitters, and may be lower than the demodulation threshold voltage Vref of the signal demodulating circuit 203 at times T13 to T14 and T15 to T16. The common mode detection circuit 204 detects common mode transient interference in a time period from T13 to T15, outputs a high level pulse lasting to a time point T14 at a time point T13, and outputs a high level pulse lasting to a time point T16 at a time point T15, because the output VOUT of the signal demodulation circuit at the previous time point is high, the low level common mode detection signal CTRL _ L outputs a low level, the high level common mode detection signal CTRL _ H is effective at the time points T13 to T14 and T15 to T16, and outputs a high level, a negative offset voltage is generated to be superposed on the demodulation threshold voltage Vref, so that even if the differential signal Vsignal is reduced, the Vsignal > Vref + Vos can be satisfied, the node VO maintains a high level, and the output VOUT of the signal demodulation circuit maintains a high level.
As can be seen from the waveform diagrams of the two signals, in the isolator according to the embodiment of the present invention, the common mode transient interference detection circuit is provided, and the common mode transient interference detection circuit detects the currents generated by the positive and negative common mode transient interferences, so that the common mode transient event can be distinguished from the normal signal propagation, the common mode transient interference can be accurately detected, and the transmission of the signal without the common mode transient interference is not affected. When the common-mode transient interference is detected, the threshold voltage of the demodulation circuit is compensated, so that the equivalent threshold voltage follows the change trend of the signal, the signal decoding abnormity caused by the common-mode transient interference can be restrained, and the common-mode transient interference resistance of the isolator is improved.
It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein indicates that the former and latter associated objects are in an "or" relationship.
"plurality" appearing in the embodiments of the present invention means two or more.
The descriptions of the first, second, etc. appearing in the embodiments of the present invention are only for illustrating and differentiating the objects, and do not have any order or represent any special limitation to the number of devices in the embodiments of the present invention, and do not constitute any limitation to the embodiments of the present invention.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (11)
1. A common-mode transient interference suppression circuit, comprising: the common-mode detection circuit comprises a first-stage high-pass filter, a second-stage high-pass filter, a signal demodulation circuit and a common-mode detection circuit, wherein the first-stage high-pass filter, the second-stage high-pass filter, the signal demodulation circuit and the common-mode detection circuit are connected in series;
the first-stage high-pass filter and the second-stage high-pass filter are used for sequentially filtering input signals of a signal receiving end, outputting differential signals and providing a current discharge channel when common-mode transient interference occurs;
the common mode detection circuit is used for detecting the differential signal, generating a common mode transient detection result signal and outputting the common mode transient detection result signal to the signal demodulation circuit;
and the signal demodulation circuit is used for demodulating the differential signal according to the common-mode transient detection result signal to obtain an original signal.
2. A common-mode transient interference rejection circuit according to claim 1 wherein said common-mode detection circuit comprises: the device comprises a current filling detection unit, a current pumping detection unit and a logic processing unit;
the current-pouring detection unit is used for detecting whether current is poured into the signal receiving end from the signal sending end and outputting a current-pouring detection result to the logic processing unit;
the current extraction detection unit is used for detecting whether current flows from the signal receiving terminal to the signal sending terminal and outputting a current extraction detection result to the logic processing unit;
and the logic processing unit is used for processing the current pouring detection result and the current pumping detection result and outputting the common-mode transient detection result signal.
3. The common mode transient interference rejection circuit of claim 2, wherein said signal demodulation circuit comprises: a threshold adjusting unit, a signal demodulating unit, and a buffer (BUF1) which are connected in sequence;
the threshold adjusting unit is used for adjusting a demodulation threshold according to the common mode transient detection result signal;
the signal demodulation unit is used for demodulating the differential signal according to the adjusted demodulation threshold value to obtain an original signal;
the buffer (BUF1) is used for converting the analog signal output by the signal demodulation unit into a digital signal and increasing the driving capability.
4. A common-mode transient interference rejection circuit according to claim 3,
the first stage high pass filter includes: a second isolation capacitor (Ciso2) and a fourth isolation capacitor (Ciso4), a first resistor (R1) and a second resistor (R2) connected in series; the upper pole plates of a second isolation capacitor (Ciso2) and a fourth isolation capacitor (Ciso4) are respectively connected with a signal sending end, the lower pole plate of the second isolation capacitor (Ciso2) is simultaneously connected to one end of a first resistor (R1) and the first input end of the common mode detection circuit, and the lower pole plate of the fourth isolation capacitor (Ciso4) is simultaneously connected to one end of a second resistor (R2) and the second input end of the common mode detection circuit; the common end of the first resistor (R1) and the second resistor (R2) is connected to the Reference Ground (RGND) of the signal receiving end;
the second stage high pass filter comprises: a first capacitor (C1) and a second capacitor (C2), a third resistor (R3) and a fourth resistor (R4) which are connected in series; the upper electrode plates of the first capacitor (C1) and the second capacitor (C2) are respectively connected with the lower electrode plates of the second isolation capacitor (Ciso2) and the fourth isolation capacitor (Ciso4), the lower electrode plate of the first capacitor (C1) is connected with one end of the third resistor (R3), the lower electrode plate of the second capacitor (C2) is connected with one end of the fourth resistor (R4), and the common end of the third resistor (R3) and the fourth resistor (R4) is connected to the common mode level (Vcm).
5. A common-mode transient interference rejection circuit according to claim 4,
the current draw detection unit includes: the pull-down current source (I1), the first PMOS tube (P1) and the second PMOS tube (P2); a source electrode of the first PMOS tube (P1) and a source electrode of the second PMOS tube (P2) are respectively connected to a power supply (VDD) of the receiving circuit, a grid electrode of the first PMOS tube (P1) is connected with a first input end of the common mode detection circuit through a third capacitor (C3) and is connected to the power supply (VDD) through a fifth resistor (R5), a grid electrode of the second PMOS tube (P2) is connected with a second input end of the common mode detection circuit through a fifth capacitor (C5) and is connected to the power supply (VDD) through a seventh resistor (R7), a drain electrode of the first PMOS tube (P1) and a drain electrode of the second PMOS tube (P2) are respectively connected to the pull-down current source (I1), and the pull-out current detection result is output;
the sink current detection unit includes: the pull-up current source (I2), the first NMOS transistor (N1) and the second NMOS transistor (N2); the source electrode of the first NMOS tube (N1) and the source electrode of the second NMOS tube (N2) are respectively connected to a Reference Ground (RGND) of the receiving circuit, the grid electrode of the first NMOS tube (N1) is connected with the first input end of the common mode detection circuit through a fourth capacitor (C4) and is connected to the Reference Ground (RGND) of the receiving circuit through a sixth resistor (R6), the grid electrode of the second NMOS tube (N2) is connected with the second input end of the common mode detection circuit through a sixth capacitor (C6) and is connected to the Reference Ground (RGND) of the receiving circuit through an eighth resistor (R8), the drain electrode of the first NMOS tube (N1) and the drain electrode of the second NMOS tube (N2) are respectively connected to the pull-up current source (I2), and the sink current detection result is output.
6. The common mode transient interference rejection circuit of claim 5, wherein said logic processing unit comprises: a first inverter (INV1) and an OR gate (OR 1);
the output of the pull-down current source (I1) is connected to one input of an OR gate (OR 1); the output of the pull-up current source (I2) is connected to the input end of a first inverter (INV1), and the output end of the first inverter (INV1) is connected to the other input end of the OR gate (OR 1); an OR gate (OR1) outputs the common mode transient detection result signal.
7. A common-mode transient interference rejection circuit according to claim 6, wherein said threshold adjustment unit comprises: the second inverter (INV2), the NOR gate (NOR1), the AND gate (AND1), the fifth NMOS transistor (N703) AND the sixth NMOS transistor (N702);
one input end of the AND gate (AND1) is connected with the output end (VOUT) of the buffer (BUF1), AND the other input end of the AND gate (AND1) is connected with the output end of the common mode detection circuit;
the input end of the second inverter (INV2) is connected with the output end of the common mode detection circuit;
one input end of the NOR gate (NOR1) is connected with the output end of the buffer (BUF1), and the other input end of the NOR gate (NOR1) is connected with the output end of the second inverter (INV 2);
the source electrode of the fifth NMOS tube (N703) is connected with the first current source (I701), the grid electrode of the fifth NMOS tube (N703) is connected with the output end of the AND gate (AND1), AND the drain electrode of the fifth NMOS tube (N703) is used as one output end (VON) of the threshold adjusting unit;
the source of the sixth NMOS transistor (N702) is connected with the second current source (I702), the gate of the sixth NMOS transistor (N702) is connected with the output end of the NOR gate (NOR1), and the drain of the sixth NMOS transistor (N702) is used as the other output end (VO) of the threshold adjusting unit.
8. The common mode transient interference rejection circuit of claim 6, wherein said signal demodulation unit comprises: the device comprises a third PMOS tube (P700), a fourth PMOS tube (P701), a third NMOS tube (N700), a fourth NMOS tube (N701) and a tail current source (I703);
the source electrode of the third PMOS tube (P700) and the source electrode of the fourth PMOS tube (P701) are both connected with the power supply (VDD), the drain electrode and the grid electrode of the third PMOS tube (P700) are in short circuit with one output end (VON) of the threshold adjusting unit, the grid electrode of the fourth PMOS tube (P701) is connected with one output end (VON) of the threshold adjusting unit, and the drain electrode of the fourth PMOS tube (P701) is connected with the other output end (VO) of the threshold adjusting unit;
the source electrode of the third NMOS tube (N700) and the source electrode of the fourth NMOS tube (N701) are connected with a tail current source (I703), and one end of the tail current source (I703) is grounded; the grid electrode of the third NMOS tube (N700) is used for inputting the differential signal, and the drain electrode of the third NMOS tube (N700) is connected to one output end (VON) of the threshold value adjusting unit; the grid electrode of the fourth NMOS tube (N701) is used for inputting a demodulation threshold voltage (Vref), and the drain electrode of the fourth NMOS tube (N701) is connected to the other output end (VO) of the threshold adjusting unit;
an input of the buffer (BUF1) is connected to the other output (VO) of the threshold adjustment unit.
9. The common mode transient interference suppression circuit of claim 8, wherein the third NMOS transistor (N700) is composed of two NMOS structural units, and the two NMOS structural units have different gates and short-circuited sources and drains.
10. An isolator, comprising: a transmission circuit (1) and a reception circuit (2); the transmitting circuit (1) comprises a signal modulation circuit, a first isolation capacitor (Ciso1) and a third isolation capacitor (Ciso3), wherein the outputs of the signal modulation circuit are respectively connected to the lower plates of the first isolation capacitor (Ciso1) and the third isolation capacitor (Ciso 3); the receiving circuit (2) comprises a common mode transient interference suppression circuit according to any of claims 1 to 9.
11. The isolator according to claim 10, wherein the receiving circuit 2 further comprises: a differential amplifier disposed between the second stage high pass filter and the signal demodulation circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210249947.0A CN114696771A (en) | 2022-03-14 | 2022-03-14 | Common mode transient interference suppression circuit and isolator |
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| CN202210249947.0A CN114696771A (en) | 2022-03-14 | 2022-03-14 | Common mode transient interference suppression circuit and isolator |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115314069A (en) * | 2022-08-08 | 2022-11-08 | 慷智集成电路(上海)有限公司 | Full-duplex transmitting and receiving circuit, deserializing circuit chip, electronic equipment and vehicle |
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2022
- 2022-03-14 CN CN202210249947.0A patent/CN114696771A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115314069A (en) * | 2022-08-08 | 2022-11-08 | 慷智集成电路(上海)有限公司 | Full-duplex transmitting and receiving circuit, deserializing circuit chip, electronic equipment and vehicle |
| CN115314069B (en) * | 2022-08-08 | 2023-10-13 | 慷智集成电路(上海)有限公司 | Full duplex transmitting and receiving circuit, deserializing circuit chip, electronic equipment and vehicle |
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