CN115932363B - Offset voltage adjustable high-side current detection circuit - Google Patents
Offset voltage adjustable high-side current detection circuit Download PDFInfo
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- CN115932363B CN115932363B CN202211626862.6A CN202211626862A CN115932363B CN 115932363 B CN115932363 B CN 115932363B CN 202211626862 A CN202211626862 A CN 202211626862A CN 115932363 B CN115932363 B CN 115932363B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a high-side current detection circuit with adjustable offset voltage, which comprises: a sampling circuit (100) for providing a sampling voltage; a voltage sampling amplifying circuit (101) connected to the sampling circuit (100) for amplifying a sampling voltage; and the filter circuit (102) is connected with the voltage sampling amplifying circuit (101) and is used for filtering high-frequency noise. The detection circuit provided by the invention is convenient for subtracting the determined offset voltage when the ADC of the MCU samples the output signal of the current detection circuit by setting the offset voltage determined by a numerical value, so that the influence of the random offset voltage on the detection precision is reduced. Meanwhile, the determined offset voltage and the voltage gain of the current detection circuit can be adjusted according to the MCU requirement, so that the current detection precision of the power driving chip is improved.
Description
Technical Field
The invention belongs to the technical field of wireless charging in an analog integrated circuit, and particularly relates to a high-side current detection circuit with adjustable offset voltage.
Background
Current detection circuits play a critical role in analog applications such as high-efficiency current-mode power management chips or other power electronics. For the wireless charging system of low-power equipment widely applied at present, the foreign matter detection function is a technical detection means for avoiding overhigh system temperature rise caused by foreign matters in the wireless charging process.
The wireless charging is different from the wired charging, the latter can work after being physically hard-connected, and the wireless charging connects two independent objects through a magnetic field, so that foreign matters such as a metal conductor and the like possibly exist in a path, induced electromotive force can be excited in an alternating magnetic field, induced current is formed inside the metal conductor, and at the moment, the metal is equivalent to a resistor, thereby generating high heat and causing harm. Foreign object detection techniques are therefore essential and quite important in wireless charging applications. The foreign matter detection function in the wireless charging system can be realized by detecting power loss, namely detecting the power difference between the power transmitting end and the power receiving end, and triggering the foreign matter detection function to stop power transmission when the power difference is larger than a set threshold value.
In order to improve the power detection efficiency of the power transmitting terminal and the power receiving terminal, a current detection circuit is generally integrated in the driving chips of the power transmitting terminal and the power receiving terminal. The detection of power loss is completed by detecting the current consumed by the driving chip in real time, so that the foreign matter detection function of wireless charging is realized, and the safety and reliability of wireless charging are improved.
The current detection circuit of the common driving chip is divided into a high-side current detection circuit and a low-side current detection circuit. The position of the low-side current detection circuit detection resistor is between the load and the ground, and the reference point of the load changes along with the load current, so that the stability of the system is affected. Noise immunity is poor. When the load is short-circuited, the current detection function fails. The position of the high-side current detection circuit detection resistor is between the power supply and the load, the detection resistor is close to the power supply, the interference from the ground to the power supply can be avoided, and the stability is good. However, the high-side current detection circuit needs a wide common-mode input voltage range, and the detection accuracy is greatly affected by offset voltage.
Disclosure of Invention
In order to solve the problems that the existing high-side current detection circuit needs a wide common-mode input voltage range and the detection accuracy is greatly influenced by offset voltage, the invention provides the high-side current detection circuit with adjustable offset voltage. Meanwhile, the determined offset voltage and the voltage gain of the current detection circuit can be adjusted according to the MCU requirement, so that the current detection precision of the power driving chip is improved.
In order to achieve the above object, the present invention provides the following solutions: a high-side current detection circuit with an adjustable offset voltage, comprising:
a sampling circuit for providing a sampling voltage;
the voltage sampling amplifying circuit is connected with the sampling circuit and is used for amplifying the sampling voltage;
and the filter circuit is connected with the voltage sampling amplifying circuit and is used for filtering high-frequency noise.
Preferably, the sampling circuit comprises a sixth resistor, a first power supply and a load;
one end of the sixth resistor is connected with the first power supply, and the other end of the sixth resistor is grounded through a load.
Preferably, the voltage sampling amplifying circuit comprises a current mirror circuit, a first resistor, a second resistor, a switching resistor and a first NMOS tube;
the positive input end of the current mirror circuit is connected to the positive electrode of the sixth resistor through the first resistor, the reverse input end of the current mirror circuit is connected to the negative electrode of the sixth resistor through the second resistor, the output end of the current mirror circuit is connected to the positive electrode of the conversion resistor through the first NMOS tube, and the negative electrode of the conversion resistor is grounded;
the drain end of the first NMOS tube is connected with the negative electrode of the first resistor, the grid electrode of the first NMOS tube is connected with the output end of the current mirror circuit, and the source end of the first NMOS tube is connected with the positive electrode of the switching resistor.
Preferably, the filter circuit comprises a fourth resistor, a fifth resistor, a first capacitor and a second capacitor;
the positive pole of the fifth resistor is connected with the positive pole of the conversion resistor through the fourth resistor, the negative pole of the fifth resistor is connected with the total output end, one end of the first capacitor is connected with the positive pole of the fifth resistor and the negative pole of the fourth resistor, and the other end of the first capacitor is grounded. One end of the second capacitor is connected with the negative electrode and the total output end of the fifth resistor, and the other end of the second capacitor is grounded.
Preferably, the current mirror circuit comprises a first current mirror;
the first current mirror comprises a first PMOS (P-channel metal oxide semiconductor) transistor, a second PMOS transistor, a third PMOS transistor, a first PNP transistor, a second PNP transistor, a third PNP transistor and a fourth PNP transistor;
the emitter of the first PNP transistor and the emitter of the second PNP transistor are respectively connected with the cathode of the second resistor;
the emitter of the third PNP transistor and the emitter of the fourth PNP transistor are respectively connected with the cathode of the first resistor;
the base electrode of the first PNP transistor, the collector electrode of the first PNP transistor, the base electrode of the second PNP transistor, the base electrode of the third PNP transistor, the base electrode of the fourth PNP transistor and the collector electrode of the fourth PNP transistor are connected to the source end of the first PMOS transistor;
the collector electrode of the second PNP transistor is connected with the source end of the second PMOS transistor;
the collector electrode of the third PNP transistor is connected with the source end of the third PMOS transistor;
the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are connected with the drain end of the first PMOS tube.
Preferably, the current mirror circuit further comprises a second current mirror;
the second current mirror comprises a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a second power supply;
the drain end of the fifth NMOS tube is connected with the drain end of the first PMOS tube;
the source end of the fifth NMOS tube is connected with the drain end of the fourth NMOS tube;
the source end of the third NMOS tube is connected with the drain end of the second NMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fourth NMOS tube;
the drain end of the third NMOS tube, the grid electrode of the third NMOS tube and the grid electrode of the fifth NMOS tube are connected with a second power supply, and the current provided by the second power supply is equal to the collector current of the first PNP transistor;
and the source end of the second NMOS tube and the source end of the fourth NMOS tube are grounded.
Preferably, the current mirror circuit further comprises a third current mirror;
the third current mirror comprises a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube and a ninth NMOS tube;
the drain end of the ninth NMOS tube is connected with the drain end of the third PMOS tube;
the source end of the ninth NMOS tube is connected with the drain end of the eighth NMOS tube;
the grid electrode of the seventh NMOS tube, the drain end of the seventh NMOS tube and the grid electrode of the ninth NMOS tube are connected with the drain end of the second PMOS tube;
the drain end of the sixth NMOS tube, the grid electrode of the sixth NMOS tube and the grid electrode of the eighth NMOS tube are connected with the source end of the seventh NMOS tube;
and the source end of the sixth NMOS tube and the source end of the eighth NMOS tube are grounded.
The invention discloses the following technical effects:
(1) The circuit has simple structure and is easy to integrate; (2) The voltage gain and offset voltage can be changed by adjusting the resistors R1, R2 and R3 so as to match different MCU, thereby improving the detection precision; (3) The emitter of PNP transistor is used as the input end of voltage sampling signal, and the P channel field effect transistor with high voltage resistance is arranged below the emitter to form a current mirror with a common-source common-gate structure, so that the current replication precision is improved; the high-voltage-resistant P-channel field effect transistor can bear higher common-mode voltage, and the common-mode input voltage range is expanded; (4) The cascoded current mirror formed by PNP type transistors has the characteristic of high response speed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a functional block diagram of a high-side current detection circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the hardware of a high-side current detection circuit according to an embodiment of the present invention;
in the figure: 100-sampling circuit, 101-voltage sampling amplifying circuit, 102-filter circuit, 201-current mirror circuit, R1-first resistor, R2-second resistor, R3-converting resistor, R4-fourth resistor, R5-fifth resistor, rs-sixth resistor, RL-load, vdd-first power supply, IQ-second power supply, vout-total output end, C1-first capacitor, C2-second capacitor, NM 1-first NMOS transistor, NM 2-second NMOS transistor, NM 3-third NMOS transistor, NM 4-fourth NMOS transistor, NM 5-fifth NMOS transistor, NM 6-sixth NMOS transistor, NM 7-seventh NMOS transistor, NM 8-eighth NMOS transistor, NM 9-ninth NMOS transistor, PM 1-first PMOS transistor, PM 2-second PMOS transistor, PM 3-third PMOS transistor, Q1-first PNP transistor, Q2-second PNP transistor, Q3-third PNP transistor, Q4-fourth PNP transistor.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
As shown in fig. 1-2, the high-side current detection circuit with adjustable offset voltage provided by the invention comprises a sampling circuit 100, a voltage sampling amplifying circuit 101 and a filter circuit 102.
One end of a sixth resistor Rs in the sampling circuit 100 is connected with the high-side power supply VDD and the positive input end of the voltage sampling amplifying circuit 101 at the same time, and the other end of the sixth resistor Rs is connected with the negative input end of the load and the voltage sampling amplifying circuit 101 at the same time. The output of the voltage sampling amplifying circuit 101 is connected to the input of the filtering circuit 102. The output Vout voltage of the filter circuit 102 is used as the output signal of the high-side current detection circuit.
The voltage sampling amplifying circuit 101 includes a first resistor R1, a second resistor R2, a current mirror circuit 201, a first NMOS transistor NM1, and a switching resistor R3.
One end of the first resistor R1 is connected to the high-side power supply VDD and the sixth resistor Rs, and the other end of the first resistor R1 is connected to the positive input end of the current mirror circuit 201. One end of the second resistor R2 is connected to the load and the sixth resistor Rs, and the other end of the first resistor R1 is connected to the negative input terminal of the current mirror circuit 201. The output of the current mirror circuit 201 is connected to the gate end of the first NMOS tube NM1, the drain end of the first NMOS tube NM1 is connected to the positive input end of the current mirror circuit 201, and the source end of the first NMOS tube NM1 is connected to one end of the switching resistor R3. The other end of the switching resistor R3 is grounded.
The filter circuit 102 includes a fourth resistor R4, a fifth resistor R5, a first capacitor C1, and a second capacitor C2. R4, R5, C1 and C2 form a second-order low-pass filter, and the filter circuit 102 can filter high-frequency noise of the output signal of the voltage sampling amplifying circuit 101, reduce high-frequency noise interference and improve detection accuracy.
The current mirror circuit 201, as shown in fig. 2, includes a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a first PNP transistor Q1, a second PNP transistor Q2, a third PNP transistor Q3, and a fourth PNP transistor Q4.
Further, NM2, NM3, NM4, NM5 form a group of cascode current mirrors, NM6, NM7, NM8, NM9 form another group of cascode current mirrors, and Q1, Q2, Q3, Q4, PM1, PM2, PM3 form another group of cascode current mirrors.
Further, the working principle of the high-side current detection circuit is as follows:
the sampling resistor Rs is used for collecting the current flowing through the load, generating a voltage difference Vsense on the sampling resistor Rs, and the voltage sampling amplifying circuit 101 is used for collecting the voltage Vsense on the sampling resistor Rs, amplifying the voltage by a certain multiple and then outputting the amplified voltage. The filter circuit 102 is used for filtering high-frequency noise and improving the anti-interference capability of the current detection circuit.
The voltage across the sampling resistor Rs is V1, V2, respectively, i.e. vsense=v1-V2. The current on the sampling resistor R1 is I1, and the current on the sampling resistor R2 is I2. Since the first NMOS transistor NM1 and the current mirror circuit 201 are connected as a negative feedback loop, the emitter voltages of Q2 and Q3 are equal, and the voltage is V0, the voltage v1=i1×r1+v0, the voltage v2=i2×r2+v0, that is, vsense=v1-v2=i1×r1-i2×r2.
Further, by selecting the ratio of the resistors R1, R2 to be 1: n, i.e. r2=n×r1. Vsense=v1-v2=i1×r1-i2×r2= (I1-n×i2) R1.
Further, due to the mirroring effect of the current mirror circuit 201, the currents IQ1, IQ2, IQ3, IQ4 flowing through Q1, Q2, Q3, Q4 are equal, so iq=iq 1=iq 2=iq 3=iq 4.
The current i2=iq 1+iq 2=2×iq flowing through the sampling resistor R2, and the current i1=iq 3+iq 4+i3=2×iq+i3 flowing through the sampling resistor R1, so the current i3=i1-I2 flowing through the first NMOS transistor NM1 and the switching resistor R3. The voltage across the switching resistor R3: v3=i3×r3= (I1-I2) ×r3= (I1-n×i2) r3+ (n-1) i2×r3.
In the above formula, (n-1) i2×r3 is the set output offset voltage Vos, vos= (n-1) i2×r3=2 (R2/R1-1) iq×r3, and the fixed offset voltage Vos needs to be subtracted when calculating the voltage gain, so that the voltage gain of the high-side current detection circuit is Vout/vsense= (V3-Vos)/(V1-V2) = [ (I1-n×i2) r3]/[ (I1-n×i2) R1] =r3/R1, i.e. the ratio of the adjusting resistor R3/R1 can change the voltage gain.
Further, the relation between the total output voltage vout+vos of the current mirror circuit and the current Is flowing through the sampling resistor Rs Is:
Vout+Vos＝I S *R S *(R3/R1)+2(R2/R1-1)IQ*R3。
further, in the filter circuit 102, the resistor r4=r5, the capacitor c1=c2, and the low-pass cut-off frequency of the output voltage is f=1/(5.344 pi×r4×c1).
The following embodiments can be seen from the foregoing:
the current sampling method of the high-side current detection circuit comprises the following steps:
the current to be detected consumed by the load flows through the differential voltage vsense=is of the sixth resistor Rs, rs=v1-V2.
The voltage sampling and amplifying circuit 101 amplifies the voltage of the sixth resistor Rs by a certain multiple and outputs the amplified voltage. Since the current mirror circuit 201 equalizes the currents of the transistors Q1, Q2, Q3, Q4, and the first NMOS transistor NM1 and the current mirror circuit 201 form a negative feedback loop, the emitter currents of the transistors Q1, Q2, Q3, Q4 are equalized and IQ, and i2=2xiq. The difference between the currents of the sense resistor R1 and the second resistor R2 flows through the switching resistor R3. Let r2=n×r1, the voltage across the sense resistor Rs:
Vsense＝Is*Rs＝V1-V2＝II*R1-I2*R2＝(I1-n*I2)R1
voltage across the switching resistor R3:
V3＝I3*R3＝(I1-I2)*R3＝(I1-n*I2)R3+(n-1)I2*R3
the applied offset voltage: vos= (n-1) i2×r3=2 (R2/R1-1) ×iq×r3
Output voltage: vout=v3-vos= (I1-n×i2) R3
Voltage gain factor: vout/vsense=r3/R1
Current to be detected: is= (Vout R1)/(RS R3)
From the above results, the values of R1, R2, R3, RS, IQ are known, the offset voltage can be determined by setting the resistance ratio R2/R1, and the reference current IQ, and the voltage gain is changed by setting the resistance ratio R3/R1. The determined offset voltage and the voltage gain of the current detection circuit can be adjusted according to the MCU requirement, so that the current detection precision of the power driving chip is improved.
The above embodiments are only illustrative of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention, and various modifications and improvements made by those skilled in the art to the technical solutions of the present invention should fall within the protection scope defined by the claims of the present invention without departing from the design spirit of the present invention.
Claims (2)
1. The utility model provides a high limit current detection circuit of offset voltage adjustable which characterized in that includes:
a sampling circuit (100) for providing a sampling voltage;
a voltage sampling amplifying circuit (101) connected to the sampling circuit (100) for amplifying a sampling voltage;
a filter circuit (102) connected to the voltage sampling amplifying circuit (101) for filtering high-frequency noise;
the sampling circuit (100) comprises a sixth resistor (Rs), a first power supply (Vdd) and a load (RL);
one end of the sixth resistor (Rs) is connected with the first power supply (Vdd), and the other end of the sixth resistor (Rs) is grounded through a load (RL);
the voltage sampling amplifying circuit (101) comprises a current mirror circuit (201), a first resistor (R1), a second resistor (R2), a conversion resistor (R3) and a first NMOS tube (NM 1);
the positive input end of the current mirror circuit (201) is connected to the positive electrode of the sixth resistor (Rs) through the first resistor (R1), the negative input end of the current mirror circuit (201) is connected to the negative electrode of the sixth resistor (Rs) through the second resistor (R2), the output end of the current mirror circuit (201) is connected to the positive electrode of the switching resistor (R3) through the first NMOS tube (NM 1), and the negative electrode of the switching resistor (R3) is grounded;
the drain end of the first NMOS tube (NM 1) is connected with the negative electrode of the first resistor (R1), the grid electrode of the first NMOS tube (NM 1) is connected with the output end of the current mirror circuit (201), and the source end of the first NMOS tube (NM 1) is connected with the positive electrode of the switching resistor (R3);
the current mirror circuit (201) comprises a first current mirror;
the first current mirror comprises a first PMOS (P-channel metal oxide semiconductor) tube (PM 1), a second PMOS tube (PM 2), a third PMOS tube (PM 3), a first PNP transistor (Q1), a second PNP transistor (Q2), a third PNP transistor (Q3) and a fourth PNP transistor (Q4);
wherein the emitter of the first PNP transistor (Q1) and the emitter of the second PNP transistor (Q2) are respectively connected with the cathode of the second resistor (R2);
an emitter of the third PNP transistor (Q3) and an emitter of the fourth PNP transistor (Q4) are respectively connected with a cathode of the first resistor (R1);
the base electrode of the first PNP transistor (Q1) and the collector electrode of the first PNP transistor (Q1), the base electrode of the second PNP transistor (Q2), the base electrode of the third PNP transistor (Q3), the base electrode of the fourth PNP transistor (Q4) and the collector electrode of the fourth PNP transistor (Q4) are connected to the source end of the first PMOS transistor (PM 1);
the collector of the second PNP transistor (Q2) is connected with the source end of the second PMOS tube (PM 2);
the collector of the third PNP transistor (Q3) is connected with the source end of the third PMOS tube (PM 3);
the grid electrode of the first PMOS tube (PM 1), the grid electrode of the second PMOS tube (PM 2) and the grid electrode of the third PMOS tube (PM 3) are connected with the drain end of the first PMOS tube (PM 1);
the current mirror circuit (201) further comprises a second current mirror;
the second current mirror comprises a second NMOS tube (NM 2), a third NMOS tube (NM 3), a fourth NMOS tube (NM 4), a fifth NMOS tube (NM 5) and a second power supply (IQ);
the drain end of the fifth NMOS tube (NM 5) is connected with the drain end of the first PMOS tube (PM 1);
the source end of the fifth NMOS tube (NM 5) is connected with the drain end of the fourth NMOS tube (NM 4);
the source end of the third NMOS tube (NM 3) is connected with the drain end of the second NMOS tube (NM 2), the grid electrode of the second NMOS tube (NM 2) and the grid electrode of the fourth NMOS tube (NM 4);
the drain end of the third NMOS tube (NM 3), the grid electrode of the third NMOS tube (NM 3) and the grid electrode of the fifth NMOS tube (NM 5) are connected with a second power supply (IQ), and the current provided by the second power supply (IQ) is equal to the collector current of the first PNP transistor (Q1);
the source end of the second NMOS tube (NM 2) and the source end of the fourth NMOS tube (NM 4) are grounded;
the current mirror circuit (201) further comprises a third current mirror;
the third current mirror comprises a sixth NMOS tube (NM 6), a seventh NMOS tube (NM 7), an eighth NMOS tube (NM 8) and a ninth NMOS tube (NM 9);
the drain end of the ninth NMOS tube (NM 9) and the drain end of the third PMOS tube (PM 3) are connected with the grid electrode of the first NMOS tube (NM 1);
the source end of the ninth NMOS tube (NM 9) is connected with the drain end of the eighth NMOS tube (NM 8);
the grid electrode of the seventh NMOS tube (NM 7), the drain end of the seventh NMOS tube (NM 7) and the grid electrode of the ninth NMOS tube (NM 9) are connected with the drain end of the second PMOS tube (PM 2);
the drain end of the sixth NMOS tube (NM 6), the grid electrode of the sixth NMOS tube (NM 6) and the grid electrode of the eighth NMOS tube (NM 8) are connected with the source end of the seventh NMOS tube (NM 7);
the source end of the sixth NMOS tube (NM 6) and the source end of the eighth NMOS tube (NM 8) are grounded.
2. The offset voltage adjustable high side current detection circuit according to claim 1, wherein,
the filter circuit (102) comprises a fourth resistor (R4), a fifth resistor (R5), a first capacitor (C1) and a second capacitor (C2);
the positive pole of fifth resistance (R5) is connected at the positive pole of converting resistor (R3) through fourth resistance (R4), and the negative pole of fifth resistance (R5) is connected with total output (Vout), the positive pole of first electric capacity (C1) and fifth resistance (R5) are connected, the negative pole of fourth resistance (R4), the other end ground connection of first electric capacity (C1), the one end of second electric capacity (C2) is connected with the negative pole of fifth resistance (R5), total output (Vout), the other end ground connection of second electric capacity (C2).
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| CN202211626862.6A CN115932363B (en) | 2022-12-16 | 2022-12-16 | Offset voltage adjustable high-side current detection circuit |
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| KR20150140430A (en) * | 2014-06-05 | 2015-12-16 | 서울시립대학교 산학협력단 | Current sensing circuit and driver uising the same |
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