CN113067566B

CN113067566B - High-voltage insulating isolation SiC MOSFET gate driving circuit with protection function

Info

Publication number: CN113067566B
Application number: CN202110347550.0A
Authority: CN
Inventors: 陈珍海; 袁述; 卢基存; 黎力
Original assignee: Jiangsu Zhongkehanyun Semiconductor Co ltd
Current assignee: Jiangsu Zhongkehanyun Semiconductor Co ltd
Priority date: 2021-03-31
Filing date: 2021-03-31
Publication date: 2024-04-30
Anticipated expiration: 2041-03-31
Also published as: CN113067566A

Abstract

The invention discloses a high-voltage insulating isolation SiC MOSFET gate driving circuit with a protection function, which comprises: the device comprises an input receiving circuit, a data channel digital control circuit, a data channel modulation transmitting circuit, a data channel high common mode transient suppression differential signal receiving circuit, a protection channel digital control circuit, a protection channel modulation transmitting circuit, a protection channel high common mode transient suppression differential signal receiving circuit, an output driving circuit, a transmitting end low voltage generating circuit, a receiving end low voltage generating circuit and a high voltage isolating circuit. On one hand, the invention adopts a high-precision protection circuit to prevent the SiC MOSFET from being separated from a safe working area, thereby improving the reliability; on the other hand, by adopting a high-voltage insulation isolation technology, an ultrahigh voltage-resistant insulation capacitor can be realized; in addition, the magnitude of the ground potential common mode transient noise is automatically detected, and errors generated by the common mode transient noise are dynamically compensated when the noise exceeds a threshold value. The invention can be widely applied to driving various high-voltage SiCNOSFET and IGBT devices.

Description

High-voltage insulating isolation SiC MOSFET gate driving circuit with protection function

Technical Field

The invention relates to a high-voltage insulating isolation SiC MOSFET gate driving circuit with a protection function, and belongs to the technical field of integrated circuits.

Background

With the advent and popularity of Si-based superjunction MOSFETs and Insulated Gate Bipolar Transistors (IGBTs), silicon devices have begun to be unsuitable for some high voltage, high temperature, high efficiency and high power density applications due to their own physical characteristics limitations. Compared with Si materials, the higher thermal conductivity of the SiC materials determines the characteristic of high current density, and the higher forbidden bandwidth determines the high breakdown field strength and the high working temperature of the SiC devices. Especially in development and application of SiC MOSFET, compared with Si MOSFET with the same power level, the on-resistance and switching loss of the SiC MOSFET are greatly reduced, and the SiC MOSFET is suitable for higher working frequency, and in addition, the high-temperature stability is greatly improved due to the high-temperature working characteristic.

Because the characteristics of the SiC MOSFET device are greatly different from those of the traditional Si MOSFET, the performance of the SiC MOSFET driving circuit plays a vital role on the whole system. The new generation of power electronic complete machine system based on SiC devices brings higher demands to the driving speed and the intellectualization of a high-voltage gate driving chip, thereby further improving the reliability of the complete machine and reducing the design complexity of the complete machine system. Compared with Si MOSFETs, siC MOSFETs have smaller parasitic capacitance, and the difference between the parasitic capacitance and the parasitic capacitance is more than ten times, so that the SiC MOSFETs are more sensitive to parasitic parameters of a driving circuit. On the other hand, the driving voltage range of SiC MOSFETs is typically-5V to +25v, whereas the driving voltage range of conventional Si MOSFETs is-30V to +30v. Therefore, siC MOSFETs have smaller safety thresholds than conventional Si MOSFETs, and a voltage spike in the drive circuit is likely to break down the oxide layer between the gate sources, which is also a careful design of the output control level of the drive circuit.

The high-voltage gate driving chip is used for meeting the requirement of conversion driving between a low-power level signal provided by an output interface of the CPU controller and a high-voltage high-current signal required by gate driving of a high-power output device. The core function of the grid driving IC in the whole system is to convert a low-power level signal (1 mA/3-5V) output by a CPU controller into a high-voltage and high-current signal (0.5-5A/5-20V) required by grid driving of a high-power device, and amplify output current and output voltage swing; because the output driving object is a high-voltage high-current device, a great voltage difference exists between the substrate potential of the output circuit and the substrate potential of the input circuit, and the high-voltage circuit and the low-voltage circuit are required to be electrically isolated; in addition, since signal connection must be performed between the high voltage and low voltage area circuits, an isolation area signal transmission module responsible for signal transmission function between two sides of the isolation area must be provided in the chip. Since the SiC MOSFET is applied in a high power system, the SiC MOSFET must be protected from escaping from its safe operating area during operation, thereby shortening the life and even damaging the SiC MOSFET. Therefore, the SiC MOSFET gate driving circuit generally integrates monitoring and protection circuits, including overvoltage, undervoltage, over-temperature, and over-current protection functions.

Disclosure of Invention

The invention aims at providing a high-voltage insulation isolation SiC MOSFET gate driving circuit which is based on an insulation isolation technology and has high common mode transient noise suppression characteristic aiming at the driving application requirement of a SiC MOSFET device.

According to the technical scheme provided by the invention, the high-voltage insulating isolation SiC MOSFET gate driving circuit with the protection function comprises: the device comprises an input receiving circuit, a data channel digital control circuit, a data channel modulation transmitting circuit, a first high-voltage isolation circuit, a protection channel high-common mode transient suppression differential signal receiving circuit, a protection channel digital control circuit, a protection channel modulation transmitting circuit, a second high-voltage isolation circuit, a data channel high-common mode transient suppression differential signal receiving circuit, an output driving circuit, a transmitting end low-voltage generating circuit, a receiving end low-voltage generating circuit, a transmitting end undervoltage protection circuit, a transmitting end overtemperature protection circuit, a transmitting end overcurrent protection circuit, a receiving end undervoltage protection circuit, a receiving end overtemperature protection circuit and a receiving end overcurrent protection circuit;

The input receiving circuit, the data channel digital control circuit, the data channel modulation transmitting circuit, the data channel high common mode transient suppression differential signal receiving circuit, the transmitting end undervoltage protection circuit, the transmitting end overtemperature protection circuit, the transmitting end overcurrent protection circuit and the transmitting end low voltage generation circuit form a driving circuit transmitting end circuit; the protection channel digital control circuit, the protection channel modulation and transmission circuit, the protection channel high common mode transient suppression differential signal receiving circuit, the output driving circuit, the receiving end undervoltage protection circuit, the receiving end over-temperature protection circuit, the receiving end overcurrent protection circuit and the receiving end low voltage generation circuit form a driving circuit receiving end circuit; the ground potential of all circuits in the circuit of the transmitting end of the driving circuit is connected to the ground voltage Vgnd1 of the transmitting end, and the ground potential of all circuits in the circuit of the receiving end of the driving circuit is connected to the ground voltage Vgnd2 of the receiving end; the first high-voltage isolation circuit comprises a positive-end transmitting capacitor Ctp, a negative-end transmitting capacitor Ctn, a positive-end receiving capacitor Crp and a negative-end receiving capacitor Crn, and the second high-voltage isolation circuit comprises a positive-end transmitting capacitor Ctpp, a negative-end transmitting capacitor Ctnp, a positive-end receiving capacitor Crpp and a negative-end receiving capacitor Crnp;

The input receiving circuit receives external low-level logic input data DI and a control signal Adj, and is processed and converted into input data Din with a high level VCC and a control signal Adjin, and the input data Din and the control signal Adjin are connected to the input end of the data channel digital control circuit; the data channel digital control circuit converts Din into differential input data DxP and DxN according to the state of an undervoltage protection signal UVLO provided by a transmitting end undervoltage protection circuit, an overtemperature protection signal OTP provided by a transmitting end overtemperature protection circuit, an overcurrent protection signal OCP provided by a transmitting end overcurrent protection circuit, an Error signal Error output by a data channel high common mode transient suppression differential signal receiving circuit and a control signal Adjin, and the differential input data DxP and DxN are connected to the input end of a data channel modulation transmitting circuit, and the data channel modulation transmitting circuit outputs the differential transmission data TxP and TxN of the data channel; the data channel differential transmission data TxP and TxN are respectively connected to the left ends of a positive end transmission capacitor Ctp and a negative end transmission capacitor Ctn, the right ends of the positive end transmission capacitor Ctp and the negative end transmission capacitor Ctn are respectively connected to the left ends of a positive end receiving capacitor Crp and a negative end receiving capacitor Crn, and the right ends of the positive end receiving capacitor Crp and the negative end receiving capacitor Crn respectively generate data channel differential reception data RxP and RxN; the data channel differential receiving data RxP and RxN are connected to the input end of the protection channel high common mode transient suppression differential signal receiving circuit, the data channel differential receiving data RxP and RxN are processed to obtain receiving output data Dout, the receiving output data Dout is connected to the input end of the output driving circuit, and the output driving circuit outputs an output driving signal DG with large driving current;

The protection channel digital control circuit obtains differential protection data PxP and PxN according to the state of an undervoltage protection signal UVLO_P provided by the receiving end undervoltage protection circuit, an overtemperature protection signal OTP_P provided by the receiving end overtemperature protection circuit and an overcurrent protection signal OCP_P provided by the receiving end overcurrent protection circuit, and is connected to the input end of the protection channel modulation transmitting circuit; the protection channel modulation transmission circuit outputs protection channel differential transmission data TxPp and TxNp which are respectively connected to the right ends of the positive end transmission capacitor Ctpp and the negative end transmission capacitor Ctnp; the left ends of the positive end transmitting capacitor Ctpp and the negative end transmitting capacitor Ctnp are respectively connected to the right ends of the positive end receiving capacitor Crpp and the negative end receiving capacitor Crnp, the left ends of the positive end receiving capacitor Crpp and the negative end receiving capacitor Crnp generate protection channel differential receiving data RxP and RxN, the protection channel differential receiving data and RxN are connected to the input end of the data channel high common mode transient suppression differential signal receiving circuit, and the data channel high common mode transient suppression differential signal receiving circuit outputs an Error signal Error and is connected to the input end of the data channel digital control circuit;

the transmitting end low voltage generating circuit and the receiving end low voltage generating circuit are realized by adopting the same low voltage generating circuit; the transmitting end low voltage generating circuit adopts transmitting end power supply voltage VCC to generate reference voltage and bias voltage required by each component circuit in the low voltage power supply VCL input receiving circuit and the driving circuit transmitting end circuit; the receiving end low voltage generating circuit adopts the receiving end power supply voltage VDD to generate reference voltage and bias voltage required by each component circuit in the receiving end circuit of the driving circuit.

Specifically, the protection channel high common mode transient suppression differential signal receiving circuit includes: the differential input receiving circuit, the X-stage tandem common mode adjustable amplifying circuit, the high-sensitivity common mode adjustable amplifying circuit, the first output shaping circuit and the common mode self-adaptive adjusting circuit; the differential input receiving circuit firstly receives a differential receiving data positive end receiving signal RxP and a differential receiving data negative end receiving signal RxN, and a positive end input signal Vip and a negative end input signal Vin are obtained through filtering; the positive end input signal Vip and the negative end input signal Vin enter a first-stage common-mode adjustable amplifying circuit in the X-stage tandem common-mode adjustable amplifying circuit, and finally a positive end output signal VoXp and a negative end output signal VoXn of the X-stage common-mode adjustable amplifying circuit are obtained; the positive end output signal VoXp and the negative end output signal VoXn are respectively connected with the positive input end and the negative input end of the high-sensitivity common-mode adjustable amplifying circuit, and the high-sensitivity common-mode adjustable amplifying circuit outputs a group of differential output signals, including a positive end output signal VoXp and a negative end output signal VoXn; the first output shaping circuit processes the positive output signal VoXp and the negative output signal VoXn to obtain final data output, namely receiving output data Dout; the common mode self-adaptive adjusting circuit adaptively generates common mode adjusting signals C11, C12, C21, C22, …, CX1 and CX2 for each stage of amplifying circuit according to the change of the power supply and ground voltage signals, and the common mode adjusting signals C11 and C12 generated by the common mode self-adaptive adjusting circuit are respectively connected to the common mode adjusting signal input end of the first stage of common mode adjustable amplifying circuit; the common mode adjustment signals C21 and C22 are respectively connected to the common mode adjustment signal input end of the second-stage common mode adjustable amplifying circuit; by analogy, the common mode adjustment signals CX1 and CX2 are respectively connected to the common mode adjustment signal input end of the X-th stage common mode adjustable amplifying circuit; the common mode self-adaptive adjusting circuit also generates common mode adjusting signals CN1 and CN2 which are respectively connected to the common mode adjusting signal input end of the high-sensitivity common mode adjustable amplifying circuit; wherein X is a positive integer greater than 1, and N is a positive integer greater than X; the data channel high common mode transient suppression differential signal receiving circuit and the protection channel high common mode transient suppression differential signal receiving circuit are realized by adopting the same high common mode transient suppression differential signal receiving circuit, and data output by the data channel high common mode transient suppression differential signal receiving circuit is used as an Error signal Error.

Specifically, the differential input receiving circuit includes: the device comprises a positive end isolation capacitor C51, a positive end grounding resistor R51, a positive end coupling capacitor C52, a positive end common mode resistor R53, a negative end isolation capacitor C53, a negative end grounding resistor R52, a negative end coupling capacitor C54, a negative end common mode resistor R54 and a receiving common mode generating circuit; the left end of the positive end isolation capacitor C51 and the left end of the negative end isolation capacitor C53 are respectively connected to a positive end receiving signal RxP and a negative end receiving signal RxN; the right end of the positive end isolation capacitor C51 is connected to the lower end of the positive end grounding resistor R51 and the left end of the positive end coupling capacitor C52; the right end of the negative end isolation capacitor C53 is connected to the lower end of the negative end grounding resistor R52 and the left end of the negative end coupling capacitor C54; the right end of the positive end coupling capacitor C52 is connected to the upper end of the positive end common mode resistor R53 and is used as the output end of the positive end input signal Vip; the right end of the negative end coupling capacitor C54 is connected to the lower end of the negative end common mode resistor R54 and is used as the output end of a negative end input signal Vin; the lower end of the positive end common mode resistor R53 is connected with the upper end of the negative end common mode resistor R54 and is simultaneously connected to the common mode output end Vicm of the receiving common mode generating circuit; the receiving common mode generating circuit dynamically tracks and adjusts the size of a common mode output end Vicm according to the change of an input common mode Vcm, and reduces the influence of the input common mode.

Specifically, the reception common mode generation circuit includes: NMOS tube M60, NMOS tube M61, PMOS tube M62, NMOS tube M63, PMOS tube M64, PMOS tube M65, NMOS tube M66, NMOS tube M67, PMOS tube M68, NMOS tube M69, PMOS tube M610, NMOS tube M611, PMOS tube M612, NMOS tube M613, NMOS tube M614, PMOS tube M615 and resistor R61, a first Schmitt trigger;

The grid electrode of the NMOS tube M60 is connected to an input common mode voltage Vcm; the drain electrode of the NMOS tube M60 is connected to the drain electrode and the grid electrode of the PMOS tube M62 and the grid electrode of the NMOS tube M63; the grid electrode of the NMOS tube M61 is connected to an input common mode control signal Vctrl; the drain electrode of the NMOS tube M61 is connected with the drain electrode of the NMOS tube M63 and is connected to the input end of the first Schmitt trigger; the output end of the first Schmitt trigger is simultaneously connected to the grid electrode of the PMOS tube M610, the grid electrode of the NMOS tube M611, the grid electrode of the PMOS tube M612 and the grid electrode of the NMOS tube M613; the drain electrode of the PMOS tube M610 is connected with the drain electrode of the NMOS tube M611 and is also connected to the grid electrode of the NMOS tube M614; the drain electrode of the PMOS tube M612 is connected with the drain electrode of the NMOS tube M613 and is also connected to the grid electrode of the PMOS tube M615; the source electrode of the NMOS tube M614 is connected with the source electrode of the PMOS tube M615 and is also used as an output port of the common mode output end Vicm; the drain of the NMOS tube M614 is connected to the high input common mode level Vcmh, and the drain of the PMOS tube M615 is connected to the low input common mode level Vcml; the source electrode of the NMOS tube M613 is connected to the upper end of the resistor R61; the source electrode of the NMOS tube M60, the source electrode of the NMOS tube M61, the source electrode of the NMOS tube M611 and the lower end of the resistor R61 are simultaneously connected to the ground voltage; the source of the PMOS transistor M62, the source of the NMOS transistor M63, and the source of the PMOS transistor M610 are simultaneously connected to the power supply voltage.

Specifically, the common mode adaptive adjustment circuit includes: the device comprises a first common mode detection circuit, a common mode detection signal transmission circuit, an adjustment common mode signal generation circuit and a common mode adjustment signal selection circuit; the first common mode detection circuit is used for detecting power supply and substrate noise, changing the magnitude of a common mode detection signal Vcm_det when the noise is larger than a certain threshold value, connecting the common mode detection signal Vcm_det to the common mode detection signal transmission circuit, generating common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2 and NN1, NN2 through the common mode detection signal transmission circuit, and outputting the common mode selection switch control signals to the common mode adjustment signal selection circuit; the common mode adjustment signal selection circuit generates and adjusts the sizes of the common mode adjustment signals C11, C12, C21, C22, …, CX1, CX2 and CN1, CN2 according to the common mode selection switch control signal and outputs the common mode adjustment signals; the common mode adjustment signal generating circuit is used for generating various common mode bias signals required by the common mode adjustment signal selecting circuit and outputting the common mode bias signals to the common mode adjustment signal selecting circuit.

Specifically, the first common mode detection circuit includes: PMOS tube M111, PMOS tube M112 and NMOS tube M113; the grid electrode and the drain electrode of the PMOS tube M111 are connected and connected to the drain electrode of the PMOS tube M112 and the grid electrode of the NMOS tube M113; the grid electrode of the PMOS tube M112 is connected with the drain electrode of the NMOS tube M113 and is used as an output node of the common mode detection signal Vcm_det; the source of the PMOS tube M111 and the source of the PMOS tube M112 are connected with a power supply voltage, and the source of the NMOS tube M113 is connected with a ground voltage.

Specifically, the sending end over-temperature protection circuit and the receiving end over-temperature protection circuit adopt the same over-temperature protection circuit, and comprise a clamping circuit, a temperature detection circuit, a wide voltage range comparator circuit and a first output shaping circuit which are sequentially connected, wherein the temperature detection circuit obtains a first temperature detection output signal Vin1 and a second temperature detection output signal Vin2 according to a bias voltage Vb provided by the clamping circuit; the wide voltage range comparator circuit compares the first temperature detection output signal Vin1 with the second temperature detection output signal Vin2 to obtain a comparison output signal Vo1; the first output shaping circuit processes the comparison output signal Vo1 to output a temperature protection signal OTLock, wherein OTLock is a digital logic signal, OTLock is connected to an input end of the clamping circuit to control the bias voltage Vb, and OTLock is also used as a control signal to output to other circuit modules of the high-voltage insulation SiC MOSFET gate driving circuit.

Specifically, the temperature detection circuit includes: PMOS tube M21, PMOS tube M22, resistor R21, triode Q1 and triode Q2; the base electrodes of the triode Q1 and the triode Q2 are connected and connected to a bias voltage Vb output node of the clamping circuit; the emitter of the triode Q1 is connected to the grid electrode and the drain electrode of the PMOS tube M21 and is used as an output node of a first temperature detection output signal Vin 1; the emitter of the triode Q2 is connected to the grid electrode and the drain electrode of the PMOS tube M22 and is used as an output node of a second temperature detection output signal Vin2; the source electrode of the PMOS tube M21 and the source electrode of the PMOS tube M22 are connected to a power supply voltage, the collector electrode of the triode Q2 is connected to the upper end of the resistor R21, and the lower end of the resistor R21 and the collector electrode of the triode Q1 are connected to a ground voltage; the width-to-length ratio of the PMOS transistor M21 and the PMOS transistor M22 is equal, and the base area ratio of the transistor Q1 and the transistor Q2 is 1: n and N are arbitrary natural numbers.

Specifically, the wide voltage range comparator circuit includes: PMOS tube M31, PMOS tube M33, PMOS tube M35, PMOS tube M36, PMOS tube M37, PMOS tube M39, NMOS tube M32, NMOS tube M34, NMOS tube M38, NMOS tube M310 and second common mode detection circuit; the grid electrode of the PMOS tube M31 is connected to the first temperature detection output signal Vin1, and the grid electrode of the PMOS tube M33 is connected to the second temperature detection output signal Vin2; the drain electrode of the PMOS tube M31 is connected to the drain electrode and the gate electrode of the NMOS tube M32, the gate electrode of the NMOS tube M34 and the gate electrode of the NMOS tube M310; the drain electrode of the PMOS tube M33 is connected to the drain electrode of the NMOS tube M34 and the grid electrode of the PMOS tube M37; the drain electrode of the PMOS tube M37 is connected to the drain electrode and the grid electrode of the NMOS tube M38, and the source electrode of the PMOS tube M37 is connected to the grid electrode of the PMOS tube M39 and the drain electrode of the PMOS tube M36; the source electrode of the PMOS tube M36 is connected to the drain electrode of the PMOS tube M35, and the grid electrodes of the PMOS tube M36 and the PMOS tube M35 are both connected to the control signal output by the second common mode detection circuit; the drain electrode of the PMOS tube M39 is connected with the drain electrode of the NMOS tube M310 and outputs a comparison output signal Vo1; the sources of the PMOS tube M31, the PMOS tube M33, the PMOS tube M35 and the PMOS tube M39 are simultaneously connected to the power supply voltage; the sources of the NMOS transistors M32, M34, M38 and M310 are simultaneously connected to the ground voltage.

Specifically, the second common mode detection circuit automatically detects common mode noise generated by the power supply voltage and the substrate potential, and changes the common mode control signal vcm_det when the common mode noise exceeds a certain threshold value; when the common mode noise does not exceed the threshold value, the common mode control signal Vcm_det is at a high level, the PMOS tube M36 and the PMOS tube M35 are in an off state, and the grid electrode of the PMOS tube M39 is controlled by the source electrode of the PMOS tube M37; when the common mode noise exceeds the threshold value, the common mode control signal vcm_det is at a low level, the PMOS transistor M36 and the PMOS transistor M35 are both in a conducting state, the PMOS transistor M39 is in a closing state, and the comparison output signal Vo1 is clamped to a low level, so that the normal operation of the comparator is prevented from being affected by the common mode noise.

The invention has the advantages that: the high-voltage insulating isolation SiC MOSFET gate driving circuit with the protection function adopts a high-precision protection circuit to prevent the SiC MOSFET from being separated from a safe working area, so that the reliability is improved; on the other hand, by adopting a high-voltage insulation isolation technology, an ultrahigh voltage-resistant insulation capacitor can be realized; in addition, the circuit can automatically detect the magnitude of the ground potential common mode transient noise and dynamically compensate errors generated by the common mode transient noise when the noise exceeds a threshold value.

Drawings

Fig. 1 is a diagram showing a gate driving circuit structure of a high-voltage insulating isolation SiC MOSFET with a protection function according to the present invention.

Fig. 2 is a block diagram of an input receiving circuit according to the present invention.

Fig. 3 is a diagram of the digital control circuit of the present invention.

Fig. 4 is a block diagram of a modulation transmission circuit according to the present invention.

Fig. 5 is a block diagram of a high common mode transient suppression differential signal receiving circuit according to the present invention.

Fig. 6 is a schematic diagram of a differential input receiving circuit according to an embodiment of the invention.

Fig. 7 is a schematic diagram of a receiving common mode generating circuit according to an embodiment of the present invention.

Fig. 8 is a schematic diagram of a common mode tunable amplifier circuit according to an embodiment of the invention.

Fig. 9 is a schematic diagram of an embodiment of a high sensitivity common mode tunable amplifying circuit according to the present invention.

Fig. 10 is a schematic diagram of a first output shaping circuit according to an embodiment of the present invention.

Fig. 11 is a schematic diagram of a common mode adaptive adjustment circuit according to an embodiment of the invention.

Fig. 12 is a schematic diagram of a common mode detection circuit according to an embodiment of the present invention.

Fig. 13 is an operational waveform of the circuit of fig. 12.

Fig. 14 shows an embodiment of the high voltage isolation capacitor of the present invention.

Fig. 15 is a diagram of a low voltage generation circuit according to an embodiment of the invention.

Fig. 16 is a block diagram of the high-precision wide-voltage-range over-temperature protection circuit of the present invention.

Fig. 17 is a schematic diagram of an embodiment of a clamping circuit according to the present invention.

Fig. 18 is a schematic diagram of a temperature sensing circuit according to an embodiment of the present invention.

FIG. 19 is a schematic diagram of a wide voltage range comparator circuit according to one embodiment of the present invention.

Fig. 20 is a diagram of a second output shaping circuit according to an embodiment of the present invention.

FIG. 21 is a block diagram of a high precision undervoltage protection circuit of the present invention.

Fig. 22 is a block diagram of a high-precision overcurrent protection circuit according to the present invention.

Fig. 23 is an embodiment of an output driving circuit of the present invention.

Detailed Description

The invention will now be described in further detail with reference to the drawings and examples.

As shown in fig. 1, the high-voltage insulating isolation SiC MOSFET gate driving circuit with a protection function according to the present invention includes an input receiving circuit 1, a data channel digital control circuit 2, a data channel modulation transmitting circuit 5, a first high-voltage isolation circuit 11, a protection channel high-common mode transient suppression differential signal receiving circuit 6, a protection channel digital control circuit 10, a protection channel modulation transmitting circuit 9, a second high-voltage isolation circuit 12, a data channel high-common mode transient suppression differential signal receiving circuit 4, an output driving circuit 7, a transmitting end low-voltage generating circuit 3, a receiving end low-voltage generating circuit 8, a transmitting end under-voltage protection circuit 13, a transmitting end over-temperature protection circuit 14, a transmitting end over-current protection circuit 15, a receiving end under-voltage protection circuit 16, a receiving end over-temperature protection circuit 17, and a receiving end over-current protection circuit 18.

The input receiving circuit 1, the data channel digital control circuit 2, the data channel modulation transmitting circuit 5, the data channel high common mode transient suppression differential signal receiving circuit 4, the transmitting end undervoltage protection circuit 13, the transmitting end overtemperature protection circuit 14, the transmitting end overcurrent protection circuit 15 and the transmitting end low voltage generating circuit 3 form a driving circuit transmitting end circuit; the protection channel digital control circuit 10, the protection channel modulation and transmission circuit 9, the protection channel high common mode transient suppression differential signal receiving circuit 6, the output driving circuit 7, the receiving end undervoltage protection circuit 16, the receiving end over-temperature protection circuit 17, the receiving end overcurrent protection circuit 18 and the receiving end low voltage generation circuit 8 form a driving circuit receiving end circuit. The ground potential of all circuits inside the transmitting end circuit of the driving circuit is connected to the transmitting end ground voltage Vgnd1, and the ground potential of all circuits inside the receiving end circuit of the driving circuit is connected to the receiving end ground voltage Vgnd2.

The high-voltage isolation circuit is used for isolating the drive circuit transmitting end circuit from the drive circuit receiving end circuit. The first high-voltage isolation circuit 11 includes a positive-side transmitting capacitor Ctp, a negative-side transmitting capacitor Ctn, a positive-side receiving capacitor Crp and a negative-side receiving capacitor Crn, and the second high-voltage isolation circuit 12 includes a positive-side transmitting capacitor Ctpp, a negative-side transmitting capacitor Ctnp, a positive-side receiving capacitor Crpp and a negative-side receiving capacitor Crnp.

The input receiving circuit 1 receives external low-level logic input data DI and a control signal Adj, and converts the input data Din and the control signal Adjin into input data Din with a high level VCC through processing; the input data Din then enters a data channel digital control circuit 2, and the data channel digital control circuit 2 obtains differential input data DxP and DxN according to the states of an undervoltage protection signal UVLO provided by a transmitting end undervoltage protection circuit 13, an over-temperature protection signal OTP provided by a transmitting end over-temperature protection circuit 14, an over-current protection signal OCP provided by a transmitting end over-current protection circuit 15, an Error signal Error output by a data channel high common mode transient suppression differential signal receiving circuit 4 and a control signal Adjin; the differential input data DxP and DxN enter a data channel modulation and transmission circuit 5 to obtain data channel differential transmission data TxP and TxN; the data channel differential transmission data TxP and TxN are respectively connected to the left ends of the positive end transmission capacitor Ctp and the negative end transmission capacitor Ctn; the right ends of the positive end transmitting capacitor Ctp and the negative end transmitting capacitor Ctn are respectively connected to the left ends of the positive end receiving capacitor Crp and the negative end receiving capacitor Crn; the right ends of the positive end receiving capacitor Crp and the negative end receiving capacitor Crn are used for differentially receiving data RxP and RxN of the data channel; the data channel differential receiving data RxP and RxN enter a protection channel high common mode transient suppression differential signal receiving circuit 6, and are processed to obtain receiving output data Dout; the received output data Dout finally enters the output driving circuit 7 to generate an output driving signal DG having a large driving current.

The same way as the data channel digital control circuit 2, the protection channel digital control circuit 10 obtains differential protection data PxP and PxN according to the state of the under-voltage protection signal uvlo_p provided by the receiving end under-voltage protection circuit 16, the over-temperature protection signal otp_p provided by the receiving end over-temperature protection circuit 17 and the over-current protection signal ocp_p provided by the receiving end over-current protection circuit 18; the differential protection data PxP and PxN enter a protection channel modulation transmitting circuit 9 to obtain protection channel differential transmission data TxPp and TxNp; the protection channel differential transmit data TxPp and TxNp are connected to the right end of the positive side transmit capacitor Ctpp and the negative side transmit capacitor Ctnp, respectively; the left ends of the positive end transmitting capacitor Ctpp and the negative end transmitting capacitor Ctnp are respectively connected to the right ends of the positive end receiving capacitor Crpp and the negative end receiving capacitor Crnp; the left ends of the positive end receiving capacitor Crpp and the negative end receiving capacitor Crnp are protection channel differential receiving data RxP and RxN; the differential receiving data RxP of the protection channel and the RxN enter the high common mode transient suppression differential signal receiving circuit 4 of the data channel, and an Error signal Error is obtained through processing.

The transmitting end low voltage generating circuit 3 adopts a transmitting end power supply voltage VCC to generate various reference voltages and bias voltages required by various component circuits in the low voltage power supply VCL input to the receiving circuit 1 and the driving circuit transmitting end circuit. The receiving end low voltage generating circuit 8 adopts the receiving end power supply voltage VDD to generate various reference voltages and bias voltages required by various component circuits inside the receiving end circuit of the driving circuit. The transmitting-side low voltage generating circuit 3 and the receiving-side low voltage generating circuit 8 are realized by adopting the same low voltage generating circuit.

The transmitting end undervoltage protection circuit 13 and the receiving end undervoltage protection circuit 16 are realized by adopting the same high-precision undervoltage protection circuit; the transmitting end over-temperature protection circuit 14 and the receiving end over-temperature protection circuit 17 are realized by adopting the same high-precision over-temperature protection circuit with wide voltage range; the transmitting-end overcurrent protection circuit 15 and the receiving-end overcurrent protection circuit 18 are realized by adopting the same high-precision overcurrent protection circuit.

In the circuit shown in fig. 1, the transmitting end undervoltage protection circuit 13, the transmitting end overtemperature protection circuit 14 and the transmitting end overcurrent protection circuit 15 respectively provide an undervoltage protection signal UVLO, an overtemperature protection signal OTP and an overcurrent protection signal OCP, and the undervoltage protection signal UVLO, the overtemperature protection signal OTP and the overcurrent protection signal OCP are sent to the data channel digital control circuit 2 to judge whether the chip state is correct or not. When the circuit generates overcurrent (OCP is effective), overtemperature (OTP is effective) or undervoltage of power supply voltage (UVLO is effective), the data channel digital control circuit 2 can block two paths of output DxP and DxN; when the overcurrent and overtemperature alarms are released and the power supply returns to the normal working voltage, the data channel digital control circuit 2 indicates the circuit to work normally. The under-voltage protection circuit 16, the over-temperature protection circuit 17 and the over-current protection circuit 18 of the receiving end, which are used for monitoring and outputting the state of the SIC MOSFET, respectively provide the under-voltage protection signal UVLO_P, the over-temperature protection signal OTP_P and the over-current protection signal OCP_P, and feed back and transmit the under-voltage protection signal UVLO_P, the over-temperature protection signal OTP_P and the over-current protection signal OCP_P to the transmitting circuit 9, the second high-voltage isolation circuit 12 and the data channel high-common mode transient suppression differential signal receiving circuit 4 through the protection channel modulation and transmission circuit to the transmitting end to obtain an Error signal Error, and on one hand, the Error signal Error is fed back to the data channel digital control circuit 2 and is output to an external CPU controller.

The basic input receiving circuit 1 of the high-voltage SiC MOSFET gate driving circuit is shown in fig. 2, and adopts two channels of identical input receiving circuits, wherein each channel of receiving circuit comprises an input ESD protection circuit, a level discrimination circuit and a medium-voltage level shifting circuit. The input receiving circuit 1 not only needs to complete signal transmission, but also needs to complete ESD protection of the internal circuit of the chip, so as to prevent the circuit from being damaged due to impact of ESD on the internal circuit. The circuits commonly used for ESD protection for integrated circuit design are: a lateral SCR clamp, an anti-parallel diode clamp, a zener clamp, a CDM clamp, etc. The level discrimination circuit is used to identify whether the external input level is logic "0" or "1", and must have sufficient noise margin against interference due to the presence of external signals, and the specific circuit implementation typically includes 2 forms, one is Schmitt trigger and the other is a hysteresis comparator. The implementation circuits of the Schmitt trigger and the hysteresis comparator have great difference according to different speeds of the driving chip driving object and the input logic signal. Since the supply voltage VCC of the gate driver chip is typically a medium voltage level of 10-20V, and the input logic level is an external digital logic of less than 5V, the input ESD and level discrimination circuits must use a relatively lower supply voltage VCL, typically 3-10V, to more accurately perform the determination of the input logic level. Therefore, before the logic signal output by the level discrimination circuit enters the control logic inside the chip, the logic signal with the high level VCL must be converted into the logic signal with the high level VCC by a medium voltage level shift circuit, so as to obtain Din and Adjin signals.

The digital control circuit of the invention is used for integrating the chip state monitoring signal, judging whether the circuit is normal or not, and switching off the data output when the chip is abnormal. One digital control circuit implementation provided in an embodiment is shown in fig. 3, which is made up of combinational logic gates. The control process realized by the circuit is as follows: when the circuit generates overcurrent (OCP is effective), overtemperature (OTP is effective) or power supply voltage undervoltage (UVLO is effective), an error logic circuit of the first row in the diagram outputs a low-level signal to indicate that the circuit is abnormal, and two paths of outputs DxP and DxN are blocked; when the overcurrent and over-temperature alarm is released and the power supply returns to normal working voltage, the error logic circuit immediately outputs a high-level signal to indicate that the circuit works normally. In fig. 3, signals of the data channel digital control circuit 2 are taken as an example for identification. The output of which is also controlled by a control signal Adjin from the outside and an Error signal Error from the data channel high common mode transient suppression differential signal receiving circuit 4. The protection channel digital control circuit 10 can also be implemented by the same digital control circuit, except that the connection signals Adjin, error and Din are not used.

Fig. 4 is a diagram of a modulation and transmission circuit according to the present invention, where a modulation scheme adopted by the circuit is pulse count modulation, and a method of describing a rising edge of an input signal with double pulses and a method of describing a falling edge of the input signal with single pulses are used to separate the rising edge and the falling edge of the input signal and generate corresponding pulse driving signals. The modulation transmitting circuit of the present invention adopts 2 sets of circuits shown in fig. 4, and signals in the figure are identified by taking the data channel modulation transmitting circuit 5 as an example: dxP is input data, R1 and R2 are high-frequency refresh signals, and the output is modulated pulse signal TxN. The refresh signals R1 and R2 respectively correspond to a refresh command signal of a falling edge single pulse and a rising edge double pulse, a circuit normally works when the signals are high, and a refresh operation is executed to refresh the circuit when the signals are low. Besides logic gate, the DELAY module for delaying is composed of inverter, capacitor and schmitt trigger. The specific length of the delay is controllable, and the delay time control can be realized by changing the size of the capacitor or the number of the inverters. The schmitt trigger is connected after the capacitor to avoid the influence of uncertainty caused by unstable voltage at two ends of the capacitor.

Because of the large voltage difference between the substrate potentials of the transmitting end circuit and the receiving end circuit, the high-voltage circuit and the low-voltage circuit must be electrically isolated. Because of the large difference in application scenarios of the power semiconductor device, the voltage difference VGND between the maximum values of the high and low voltage regions is equal to (VGND 1-VGND 2) and can span from 40V to 6500V. The VGND directly determines the electrical isolation level inside the chip, and realizes different levels of electrical isolation constituent circuits inside the chip, so that the technology and the cost quality level of the adopted circuit devices have great difference. The invention adopts the insulating isolation technology of capacitance isolation to isolate the high-low voltage signal processing circuit in physical space, thereby realizing ultra-high voltage electric isolation exceeding 3000V.

In the implementation of the invention shown in fig. 1, the transmitting-side circuit and the receiving-side circuit are connected to the ground voltages Vgnd1 and Vgnd2, respectively, wherein an isolation circuit is provided to isolate the two ground voltages Vgnd1 and Vgnd2. However, since there is typically some degree of common mode transient noise between the two ground voltages Vgnd1 and Vgnd2, errors in the signal will occur during transmission. It is generally defined that the common mode transient noise VGND is equal to the voltage difference of (VGND 1-VGND 2) and will periodically ramp up from 0V to 1200V and then ramp down from 1200V to 0V for a typical application scenario of a 1200V SiC MOSFET. Then, under the interference of the common mode transient noise VGND, the voltage of the receiving terminal Vcm (vcm= (RxP +rxn)/2) will generate a spike error, which inevitably causes the data error of the receiving terminal circuit, and the influence of the common mode transient noise will further worsen as the switching frequency increases. Therefore, in order to realize high-reliability driving of the SiC MOSFET device and effectively inhibit common-mode transient noise, the invention adopts a high-common-mode transient inhibition differential signal receiving circuit.

In the invention, the protection channel high common mode transient suppression differential signal receiving circuit 6 and the data channel high common mode transient suppression differential signal receiving circuit 4 are realized by adopting the same high common mode transient suppression differential signal receiving circuit. Fig. 5 is a block diagram of a high common mode transient suppression differential signal receiving circuit of the present invention, where signals are identified by taking a protection channel high common mode transient suppression differential signal receiving circuit 6 as an example, the circuit includes: the differential input receiving circuit 1, the common mode adjustable amplifying circuits 602 (CM 1 to CMX) cascaded in tandem of the X stage, the high sensitivity common mode adjustable amplifying circuit 603 (CMN), the first output shaping circuit 604, and the common mode adaptive adjusting circuit 605. The differential input receiving circuit 1 firstly receives differential signals (a positive end receiving signal RxP and a negative end receiving signal RxN) coupled by the transmitting end circuit shown in fig. 2 through the isolating circuit 10, and obtains a positive end input signal Vip and a negative end input signal Vin through filtering processing; the Vip and Vin enter a first pole common mode adjustable amplifying circuit CM1 of the X-stage tandem common mode adjustable amplifying circuit 602, and finally a positive end output signal VoXp and a negative end output signal VoXn of the X-stage common mode adjustable amplifying circuit are obtained; voXp and VoXn are respectively connected to the positive input terminal and the negative input terminal of the high-sensitivity common-mode adjustable amplifying circuit 603 (CMN), so as to obtain differential output signals (a positive output signal VoNp and a negative output signal VoNn) of the high-sensitivity common-mode adjustable amplifying circuit 603; the first output shaping circuit 604 processes the resulting data output Dout according to the sizes VoNp and VoNn. The common mode adaptive adjustment circuit 605 adaptively generates common mode adjustment signals C11, C12, C21, C22, …, CX1, CX2, CN1, CN2 for each stage of amplifying circuit according to the changes of the power supply and ground voltage signals, and the common mode adjustment signals C11 and C12 generated by the common mode adaptive adjustment circuit 605 are respectively connected to the common mode adjustment signal input terminal of the first stage common mode adjustable amplifying circuit CM 1; the common mode adjustment signal C21 and the common mode adjustment signal C22 are respectively connected to the common mode adjustment signal input end of the second-stage common mode adjustable amplifying circuit CM 2; … … by analogy, the common mode adjustment signal CX1 and the common mode adjustment signal CX2 are respectively connected to the common mode adjustment signal input of the X-th stage common mode adjustable amplifying circuit CMX; the common mode adjustment signal CN1 and the common mode adjustment signal CN2 are connected to the common mode adjustment signal input terminal of the high-sensitivity common mode tunable amplifier circuit 603 (CMN), respectively. Wherein X is a positive integer greater than 1, and N is a positive integer greater than X.

In fig. 5, the common-mode adaptive adjustment circuit 605 automatically detects the magnitude of transient common-mode noise caused by the fluctuation of the power supply voltage VDD and the ground voltage Vgnd2 of the receiving circuit, and adjusts the values of the common-mode adjustment signals C11, C12, C21, C22, …, CX1, CX2, CN1, CN2 and correspondingly outputs the values to the common-mode adjustable amplification circuits CM1 to CMX and the high-sensitivity common-mode adjustable amplification circuit 603 (CMN) of the tandem cascade of the X stages when the transient common-mode noise exceeds a certain threshold value, so as to adjust the common-mode levels of the common-mode adjustable amplification circuits CM1 to CMX and the high-sensitivity common-mode adjustable amplification circuit 3 of the tandem cascade of the X stages to compensate the influence of the transient common-mode noise. In addition to the common mode adaptive adjustment, the present invention further employs a high reliability first output shaping circuit 604, and employs RC low pass filtering and schmitt trigger combination filtering to filter out the influence of high frequency noise, so as to obtain the data output Dout that is not influenced by transient common mode noise.

Fig. 6 shows an implementation of a differential input receiving circuit 601 according to the present invention, which is composed of a positive side isolation capacitor C51, a positive side ground resistor R51, a positive side coupling capacitor C52, a positive side common mode resistor R53, a negative side isolation capacitor C53, a negative side ground resistor R52, a negative side coupling capacitor C54, a negative side common mode resistor R54, and a receiving common mode generating circuit 6011. The left end of the positive end isolation capacitor C51 and the left end of the negative end isolation capacitor C53 are respectively connected to a positive end receiving signal RxP and a negative end receiving signal RxN; the right end of the positive end isolation capacitor C51 is connected to the lower end of the positive end grounding resistor R51 and the left end of the positive end coupling capacitor C52; the right end of the negative end isolation capacitor C53 is connected to the lower end of the negative end grounding resistor R52 and the left end of the negative end coupling capacitor C54; the right end of the positive end coupling capacitor C52 is connected to the upper end of the positive end common mode resistor R53 and is used as the output end of the positive end input signal Vip; the right end of the negative end coupling capacitor C54 is connected to the lower end of the negative end common mode resistor R54 and is used as the output end of a negative end input signal Vin; the lower end of the positive-side common-mode resistor R53 and the upper end of the negative-side common-mode resistor R54 are connected, and are simultaneously connected to the common-mode output terminal Vicm of the reception common-mode generating circuit 6011.

In the circuit shown in fig. 6, the positive-side isolation capacitor C51 and the negative-side isolation capacitor C53 are both high-voltage capacitors, and the size of the capacitors is typically several tens of fp; the positive side coupling capacitor C52 and the negative side coupling capacitor C54 are both low-voltage capacitors, and the capacitance values thereof are relatively small. The positive end receiving signal RxP and the negative end receiving signal RxN are input to output, and the positive end input signal Vip and the negative end input signal Vin are obtained through 2-stage direct-isolation coupling filtering. The common mode level of the positive input signal Vip and the negative input signal Vin is provided by the receive common mode generation circuit 6011.

Fig. 7 is a schematic diagram of an implementation of the receive common mode generation circuit 6011 of the present invention. The circuit is composed of an NMOS tube M60, an NMOS tube M61, a PMOS tube M62, an NMOS tube M63, a PMOS tube M64, a PMOS tube M65, an NMOS tube M66, an NMOS tube M67, a PMOS tube M68, an NMOS tube M69, a PMOS tube M610, an NMOS tube M611, a PMOS tube M612, an NMOS tube M613, an NMOS tube M614, a PMOS tube M615 and a resistor R61; the PMOS transistor M64, the PMOS transistor M65, the NMOS transistor M66, the NMOS transistor M67, the PMOS transistor M68, and the NMOS transistor M69 form the schmitt trigger 600.

The grid electrode of the NMOS tube M60 is connected to an input common mode voltage Vcm; the drain electrode of the NMOS tube M60 is connected to the drain electrode and the grid electrode of the PMOS tube M62 and the grid electrode of the NMOS tube M63; the grid electrode of the NMOS tube M61 is connected to an input common mode control signal Vctrl; the drain electrode of the NMOS tube M61 is connected with the drain electrode of the NMOS tube M63 and is connected to the input end of the Schmitt trigger 600; the output end of the schmitt trigger 600 is simultaneously connected to the gates of the PMOS transistor M610, the NMOS transistor M611, the PMOS transistor M612 and the NMOS transistor M613; the drain electrode of the PMOS tube M610 is connected with the drain electrode of the NMOS tube M611 and is also connected to the grid electrode of the NMOS tube M614; the drain electrode of the PMOS tube M612 is connected with the drain electrode of the NMOS tube M613 and is also connected to the grid electrode of the PMOS tube M615; the source electrode of the NMOS tube M614 is connected with the source electrode of the PMOS tube M615 and is also used as an output port of the common mode output end Vicm; the drain of the NMOS tube M614 is connected to the high input common mode level Vcmh, and the drain of the PMOS tube M615 is connected to the low input common mode level Vcml; the source electrode of the NMOS tube M613 is connected to the upper end of the resistor R61; the source of NMOS tube M60, the source of NMOS tube M61, the source of NMOS tube M611 and the lower end of resistor R61 are connected to the ground voltage; the source of the PMOS transistor M62, the source of the NMOS transistor M63, the source of the PMOS transistor M64, and the source of the PMOS transistor M610 are simultaneously connected to the power supply voltage. The ground terminals of this circuit are each connected to receive the circuit ground voltage.

The circuit shown in fig. 7 has the function of dynamically tracking and adjusting the magnitude of the common mode output end Vicm according to the change of the input common mode Vcm, so as to reduce the influence of the input common mode. Assuming that the input common mode Vcm decreases, the input terminals of the schmitt trigger 600 will decrease synchronously, and assuming that the fluctuation exceeds the threshold of the schmitt trigger 600, the output of the schmitt trigger 600 will become high level, the PMOS tube M615 will be turned on, the common mode output terminal Vicm will output the low input common mode level Vcml, so that it matches and inputs the common mode variation; assuming that the input common mode Vcm increases and exceeds the threshold of the schmitt trigger 600, the NMOS transistor M614 is turned on and the common mode output terminal Vicm will output a high input common mode level Vcmh; it can be seen that the circuit of fig. 7 can achieve dynamic compensation of input common mode variations for different input common mode fluctuations. In the circuit shown in fig. 7, in order to make the common mode output end Vicm better realize the common mode signal output, an NMOS transistor is used to transmit the high input common mode level Vcmh, and a PMOS transistor is used to transmit the low input common mode level Vcml.

Fig. 8 is a schematic diagram of one implementation of a cascode circuit of the present invention. The circuit is a fully differential single-stage amplifying circuit, and the left side of the circuit comprises a PMOS tube M71 and an NMOS tube M73 which are connected in series through drain electrodes; the source electrode of the PMOS tube M71 is connected with a power supply VDD, a capacitor C71 is connected between the grid electrode and the source electrode of the PMOS tube M71, and a bias resistor R71 is connected between the grid electrode and the drain electrode of the PMOS tube; the drain electrode of the NMOS tube M73 outputs a negative end output signal Vo1n connected to the negative input end of the next cascade unit (the second cascade unit outputs a negative end output signal Vo2n to the next cascade unit, and so on), and the gate electrode of the NMOS tube M73 is connected to the positive input end Vip of the common mode adjustable amplifying circuit 602; the right side of the circuit includes: PMOS tube M72 and NMOS tube M74 connected in series through drain electrode; the source electrode of the PMOS tube M72 is connected with a power supply VDD, a capacitor C72 is connected between the grid electrode and the source electrode of the PMOS tube M72, and a bias resistor R72 is connected between the grid electrode and the drain electrode of the PMOS tube M72; the drain electrode of the NMOS tube M74 outputs a positive output signal Vo1p to the positive input end of the next cascade unit (the second cascade unit outputs a positive output signal Vo2p to the next cascade unit, and so on), and the gate electrode of the NMOS tube M74 is connected to the negative input end Vin of the common-mode adjustable amplifying circuit 602; the sources of the PMOS tube M71 and the PMOS tube M72 on two sides of the amplifying circuit are connected in parallel, and the sources of the NMOS tube M73 and the NMOS tube M74 are connected in parallel; the sources of the NMOS tube M73 and the NMOS tube M74 are connected with the drains of the NMOS tube M75, the NMOS tube M76 and the NMOS tube M77 which are grounded; the grid electrode of the grounded NMOS tube M75 is connected with bias voltage Vb1 to provide bias current required by normal operation of the amplifier; the gates of the NMOS transistors M76 and M77 are connected to common mode adjustment signals C11 and C12, respectively.

As can be seen from the circuit of fig. 8, by changing the magnitudes of the common mode adjustment signals C11 and C12, the bias currents flowing through the NMOS transistor M73 and the NMOS transistor M74 are changed, and the output voltages of the negative end output signal Vo1n and the positive end output signal Vo1p of the cascade unit are correspondingly changed at the same time, so that the adjustment of the output common mode voltage is realized. The invention adopts the cascade connection of the same common mode adjustable amplifying circuit with the multistage as shown in fig. 9, and the X-th stage common mode adjustable amplifying circuit CMX outputs the positive end output signal VoXp and the negative end output signal VoXn, thereby finally realizing the dynamic compensation of common mode noise.

Fig. 9 shows an implementation of the high sensitivity common mode tunable amplifying circuit 603 of the present invention. The circuit is a front-back two-stage fully-differential amplifying circuit, the front-stage common-mode adjustable amplifying circuit adopts an amplifying circuit structure similar to that of fig. 9, and the rear-stage amplifying circuit is a differential amplifying circuit (DDA). The positive input end of the front-stage common-mode adjustable amplifying circuit is the positive input end of the high-sensitivity common-mode adjustable amplifying circuit 603, and the negative input end of the front-stage common-mode adjustable amplifying circuit is the negative input end of the high-sensitivity common-mode adjustable amplifying circuit 603; the positive output end VoNp of the differential amplification circuit is the positive output end of the high-sensitivity common-mode adjustable amplification circuit 603, and the negative output end VoNn of the differential amplification circuit is the negative output end of the high-sensitivity common-mode adjustable amplification circuit 603.

The left side of the front-stage common mode adjustable amplifying circuit comprises a PMOS tube M81 and an NMOS tube M83 which are connected in series through drain electrodes; the source electrode of the PMOS tube M81 is connected with the power supply VDD, a capacitor C81 is connected between the grid electrode and the source electrode of the PMOS tube M81, the grid electrode of the PMOS tube M81 is also connected to the upper end of the bias resistor R81, and the drain electrode of the PMOS tube M81 is also connected to the lower end of the bias resistor R82; the lower end of the bias resistor R81 is connected with the upper end of the bias resistor R82 and is also used as a first signal input end of the differential amplifying circuit; the drain electrode of the NMOS tube M83 is connected with the drain electrode of the PMOS tube M81 and is also connected with the third signal input end of the differential amplification circuit; the grid electrode of the NMOS tube M83 is connected with the positive input end VoXp of the front-stage common mode adjustable amplifying circuit; the right side of the circuit comprises a PMOS tube M82 and an NMOS tube M84 which are connected in series through drain electrodes; the source electrode of the PMOS tube M82 is connected with a power supply VDD, a capacitor C82 is connected between the grid electrode and the source electrode of the PMOS tube M82, the grid electrode of the PMOS tube M82 is also connected to the upper end of a bias resistor R83, and the drain electrode of the PMOS tube M82 is also connected to the lower end of the bias resistor R84; the lower end of the bias resistor R83 is connected with the upper end of the bias resistor R84 and is also used as a second signal input end of the differential amplifying circuit; the drain electrode of the NMOS tube M84 is connected with the drain electrode of the PMOS tube M82 and is also connected to the fourth signal input end of the differential amplification circuit; the grid electrode of the NMOS tube M84 is connected with the negative input end VoXn of the front-stage common mode adjustable amplifying circuit; the sources of the PMOS tube M81 and the PMOS tube M82 on two sides of the amplifying circuit are connected in parallel, and the sources of the NMOS tube M83 and the NMOS tube M84 are connected in parallel; the sources of the NMOS tube M83 and the NMOS tube M84 are connected with the drains of the NMOS tube M85, the NMOS tube M86 and the NMOS tube M87 which are grounded; the grid electrode of the grounded NMOS tube M85 is connected with bias voltage Vb1 to provide bias current required by normal operation of the amplifier; the gates of the NMOS transistors M86 and M87 are connected to common mode adjustment signals CN1 and CN2, respectively.

The differential amplification circuit internally includes: PMOS tube M88, PMOS tube M89, PMOS tube M812, PMOS tube M813, NMOS tube M810, NMOS tube M811, NMOS tube M814, NMOS tube M815 and resistor 85; the grid electrode of the PMOS tube M88 is a first signal input end of the differential amplification circuit, the grid electrode of the PMOS tube M89 is a second signal input end of the differential amplification circuit, the PMOS tube M812 is a third signal input end of the differential amplification circuit, and the PMOS tube M813 is a fourth signal input end of the differential amplification circuit; the drain electrode of the PMOS tube M88 is connected with the drain electrode of the PMOS tube M89 and is connected to the drain electrode of the NMOS tube M810, and is used as the positive output end VoNp of the differential amplifying circuit; the drain electrode of the PMOS tube M812 is connected with the drain electrode of the PMOS tube M813 and is connected to the upper end of the resistor R85; the lower end of the resistor R85 is connected with the drain electrode of the NMOS tube M814 and is used as the negative output end VoNn of the differential amplifying circuit; the NMOS tube M810 and the NMOS tube M811 form a cascode current source structure, the NMOS tube M814 and the NMOS tube M815 form a cascode current source structure, the gates of the NMOS tube M810 and the NMOS tube M814 are connected with the same bias voltage Vb81, and the gates of the NMOS tube M811 and the NMOS tube M815 are connected with the same bias voltage Vb82.

Fig. 10 is an implementation manner of the first output shaping circuit 604 according to the present invention, including a PMOS transistor M401, a PMOS transistor M402, a PMOS transistor M403, a PMOS transistor M404, a PMOS transistor M405, a PMOS transistor M406, a PMOS transistor M409, an NMOS transistor M407, an NMOS transistor M408, an NMOS transistor M4010, a resistor R401, a resistor R402, a PMOS transistor M41, a PMOS transistor M43, a PMOS transistor M45, a PMOS transistor M46, a PMOS transistor M49, a PMOS transistor M411, an NMOS transistor M42, an NMOS transistor M44, an NMOS transistor M47, an NMOS transistor M48, an NMOS transistor M410, an NMOS transistor M412, a resistor R41, a resistor R42, and a capacitor C41.

The PMOS tube M401, the PMOS tube M402, the PMOS tube M403, the PMOS tube M404, the PMOS tube M405, the PMOS tube M406, the PMOS tube M409, the NMOS tube M407, the NMOS tube M408, the NMOS tube M4010, the resistor R401 and the resistor R402 form a three-stage comparator; the PMOS tube M41, the PMOS tube M43, the NMOS tube M42, the NMOS tube M44, the resistor R41, the resistor R42 and the capacitor C41 form a buffer with RC filtering function; the PMOS tube M45, the PMOS tube M46, the PMOS tube M49, the NMOS tube M47, the NMOS tube M48 and the NMOS tube M410 form a Schmidt trigger; the PMOS transistor M411 and the NMOS transistor M412 form an output inverter. The input end of the buffer with the RC filtering function is connected to the comparison output voltage Vo1 of the wide voltage range comparator circuit, the output end of the buffer with the RC filtering function is connected to the input end of the Schmitt trigger, the output end of the Schmitt trigger is connected to the input end of the output inverter, and the output end of the output inverter is the final data output Dout of the high common mode transient suppression differential signal receiving circuit 6.

The internal circuit structure of the three-stage comparator is as follows: the PMOS tube M401, the PMOS tube M402, the PMOS tube M403, the resistor R401 and the resistor R402 form an input stage of the three-stage comparator, the PMOS tube M404, the PMOS tube M405, the PMOS tube M406, the NMOS tube M407 and the NMOS tube M408 form an amplifying stage of the three-stage comparator, and the PMOS tube M409 and the NMOS tube M4010 form an output stage of the three-stage comparator; the connection relation of the internal circuit of the buffer with the RC filter function is as follows: the gates of the PMOS tube M41 and the NMOS tube M42 are simultaneously connected to the comparison output voltage of the three-stage comparator, the drains of the PMOS tube M41 and the NMOS tube M42 are simultaneously connected to the gates of the PMOS tube M43 and the NMOS tube M44, the drain of the PMOS tube M43 is connected to the upper end of the resistor R41, the lower end of the resistor R41 is connected to the upper end of the resistor R42, the upper end of the capacitor C41 and the input end of the Schmitt trigger, the lower end of the resistor R42 is connected to the drain of the NMOS tube M44, the simultaneous sources of the PMOS tube M41 and the PMOS tube M43 are connected to the power supply voltage, and the sources of the NMOS tube M42 and the NMOS tube M44 and the lower end of the capacitor C41 are simultaneously connected to the ground voltage.

The first output shaping circuit 604 of the present invention shown in fig. 10 provides, on the one hand, a three-stage comparator to convert the input differential signal into a standard digital logic signal Dout; on the other hand, RC low-pass filtering and Schmitt trigger combined filtering are adopted, and certain hysteresis is kept for effectively filtering out high-frequency interference influence caused by common-mode noise.

Fig. 11 shows a specific implementation of the common mode adaptive adjustment circuit 605 according to the present invention, which includes a first common mode detection circuit 100, a common mode detection signal transmission circuit 101, an adjustment common mode signal generation circuit 102, and a common mode adjustment signal selection circuit 103. The first common mode detection circuit 100 is configured to detect power supply and substrate noise, and change the magnitude of a common mode detection signal vcm_det when the noise is greater than a certain threshold, where the common mode detection signal vcm_det is connected to the common mode detection signal transmission circuit 101, and the vcm_det generates a common mode selection switch control signal N11, N12, N21, N22, …, NX1, NX2, and NN1, NN2 through the common mode detection signal transmission circuit 101, and outputs the common mode adjustment signal selection signal to the common mode adjustment signal selection circuit 103; the common mode adjustment signal selection circuit 103 generates and adjusts the magnitudes of the common mode adjustment signals C11, C12, C21, C22, …, CX1, CX2, and CN1, CN2 according to the common mode selection switch control signal, and outputs them; the common mode adjustment signal generation circuit 102 is configured to generate various common mode bias signals required by the common mode adjustment signal selection circuit 103, and output the generated common mode bias signals to the common mode adjustment signal selection circuit 503.

In the circuit shown in fig. 11, the common mode detection signal transmission circuit 101 is implemented by using a distributed inverter chain, and the common mode detection signal vcm_det propagates through the distributed N groups of inverter chains to obtain N groups of common mode control signals. The regulated common mode signal generating circuit 102 generates a high input common mode level Vcmh and a low input common mode level Vcml from one bias signal path of the supply voltages VDD to SW. For Vcmh and Vcml implementations, a minimum hardware cost implementation is shown in the figure, and the same functions can be implemented by using other circuits such as reference voltage division or LDO, which are not described here. The internal circuit of the common mode adjustment signal selection circuit 103 is a switch selection array, and the switch array determines the outputs of the common mode adjustment signals C11, C12, C21, C22, …, CX1, CX2 and CN1, CN2 according to the values of the common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2 and NN1, NN 2.

Fig. 12 and 13 show the implementation manner and the operation waveforms of the common mode detection circuit according to the present invention. The common mode detection circuit is used for detecting power supply and substrate noise, and changing the magnitude of a common mode detection signal vcm_det when the noise is larger than a certain threshold value so as to control the output of the common mode adaptive adjustment circuit shown in fig. 11. The common mode detection circuit is composed of a PMOS tube M111, a PMOS tube M112 and an NMOS tube M113; the grid electrode and the drain electrode of the PMOS tube M111 are connected and connected to the drain electrode of the PMOS tube M112 and the grid electrode of the NMOS tube M113; the grid electrode of the PMOS tube M112 is connected with the drain electrode of the NMOS tube M113 and is used as an output node of the common mode detection signal Vcm_det; the sources of the PMOS tube M111 and the PMOS tube M112 are connected with a power supply voltage, and the source of the NMOS tube M113 is connected with a ground voltage.

Taking the operating voltage of the first common mode detection circuit 100 as an example. The typical high-voltage half-bridge gate driving circuit is divided into a high-side driving circuit channel and a low-side driving circuit channel, and the high-side driving circuit realizes signal transmission control in a bootstrap boosting mode. Assuming that the circuit is operated in a high-side drive circuit of the half-bridge gate drive chip, vgnd2 is connected with half-bridge output SW, SW swinging between 0 and Vgnd; VDD is connected to the power supply voltage VHB of the high-side driving circuit, and VHB is bootstrapped and floated by the bootstrap capacitor on the basis of the SW potential, so that the bootstrap voltage vdd=vhb=sw+vcc in normal operation. Because the capacitor bootstrapping charges also needs a certain charging time, in the capacitor charging process, the bootstrap voltage can not completely synchronize the fluctuation of SW, which leads to a certain delay of VDD relative to SW, the voltage difference between the power supply and the ground in the delay interval is not strictly equal to VCC, which is equivalent to the common mode noise of the power supply, and the noise amplitude is large enough to influence the circuit function, so that the false triggering of the comparator is generated.

As shown in the right waveform of fig. 13, when the half-bridge output SW is stable, the VDD and Vgnd2 voltages are in a stable state, M111 is turned on, M113 is turned on, vcm_det will be pulled down to Vgnd2 by M113, and at a low level; when the half-bridge output SW is switched from 0 to VGND, the VGND2 voltage is synchronously switched to VGND, but VDD has a certain delay, a certain delay interval is generated, VDD does not reach vgnd+vcc in the delay interval, the gate voltage of M113 is insufficient to turn on M113, M113 will be turned off, vcm_det will be influenced by VGND2 to generate a spike high pulse under the effect of parasitic capacitance until VDD reaches vgnd+vcc, at this time, M113 is turned back on, vcm_det will be pulled down to VGND2 by M113.

As shown in FIG. 1, the overall isolation of the capacitor isolation SiC MOSFET driving chip of the invention is realized by two groups of isolation capacitors (Ctp and Crp form a group of P-end series isolation capacitors and Ctn and Crn form a group of N-end series isolation capacitors) which are arranged in series, and the middle is connected with the upper polar plates of the two series isolation capacitors through a Bonding wire (Bonding wire), so that the overall voltage resistance of the capacitor isolator chip is the sum of the voltage resistance of the two capacitors in the series capacitors. In general, the withstand voltage of SiO ₂ is about 500V/um, and in a general CMOS process with 0.18um, if the first layer M1 is used as the lower electrode plate of the isolation capacitor and the sixth layer M6 is used as the upper electrode plate of the isolation capacitor, the total thickness of SiO ₂ between the metal layers is about 6-7 um, that is, the withstand voltage of a single isolation capacitor is about 3000V-3500V, and the withstand voltages of two isolation capacitors are about 6000V-7000V. The withstand voltage can meet the common and conventional application, and cannot meet the withstand voltage requirement of ultrahigh voltage isolation.

As shown in fig. 14, the present invention provides an ultra-high withstand voltage separating capacitor comprising: the deep N well isolation region DNWELL 50, a lower electrode plate (a first layer M1) 51, an upper electrode plate 54, and a SiO ₂ layer 52 and a passivation layer 53 which are arranged between the lower electrode plate 51 and the upper electrode plate 54 from bottom to top, wherein the passivation layer 53 is a superposition of SiO ₂ and Si ₃N₄. The thickness of the SiO ₂ layer is mainly VIA12, M2 (second layer), VIA23, M3 (third layer), VIA34, M4 (fourth layer), VIA45, M5 (fifth layer), VIA56, M6 (sixth layer), the sum thickness is 8-9 um, and the thickness of the passivation layer 53 is 2-3 um. Si ₃N₄ in the passivation layer 53 is disposed superimposed over SiO ₂ because Si ₃N₄ has better compactness and pressure resistance than SiO ₂. The upper plate 54 is made of metal Cu, and the upper plate 54 is formed by processing the rear end of the wafer, and a layer of metal Cu is formed on the passivation layer 53, and the metal Cu also serves as a PAD. A deep N-well isolation region DNWELL 50 is under the lower plate 51, and a substrate of a wafer is under the deep N-well isolation region 50; the deep N-well isolation region 50 should have an area larger than the planar area of the lower plate 51 and entirely cover the lower surface of the lower plate 51.

According to the ultrahigh voltage-resistant isolation capacitor scheme provided by the invention, the thickness of the passivation layer is controlled to be about 2.5um through process adjustment, the thickness of a single isolation capacitor is about 12um, and the voltage-resistant value can reach 6000V, so that the total thickness of two isolation capacitors connected in series is about 24um, the total voltage-resistant value can reach 12000V, the requirement of enhancing isolation can be met, the capacitance value of the isolation capacitor is reduced after thickening, the area of an isolation capacitor polar plate can be properly increased, the capacitance value of the isolation capacitor is basically kept unchanged, and the transmission quality of the whole isolation signal is not affected.

The low voltage supply circuit is a basic functional module which any analog IC must be equipped with, and a block diagram of an implementation structure which can be used by the transmitting side low voltage generation circuit 3 and the receiving side low voltage generation circuit 8 of the present invention is shown in fig. 15. The circuit internally comprises: a start-up circuit 801, a bandgap reference voltage generation circuit 802, a reference voltage generation circuit 803, a bias signal generation circuit 804, and an input low voltage generation circuit 805. Taking the transmitting end low voltage generating circuit 3 as an example, after the VCC voltage of the chip is powered on, the starting circuit 801 is the circuit that is started first in the whole chip, and the starting circuit generally provides a certain initial bias signal to generate a fixed reference voltage and a fixed reference current for the bandgap reference voltage generating circuit 802; the reference voltage is then used for generating various reference voltages V _R1、V_R2～V_Rn required by the internal work of the chip through a reference voltage generating circuit and is output through a buffer circuit; the reference current typically goes into bias signal generation circuit 804, which generates various bias signals for biasing other analog circuits in the chip, as well as bias to reference voltage generation circuit and input low voltage generation circuit 805. The input low voltage generation circuit 805 typically generates a 3-10V floatable low voltage power supply voltage VCL.

Fig. 16 is a block diagram of an over-temperature protection circuit of the present invention with high accuracy and wide voltage range. The circuit of the present invention includes a clamp 1401, a temperature sensing circuit 1402, a wide voltage range comparator circuit 1403 and a second output shaping circuit 1404. The temperature detection circuit 1402 obtains a first temperature detection output signal Vin1 and a second temperature detection output signal Vin2 according to the bias voltage Vb provided by the clamp circuit 1401; the wide voltage range comparator circuit 1403 compares the first temperature detection output signal Vin1 with the second temperature detection output signal Vin2 to obtain a comparison output signal Vo1; the second output shaping circuit 1404 processes the comparison output signal Vo1 to obtain a temperature protection signal OTLock and an OTP, and OTLock is a digital logic signal, OTLock is connected to the clamp circuit 1401 for controlling the magnitude of the bias voltage Vb, and the OTP is output to the digital control circuit as a control signal.

When the chip temperature is normal, the temperature protection signal OTLock is at high level, and the OTLock high level controls the clamp circuit 1401 to generate a higher bias voltage Vb; the temperature detection circuit 1402 generates a first temperature detection output signal Vin1 and a second temperature detection output signal Vin2 according to the bias voltage Vb and the temperature signal. The comparison output signal Vo1 obtained from the first temperature detection output signal Vin1 and the second temperature detection output signal Vin2 by the wide voltage range comparator circuit 1403 under normal conditions should be a high level signal; the second output shaping circuit 1404 processes the comparison output signal Vo1 to obtain the temperature protection signal OTLock as a high level logic signal.

When the chip temperature is abnormal, the first temperature detection output signal Vin1 and the second temperature detection output signal Vin2 generated by the temperature detection circuit 1402 will change, the wide voltage range comparator circuit 1403 changes the comparison output signal Vo1 obtained by the first temperature detection output signal Vin1 and the second temperature detection output signal Vin2 to a low level signal, the temperature protection signal OTLock obtained by the second output shaping circuit 1404 also changes to a low level logic signal, the temperature protection signal OTLock changes to a low level, the OTLock low level will control the clamp circuit 1401 to generate a lower bias voltage Vb, the bias voltage Vb will further change the magnitudes of the first temperature detection output signal Vin1 and the second temperature detection output signal Vin2, so that the comparison output signal Vo1 of the wide voltage range comparator circuit 1403 is further locked to a low level signal.

Since the high-voltage gate driving chip normally works, the power supply voltage and the substrate potential of the high-voltage gate driving chip generally have huge fluctuation, and very serious common mode noise is generated. In order to overcome the serious influence of common mode noise, on one hand, the invention adopts the wide voltage range comparator circuit 1403 to compare the first temperature detection output signal Vin1 and the second temperature detection output signal Vin2 generated by the temperature detection circuit 1402, the wide voltage range comparator circuit 1403 can automatically detect common mode noise generated by the power supply voltage and the substrate potential, and when the common mode noise exceeds a certain threshold value, the output of the wide voltage range comparator circuit 1403 is automatically closed, so that the effectiveness of the comparison output signal Vo1 is not influenced by the common mode noise. On the other hand, the second output shaping circuit 1404 further employs RC low-pass filtering and schmitt trigger combined filtering to filter out the effects of high frequency noise, thereby producing a stable and reliable temperature-protected output signal OTLock.

FIG. 17 shows an implementation of a clamp 1401, which is composed of a PMOS tube M11, an NMOS tube M12, an NMOS tube M13, a resistor R11, a resistor R12 and a resistor R13; the source electrode of the PMOS tube M11 is connected with the upper end of the resistor R11 and is simultaneously connected to the power supply voltage; the grid electrode of the PMOS tube M11 is connected with the grid electrode of the NMOS tube M12 and is simultaneously connected with a temperature protection signal OTLock; the drain electrode of the PMOS tube M11 is connected with the drain electrode of the NMOS tube M12 and is simultaneously connected with the grid electrode of the NMOS tube M13; the source electrode of the NMOS tube M12 is connected with the lower end of the resistor R13 and the source electrode of the NMOS tube M13 and is simultaneously connected to the ground voltage; the drain electrode of the NMOS tube M13 is simultaneously connected with the upper end of the resistor R13 and the lower end of the resistor R12; the upper end of the resistor R12 is connected to the lower end of the resistor R11, and serves as a bias voltage Vb output node of the clamp circuit 1401.

In the clamp circuit 101, the power supply voltage VCC is detected by the voltage dividing resistors R11, R12 and R13 in real time, the voltage value Vb obtained by the voltage division is input into the temperature detecting circuit 1402, the resistance value of R13 is controlled by M13, and the on and off of M13 is controlled by OTLock signals. When OTLock signal is high level, the grid of M13 is low, M13 is in off state, R13 is large resistance, and voltage value Vb obtained by voltage division is high bias voltage; when OTLock is low, the gate of M13 is high, M13 is on, R13 is shorted by M13 to a small resistance, and the divided voltage value Vb is a low bias voltage.

FIG. 18 shows an implementation of a temperature sensing circuit 1402 according to the present invention, which is composed of a PMOS tube M21, a PMOS tube M22, a resistor R21, a triode Q1 and a triode Q2; the base electrodes of the triode Q1 and the triode Q2 are connected and connected to a bias voltage Vb output node of the clamping circuit 101; the emitter of the triode Q1 is connected to the grid electrode and the drain electrode of the PMOS tube M21, and the node voltage of the triode Q is used as a first temperature detection output signal Vin1; the emitter of the triode Q2 is connected to the grid electrode and the drain electrode of the PMOS tube M22, and the node voltage of the triode Q is used as a second temperature detection output signal Vin2; the source electrode of the PMOS tube M21 is connected with the source electrode of the PMOS tube M22 and is connected to the power supply voltage; the collector of the triode Q2 is connected to the upper end of a resistor R21; the lower end of the resistor R21 is connected to the collector of the transistor Q1 and to the ground voltage GND. The width-to-length ratio of the PMOS transistor M21 and the PMOS transistor M22 is equal, and the base area ratio of the transistor Q1 and the transistor Q2 is 1: n (N is a natural number).

The principle adopted in the circuit temperature detection in fig. 18 is that the triode Vbe junction voltage has a negative temperature coefficient characteristic, and the negative temperature coefficients of the Vbe junctions with different current densities are different, so that under the same bias voltage condition, a voltage difference is generated by the voltages generated on the two Vbe junctions with different current densities along with the change of temperature, and the voltage difference is in a linear increasing relation along with the change of temperature. In fig. 18, the base area ratio of transistor Q1 to transistor Q2 is 1: n, the emitters of the two emitters respectively output voltages, and the first temperature detection output signal Vin1 and the second temperature detection output signal Vin2 will generate a voltage difference vt=vjn1-vjn2 that varies linearly with temperature. By adjusting the size of resistor R21, vt is set to a negative value less than 0 when the temperature is low; when the temperature increases, the value of the second temperature detection output signal Vin2 will decrease at a faster rate due to the larger base area of the transistor Q2, and the voltage difference Vt will increase with the temperature increase; when the temperature exceeds a certain value, vt will be changed from negative voltage to positive voltage, and the comparison output voltage Vo1 of the wide voltage range comparator circuit 103 will change, and the output voltage Vo1 will change from high to low. When the base voltages Vb of transistors Q1 and Q2 decrease, the voltage difference Vt will further increase, thereby locking the comparison output voltage Vo1.

Fig. 19 shows an implementation manner of a wide voltage range comparator circuit 1403 according to the present invention, which is composed of a PMOS transistor M31, a PMOS transistor M33, a PMOS transistor M35, a PMOS transistor M36, a PMOS transistor M37, a PMOS transistor M39, an NMOS transistor M32, an NMOS transistor M34, an NMOS transistor M38, an NMOS transistor M310, and a second common mode detection circuit 1031. The grid electrode of the PMOS tube M31 is connected to the first temperature detection output signal Vin1, and the grid electrode of the PMOS tube M33 is connected to the second temperature detection output signal Vin2; the drain electrode of the PMOS tube M31 is connected to the drain electrode and the gate electrode of the NMOS tube M32, the gate electrode of the NMOS tube M34 and the gate electrode of the NMOS tube M310; the drain electrode of the PMOS tube M33 is connected to the drain electrode of the NMOS tube M34 and the grid electrode of the PMOS tube M37; the drain electrode of the PMOS tube M37 is connected to the drain electrode and the grid electrode of the NMOS tube M38, and the source electrode of the PMOS tube M37 is connected to the grid electrode of the PMOS tube M39 and the drain electrode of the PMOS tube M36; the source electrode of the PMOS tube M36 is connected to the drain electrode of the PMOS tube M35, and the grid electrodes of the PMOS tube M36 and the PMOS tube M35 are both connected to the output control signal of the common mode detection circuit 1031; the drain electrode of the PMOS tube M39 is connected to the drain electrode of the NMOS tube M310 and outputs a comparison output voltage Vo1; the sources of the PMOS tube M31, the PMOS tube M33, the PMOS tube M35 and the PMOS tube M39 are simultaneously connected to the power supply voltage; the sources of the NMOS transistors M32, M34, M38 and M310 are simultaneously connected to the ground voltage.

The second common mode detection circuit 1031 and its operation principle employed in fig. 19 of the present invention can employ the same implementation as in fig. 12. In the circuit shown in fig. 19, the gate control signals of the PMOS transistor M36 and the PMOS transistor M35 are the same common mode control signal vcm_det, and the second common mode detection circuit 1031 can automatically detect the common mode noise generated by the power voltage and the substrate potential, and change the common mode control signal vcm_det when the common mode noise exceeds a certain threshold. When the common mode noise amplitude and influence are limited and the threshold value is not exceeded, the common mode control signal Vcm_det is in a high level, the PMOS tube M36 and the PMOS tube M35 are in an off state, and the grid electrode of the PMOS tube M39 is controlled by the source electrode of the PMOS tube M37; when the amplitude of the common mode noise is abnormal and exceeds a threshold value, the common mode control signal Vcm_det is at a low level, the PMOS tube M36 and the PMOS tube M35 are in a conducting state, the grid of the PMOS tube M39 is pulled high and enters a closing state, and the comparison output voltage Vo1 is clamped to a low level, so that the normal operation of the comparator is prevented from being influenced by the common mode noise. The load resistors of the single-stage amplifying circuits adopted by the comparator circuit in fig. 19 are all realized by adopting active diodes, so that the comparator circuit can work under a very wide power supply voltage condition, and the applicable voltage condition of the circuit is further expanded.

Fig. 20 is an implementation of a second output shaping circuit 1404, which is substantially identical in structure to the output shaping circuit on the right side in fig. 10, and includes a buffer with an RC filtering function, a schmitt trigger, and an output inverter, which are sequentially connected. The output end of the schmitt trigger is connected to the input end of the output inverter, the output end of the output inverter is the temperature protection output signal OTLock, and the temperature protection output signal OTLock is output through one inverter to obtain an output signal OTP. The output shaping circuit of fig. 20, on the one hand, provides a standard digital logic signal, converting the comparison output voltage Vo1 into a standard digital logic signal temperature protection output signal OTLock; another aspect is to filter out high frequency interference effects caused by common mode noise and temperature fluctuations. The circuit adopts RC low-pass filtering and Schmitt trigger combined filtering, and maintains a certain hysteresis quantity to effectively prevent thermal shock of temperature, and prevent frequent system starting and shutdown when working at a certain temperature point, thereby causing adverse effect on the system.

Fig. 21 and 22 are respectively a structure diagram of an under-voltage protection circuit and an over-current protection circuit according to the present invention, and the circuit structures of the two protection circuits are similar to the structure of the over-temperature protection circuit shown in fig. 16, and each of them includes: a clamp circuit, a wide voltage range comparator circuit, and an output shaping circuit. Compared with the over-temperature protection circuit shown in fig. 16, the under-voltage protection circuit shown in fig. 21 is different in that a voltage detection circuit is adopted to detect the magnitude of a power supply voltage, and the obtained sampling voltage is compared with a reference voltage signal to obtain output under-voltage protection signals UVLO and UVlock signals; UVlock is connected to the clamp circuit for controlling the magnitude of the bias voltage Vb, and UVLO is outputted to the digital control circuit as a control signal. The voltage detection circuit can be realized by adopting a conventional resistor voltage division circuit. Compared with the over-temperature protection circuit shown in fig. 16, the over-current protection circuit shown in fig. 22 is different in that a current detection circuit is adopted to detect the current of an output power device, the obtained sampling current is generally converted into a voltage through a resistor, and the voltage is compared with a reference voltage signal to obtain output under-voltage protection signals OCP and OClock signals. OClock is connected to the clamp circuit for controlling the magnitude of the bias voltage Vb, and the OCP is outputted to the digital control circuit as a control signal.

Fig. 23 shows an implementation of the output driving circuit 7 according to the present invention. The power supply of the output driving circuit 7 also adopts VCC, the output driving circuit 7 is composed of a plurality of inverter chains with gradually amplified sizes and MOS tubes M221 and M222, the branches where the M221 and M222 tubes are located determine the output current of the driving circuit, and meanwhile, the output impedance of the circuit is also determined, so that the aspect ratio of the M221 and M222 is designed according to the requirements of the driving device. In order to make the SiC MOSFET device controlled by the output saturated on and off promptly, the output impedance of the output driving circuit 7 is required to be small and the output current to be large (several amperes).

The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims

1. High voltage insulation isolation SiC MOSFET gate drive circuit with protect function, characterized by including: the device comprises an input receiving circuit (1), a data channel digital control circuit (2), a data channel modulation transmitting circuit (5), a first high-voltage isolation circuit (11), a protection channel high-common mode transient suppression differential signal receiving circuit (6), a protection channel digital control circuit (10), a protection channel modulation transmitting circuit (9), a second high-voltage isolation circuit (12), a data channel high-common mode transient suppression differential signal receiving circuit (4), an output driving circuit (7), a transmitting end low-voltage generating circuit (3), a receiving end low-voltage generating circuit (8), a transmitting end undervoltage protection circuit (13), a transmitting end over-temperature protection circuit (14), a transmitting end over-current protection circuit (15), a receiving end undervoltage protection circuit (16), a receiving end over-temperature protection circuit (17) and a receiving end over-current protection circuit (18);

The input receiving circuit (1), the data channel digital control circuit (2), the data channel modulation transmitting circuit (5), the data channel high common mode transient suppression differential signal receiving circuit (4), the transmitting end undervoltage protection circuit (13), the transmitting end overtemperature protection circuit (14), the transmitting end overcurrent protection circuit (15) and the transmitting end low voltage generating circuit (3) form a transmitting end circuit of the driving circuit; the protection channel digital control circuit (10), the protection channel modulation and transmission circuit (9), the protection channel high common mode transient suppression differential signal receiving circuit (6), the output driving circuit (7), the receiving end undervoltage protection circuit (16), the receiving end overtemperature protection circuit (17), the receiving end overcurrent protection circuit (18) and the receiving end low voltage generation circuit (8) form a driving circuit receiving end circuit; the ground potential of all circuits in the circuit of the transmitting end of the driving circuit is connected to the ground voltage Vgnd1 of the transmitting end, and the ground potential of all circuits in the circuit of the receiving end of the driving circuit is connected to the ground voltage Vgnd2 of the receiving end; the first high-voltage isolation circuit (11) comprises a positive-end transmitting capacitor Ctp, a negative-end transmitting capacitor Ctn, a positive-end receiving capacitor Crp and a negative-end receiving capacitor Crn, and the second high-voltage isolation circuit (12) comprises a positive-end transmitting capacitor Ctpp, a negative-end transmitting capacitor Ctnp, a positive-end receiving capacitor Crpp and a negative-end receiving capacitor Crnp;

The input receiving circuit (1) receives external low-level logic input data DI and a control signal Adj, and is processed and converted into input data Din with a high level VCC and a control signal Adjin, and the input data Din and the control signal Adjin are connected to the input end of the data channel digital control circuit (2); the data channel digital control circuit (2) converts Din into differential input data DxP and DxN according to the state of an undervoltage protection signal UVLO provided by a transmitting end undervoltage protection circuit (13), an overtemperature protection signal OTP provided by a transmitting end overtemperature protection circuit (14), an overcurrent protection signal OCP provided by a transmitting end overcurrent protection circuit (15), an Error signal Error output by a data channel high common mode transient suppression differential signal receiving circuit (4) and a control signal Adjin, and is connected to the input end of the data channel modulation transmitting circuit (5), and the data channel modulation transmitting circuit (5) outputs the differential transmission data TxP and TxN of the data channel; the data channel differential transmission data TxP and TxN are respectively connected to the left ends of a positive end transmission capacitor Ctp and a negative end transmission capacitor Ctn, the right ends of the positive end transmission capacitor Ctp and the negative end transmission capacitor Ctn are respectively connected to the left ends of a positive end receiving capacitor Crp and a negative end receiving capacitor Crn, and the right ends of the positive end receiving capacitor Crp and the negative end receiving capacitor Crn respectively generate data channel differential reception data RxP and RxN; the data channel differential receiving data RxP and RxN are connected to the input end of the protection channel high common mode transient suppression differential signal receiving circuit (6), the data channel differential receiving data are processed to obtain receiving output data Dout, the receiving output data Dout are connected to the input end of the output driving circuit (7), and the output driving circuit (7) outputs an output driving signal DG with large driving current;

The protection channel digital control circuit (10) obtains differential protection data PxP and PxN according to the state of an undervoltage protection signal UVLO_P provided by a receiving end undervoltage protection circuit (16), an overtemperature protection signal OTP_P provided by a receiving end overtemperature protection circuit (17) and an overcurrent protection signal OCP_P provided by a receiving end overcurrent protection circuit (18), and is connected to the input end of the protection channel modulation transmitting circuit (9); the protection channel modulation transmitting circuit (9) outputs protection channel differential transmitting data TxPp and TxNp, which are respectively connected to the right ends of the positive end transmitting capacitor Ctpp and the negative end transmitting capacitor Ctnp; the left ends of the positive end transmitting capacitor Ctpp and the negative end transmitting capacitor Ctnp are respectively connected to the right ends of the positive end receiving capacitor Crpp and the negative end receiving capacitor Crnp, the left ends of the positive end receiving capacitor Crpp and the negative end receiving capacitor Crnp generate protection channel differential receiving data RxP and RxN, the protection channel differential receiving data are connected to the input end of the data channel high common mode transient suppression differential signal receiving circuit (4), and the output Error signal Error of the data channel high common mode transient suppression differential signal receiving circuit (4) is connected to the input end of the data channel digital control circuit (2);

The transmitting end low voltage generating circuit (3) and the receiving end low voltage generating circuit (8) are realized by adopting the same low voltage generating circuit; the transmitting end low voltage generating circuit (3) adopts transmitting end power supply voltage VCC to generate reference voltage and bias voltage required by each component circuit in the low voltage power supply VCL input into the receiving circuit (1) and the driving circuit transmitting end circuit; the receiving end low voltage generating circuit (8) adopts the receiving end power supply voltage VDD to generate reference voltage and bias voltage required by each component circuit in the receiving end circuit of the driving circuit.

2. The high-voltage insulating isolation SiC MOSFET gate driving circuit with a protection function according to claim 1, wherein the protection channel high common mode transient suppression differential signal receiving circuit (6) includes: the differential input receiving circuit (601), the X-stage tandem common mode adjustable amplifying circuit (602), the high-sensitivity common mode adjustable amplifying circuit (603), the first output shaping circuit (604) and the common mode self-adaptive adjusting circuit (605); the differential input receiving circuit (601) firstly receives a positive end receiving signal RxP and a negative end receiving signal RxN of differential receiving data, and obtains a positive end input signal Vip and a negative end input signal Vin through filtering processing; the positive end input signal Vip and the negative end input signal Vin enter a first-stage common-mode adjustable amplifying circuit in an X-stage tandem common-mode adjustable amplifying circuit (602), and finally a positive end output signal VoXp and a negative end output signal VoXn of an X-stage common-mode adjustable amplifying circuit are obtained; the positive end output signal VoXp and the negative end output signal VoXn are respectively connected with the positive input end and the negative input end of the high-sensitivity common-mode adjustable amplifying circuit (603), and the high-sensitivity common-mode adjustable amplifying circuit (603) outputs a group of differential output signals, including a positive end output signal VoXp and a negative end output signal VoXn; the first output shaping circuit (604) processes the positive output signal VoXp and the negative output signal VoXn to obtain a final data output, namely receiving output data Dout; the common mode self-adaptive adjusting circuit (605) adaptively generates common mode adjusting signals C11, C12, C21, C22, …, CX1 and CX2 for each stage of amplifying circuit according to the change of power supply and ground voltage signals, and the common mode adjusting signals C11 and C12 generated by the common mode self-adaptive adjusting circuit (605) are respectively connected to the common mode adjusting signal input end of the first stage of common mode adjustable amplifying circuit; the common mode adjustment signals C21 and C22 are respectively connected to the common mode adjustment signal input end of the second-stage common mode adjustable amplifying circuit; by analogy, the common mode adjustment signals CX1 and CX2 are respectively connected to the common mode adjustment signal input end of the X-th stage common mode adjustable amplifying circuit; the common mode self-adaptive adjusting circuit (605) also generates common mode adjusting signals CN1 and CN2 which are respectively connected to the common mode adjusting signal input end of the high-sensitivity common mode adjustable amplifying circuit (603); wherein X is a positive integer greater than 1, and N is a positive integer greater than X; the data channel high common mode transient suppression differential signal receiving circuit (4) and the protection channel high common mode transient suppression differential signal receiving circuit (6) are realized by adopting the same high common mode transient suppression differential signal receiving circuit, and data output by the data channel high common mode transient suppression differential signal receiving circuit (4) is used as an Error signal Error.

3. The high-voltage insulating isolation SiC MOSFET gate driving circuit with a protection function according to claim 2, characterized in that the differential input receiving circuit (601) includes: a positive end isolation capacitor C51, a positive end grounding resistor R51, a positive end coupling capacitor C52, a positive end common mode resistor R53, a negative end isolation capacitor C53, a negative end grounding resistor R52, a negative end coupling capacitor C54, a negative end common mode resistor R54 and a receiving common mode generating circuit (6011); the left end of the positive end isolation capacitor C51 and the left end of the negative end isolation capacitor C53 are respectively connected to a positive end receiving signal RxP and a negative end receiving signal RxN; the right end of the positive end isolation capacitor C51 is connected to the lower end of the positive end grounding resistor R51 and the left end of the positive end coupling capacitor C52; the right end of the negative end isolation capacitor C53 is connected to the lower end of the negative end grounding resistor R52 and the left end of the negative end coupling capacitor C54; the right end of the positive end coupling capacitor C52 is connected to the upper end of the positive end common mode resistor R53 and is used as the output end of the positive end input signal Vip; the right end of the negative end coupling capacitor C54 is connected to the lower end of the negative end common mode resistor R54 and is used as the output end of a negative end input signal Vin; the lower end of the positive end common mode resistor R53 is connected with the upper end of the negative end common mode resistor R54 and is simultaneously connected to a common mode output end Vicm of the receiving common mode generating circuit (6011); the receiving common mode generating circuit (6011) dynamically tracks and adjusts the size of the common mode output end Vicm according to the change of the input common mode Vcm, and reduces the influence of the input common mode.

4. A high-voltage insulating isolation SiC MOSFET gate driving circuit with a protection function according to claim 3, characterized in that said reception common mode generating circuit (6011) comprises: NMOS tube M60, NMOS tube M61, PMOS tube M62, NMOS tube M63, PMOS tube M64, PMOS tube M65, NMOS tube M66, NMOS tube M67, PMOS tube M68, NMOS tube M69, PMOS tube M610, NMOS tube M611, PMOS tube M612, NMOS tube M613, NMOS tube M614, PMOS tube M615 and resistor R61, a first Schmitt trigger (600);

The grid electrode of the NMOS tube M60 is connected to an input common mode voltage Vcm; the drain electrode of the NMOS tube M60 is connected to the drain electrode and the grid electrode of the PMOS tube M62 and the grid electrode of the NMOS tube M63; the grid electrode of the NMOS tube M61 is connected to an input common mode control signal Vctrl; the drain electrode of the NMOS tube M61 is connected with the drain electrode of the NMOS tube M63 and is connected to the input end of the first Schmitt trigger (600); the output end of the first Schmitt trigger (600) is simultaneously connected to the grid electrode of the PMOS tube M610, the grid electrode of the NMOS tube M611, the grid electrode of the PMOS tube M612 and the grid electrode of the NMOS tube M613; the drain electrode of the PMOS tube M610 is connected with the drain electrode of the NMOS tube M611 and is also connected to the grid electrode of the NMOS tube M614; the drain electrode of the PMOS tube M612 is connected with the drain electrode of the NMOS tube M613 and is also connected to the grid electrode of the PMOS tube M615; the source electrode of the NMOS tube M614 is connected with the source electrode of the PMOS tube M615 and is also used as an output port of the common mode output end Vicm; the drain of the NMOS tube M614 is connected to the high input common mode level Vcmh, and the drain of the PMOS tube M615 is connected to the low input common mode level Vcml; the source electrode of the NMOS tube M613 is connected to the upper end of the resistor R61; the source electrode of the NMOS tube M60, the source electrode of the NMOS tube M61, the source electrode of the NMOS tube M611 and the lower end of the resistor R61 are simultaneously connected to the ground voltage; the source of the PMOS transistor M62, the source of the NMOS transistor M63, and the source of the PMOS transistor M610 are simultaneously connected to the power supply voltage.

5. The high-voltage insulating isolation SiC MOSFET gate drive circuit with a protection function according to claim 2, characterized in that the common mode adaptive adjustment circuit (605) includes: a first common mode detection circuit (100), a common mode detection signal transmission circuit (101), an adjustment common mode signal generation circuit (102), and a common mode adjustment signal selection circuit (103); the first common mode detection circuit (100) is used for detecting power supply and substrate noise, changing the magnitude of a common mode detection signal Vcm_det when the noise is larger than a certain threshold value, connecting the common mode detection signal Vcm_det to the common mode detection signal transmission circuit (101), generating common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2 and NN1, NN2 through the common mode detection signal transmission circuit (101), and outputting the common mode selection switch control signals to the common mode adjustment signal selection circuit (103); the common mode adjustment signal selection circuit (103) generates and adjusts the magnitude of the common mode adjustment signals C11, C12, C21, C22, …, CX1, CX2 and CN1, CN2 according to the common mode selection switch control signal and outputs the common mode adjustment signals; the common mode adjustment signal generation circuit (102) is used for generating various common mode bias signals required by the common mode adjustment signal selection circuit (103) and outputting the common mode bias signals to the common mode adjustment signal selection circuit (103).

6. The high-voltage insulating isolation SiC MOSFET gate drive circuit with a protection function according to claim 5, characterized in that the first common mode detection circuit (100) includes: PMOS tube M111, PMOS tube M112 and NMOS tube M113; the grid electrode and the drain electrode of the PMOS tube M111 are connected and connected to the drain electrode of the PMOS tube M112 and the grid electrode of the NMOS tube M113; the grid electrode of the PMOS tube M112 is connected with the drain electrode of the NMOS tube M113 and is used as an output node of the common mode detection signal Vcm_det; the source of the PMOS tube M111 and the source of the PMOS tube M112 are connected with a power supply voltage, and the source of the NMOS tube M113 is connected with a ground voltage.

7. The high-voltage insulating isolation SiC MOSFET gate driving circuit with the protection function according to claim 1, wherein the transmitting-end over-temperature protection circuit (14) and the receiving-end over-temperature protection circuit (17) adopt the same over-temperature protection circuit, and the high-voltage insulating isolation SiC MOSFET gate driving circuit comprises a clamping circuit (1401), a temperature detection circuit (1402), a wide-voltage-range comparator circuit (1403) and a first output shaping circuit (1404) which are sequentially connected, wherein the temperature detection circuit (1402) obtains a first temperature detection output signal Vin1 and a second temperature detection output signal Vin2 according to a bias voltage Vb provided by the clamping circuit (1401); the wide voltage range comparator circuit (1403) compares the first temperature detection output signal Vin1 with the second temperature detection output signal Vin2 to obtain a comparison output signal Vo1; the first output shaping circuit (1404) processes the comparison output signal Vo1 to output a temperature protection signal OTLock, wherein OTLock is a digital logic signal, OTLock is connected to an input end of the clamping circuit (1401) and used for controlling the bias voltage Vb, and OTLock is also used as a control signal to output to other circuit modules of the high-voltage insulation isolation SiC MOSFET gate driving circuit.

8. The high-voltage insulating isolation SiC MOSFET gate driving circuit with a protection function according to claim 7, characterized in that the temperature detecting circuit (1402) includes: PMOS tube M21, PMOS tube M22, resistor R21, triode Q1 and triode Q2; the base electrodes of the triode Q1 and the triode Q2 are connected and connected to a bias voltage Vb output node of the clamping circuit (1401); the emitter of the triode Q1 is connected to the grid electrode and the drain electrode of the PMOS tube M21 and is used as an output node of a first temperature detection output signal Vin 1; the emitter of the triode Q2 is connected to the grid electrode and the drain electrode of the PMOS tube M22 and is used as an output node of a second temperature detection output signal Vin 2; the source electrode of the PMOS tube M21 and the source electrode of the PMOS tube M22 are connected to a power supply voltage, the collector electrode of the triode Q2 is connected to the upper end of the resistor R21, and the lower end of the resistor R21 and the collector electrode of the triode Q1 are connected to a ground voltage; the width-to-length ratio of the PMOS transistor M21 and the PMOS transistor M22 is equal, and the base area ratio of the transistor Q1 and the transistor Q2 is 1: n and N are arbitrary natural numbers.

9. The high-voltage insulating isolation SiC MOSFET gate drive circuit with a protection function according to claim 7, characterized in that the wide voltage range comparator circuit (1403) includes: PMOS tube M31, PMOS tube M33, PMOS tube M35, PMOS tube M36, PMOS tube M37, PMOS tube M39, NMOS tube M32, NMOS tube M34, NMOS tube M38, NMOS tube M310 and second common mode detection circuit (1031); the grid electrode of the PMOS tube M31 is connected to the first temperature detection output signal Vin1, and the grid electrode of the PMOS tube M33 is connected to the second temperature detection output signal Vin2; the drain electrode of the PMOS tube M31 is connected to the drain electrode and the gate electrode of the NMOS tube M32, the gate electrode of the NMOS tube M34 and the gate electrode of the NMOS tube M310; the drain electrode of the PMOS tube M33 is connected to the drain electrode of the NMOS tube M34 and the grid electrode of the PMOS tube M37; the drain electrode of the PMOS tube M37 is connected to the drain electrode and the grid electrode of the NMOS tube M38, and the source electrode of the PMOS tube M37 is connected to the grid electrode of the PMOS tube M39 and the drain electrode of the PMOS tube M36; the source electrode of the PMOS tube M36 is connected to the drain electrode of the PMOS tube M35, and the grid electrodes of the PMOS tube M36 and the PMOS tube M35 are both connected to the control signal output by the second common mode detection circuit (1031); the drain electrode of the PMOS tube M39 is connected with the drain electrode of the NMOS tube M310 and outputs a comparison output signal Vo1; the sources of the PMOS tube M31, the PMOS tube M33, the PMOS tube M35 and the PMOS tube M39 are simultaneously connected to the power supply voltage; the sources of the NMOS transistors M32, M34, M38 and M310 are simultaneously connected to the ground voltage.

10. The high-voltage insulating isolation SiC MOSFET gate driving circuit with a protection function according to claim 9, wherein the second common mode detection circuit (1031) automatically detects common mode noise generated by a power supply voltage and a substrate potential, and changes a common mode control signal vcm_det when the common mode noise exceeds a certain threshold value; when the common mode noise does not exceed the threshold value, the common mode control signal Vcm_det is at a high level, the PMOS tube M36 and the PMOS tube M35 are in an off state, and the grid electrode of the PMOS tube M39 is controlled by the source electrode of the PMOS tube M37; when the common mode noise exceeds the threshold value, the common mode control signal vcm_det is at a low level, the PMOS transistor M36 and the PMOS transistor M35 are both in a conducting state, the PMOS transistor M39 is in a closing state, and the comparison output signal Vo1 is clamped to a low level, so that the normal operation of the comparator is prevented from being affected by the common mode noise.