CN113067566A

CN113067566A - High-voltage insulation isolation SiC MOSFET gate drive circuit with protection function

Info

Publication number: CN113067566A
Application number: CN202110347550.0A
Authority: CN
Inventors: 陈珍海; 袁述; 卢基存; 黎力
Original assignee: Jiangsu Zhongkehanyun Semiconductor Co ltd
Current assignee: Jiangsu Zhongkehanyun Semiconductor Co ltd
Priority date: 2021-03-31
Filing date: 2021-03-31
Publication date: 2021-07-02
Anticipated expiration: 2041-03-31
Also published as: CN113067566B

Abstract

The invention discloses a high-voltage insulation isolation SiC MOSFET gate drive circuit with a protection function, which comprises: the device comprises an input receiving circuit, a data channel digital control circuit, a data channel modulation transmitting circuit, a data channel high common mode transient suppression differential signal receiving circuit, a protection channel digital control circuit, a protection channel modulation transmitting circuit, a protection channel high common mode transient suppression differential signal receiving circuit, an output driving circuit, a transmitting end low voltage generating circuit, a receiving end low voltage generating circuit and a high voltage isolating circuit. On one hand, the high-precision protection circuit is adopted to prevent the SiC MOSFET from separating from the safe working area, so that the reliability is improved; on the other hand, the ultrahigh voltage-resistant insulating capacitor can be realized by adopting a high-voltage insulating and isolating technology; in addition, the magnitude of the ground potential common mode transient noise is automatically detected, and the error generated by the common mode transient noise is dynamically compensated when the noise exceeds a threshold value. The invention can be widely applied to driving various high-voltage SiCMOS MOSFETs and IGBT devices.

Description

High-voltage insulation isolation SiC MOSFET gate drive circuit with protection function

Technical Field

The invention relates to a high-voltage insulation isolation SiC MOSFET gate drive circuit with a protection function, and belongs to the technical field of integrated circuits.

Background

With the advent and widespread use of Si-based superjunction MOSFETs and Insulated Gate Bipolar Transistors (IGBTs), silicon devices have begun to be unsuitable for some high voltage, high temperature, high efficiency and high power density applications due to their physical property limitations. Compared with Si materials, the high thermal conductivity of SiC materials determines the high current density characteristics of the SiC materials, and the high breakdown field strength and the high working temperature of SiC devices are determined by the high forbidden band width of the SiC materials. Particularly, in the aspects of development and application of the SiC MOSFET, compared with the Si MOSFET with the same power grade, the SiC MOSFET has greatly reduced on-resistance and switching loss, is suitable for higher working frequency, and greatly improves the high-temperature stability due to the high-temperature working characteristic.

Because the device characteristics of the SiC MOSFET are greatly different from those of the traditional Si MOSFET, the performance of the SiC MOSFET drive circuit plays a crucial role in the whole system. A new generation of power electronic complete machine system based on SiC devices puts higher demands on the driving speed and the intellectualization of a high-voltage grid driving chip, thereby further improving the reliability of the complete machine and reducing the design complexity of the complete machine system. Compared with a Si MOSFET, a SiC MOSFET has smaller parasitic capacitance, which differs by more than ten times, and thus is more sensitive to parasitic parameters of a driving circuit. On the other hand, the drive voltage range of SiC MOSFETs is typically-5V- +25V, whereas the drive voltage range of conventional Si MOSFETs is-30V- + 30V. Therefore, the SiC MOSFET has a smaller safety threshold than the conventional Si MOSFET, and a voltage spike of the driving circuit is likely to break down the oxide layer between the gate and the source, which also requires careful design of the output control level of the driving circuit.

The high-voltage gate driving chip is used for meeting the requirements of switching driving between a low-power level signal provided by an output interface of the CPU controller and a high-voltage high-current signal required by gate driving of a high-power output device. The core function of the gate drive IC in the whole machine system is to convert a low-power level signal (1mA/3-5V) output by a CPU controller into a high-voltage high-current signal (0.5-5A/5-20V) required by gate drive of a high-power device, and amplify output current and output voltage swing amplitude; because the output driving object is a high-voltage heavy-current device, a large voltage difference exists between the substrate potential of the output circuit and the substrate potential of the input circuit, and the high-voltage circuit and the low-voltage circuit are electrically isolated; in addition, since signal connection is required between the high-voltage and low-voltage circuits, an isolation area signal transmission module which is responsible for signal transmission between two sides of the isolation area is required in the chip. Since the application background of the SiC MOSFET is a high-power system, the SiC MOSFET must be protected during operation to avoid leaving its safe operating area, thereby shortening the lifetime and even damaging it, so that a protection circuit must be added to the driver to enable fast and effective protection in case of a fault. Therefore, monitoring and protection circuits including overvoltage, undervoltage, overtemperature, overcurrent protection and the like are generally integrated in the SiC MOSFET gate driving circuit.

Disclosure of Invention

The invention aims to provide a high-voltage insulation isolation SiC MOSFET gate drive circuit based on insulation isolation technology and having high common-mode transient noise suppression characteristic aiming at the drive application requirement of a SiC MOSFET device.

According to the technical scheme provided by the invention, the high-voltage insulation isolation SiC MOSFET gate drive circuit with the protection function comprises: the device comprises an input receiving circuit, a data channel digital control circuit, a data channel modulation transmitting circuit, a first high-voltage isolation circuit, a protection channel high common mode transient suppression differential signal receiving circuit, a protection channel digital control circuit, a protection channel modulation transmitting circuit, a second high-voltage isolation circuit, a data channel high common mode transient suppression differential signal receiving circuit, an output driving circuit, a transmitting end low-voltage generating circuit, a receiving end low-voltage generating circuit, a transmitting end undervoltage protection circuit, a transmitting end over-temperature protection circuit, a transmitting end over-current protection circuit, a receiving end undervoltage protection circuit, a receiving end over-temperature protection circuit and a receiving end over-current protection circuit;

the input receiving circuit, the data channel digital control circuit, the data channel modulation transmitting circuit, the data channel high common mode transient suppression differential signal receiving circuit, the transmitting end undervoltage protection circuit, the transmitting end overtemperature protection circuit, the transmitting end overcurrent protection circuit and the transmitting end low voltage generating circuit form a driving circuit transmitting end circuit; the protection channel digital control circuit, the protection channel modulation transmitting circuit, the protection channel high common mode transient suppression differential signal receiving circuit, the output driving circuit, the receiving end under-voltage protection circuit, the receiving end over-temperature protection circuit, the receiving end over-current protection circuit and the receiving end low-voltage generation circuit form a driving circuit receiving end circuit; the ground potentials of all circuits in the sending end circuit of the driving circuit are connected to a sending end ground voltage Vgnd1, and the ground potentials of all circuits in the receiving end circuit of the driving circuit are connected to a receiving end ground voltage Vgnd 2; the first high-voltage isolation circuit comprises a positive end sending capacitor Ctp, a negative end sending capacitor Ctn, a positive end receiving capacitor Crp and a negative end receiving capacitor Crn, and the second high-voltage isolation circuit comprises a positive end sending capacitor Ctpp, a negative end sending capacitor Ctnp, a positive end receiving capacitor Crpp and a negative end receiving capacitor Crnp;

the input receiving circuit receives external low-level logic input data DI and a control signal Adj, converts the external low-level logic input data DI and the control signal Adj into input data Din with a high level VCC through processing, and is connected to the input end of the data channel digital control circuit; the data channel digital control circuit converts Din into differential input data DxP and DxN according to the states of an undervoltage protection signal UVLO provided by the transmitting end undervoltage protection circuit, an over-temperature protection signal OTP provided by the transmitting end over-temperature protection circuit, an over-current protection signal OCP provided by the transmitting end over-current protection circuit, an Error signal Error output by the data channel high common mode transient suppression differential signal receiving circuit and a control signal Adjin, and the data channel digital control circuit is connected to the input end of the data channel modulation transmitting circuit; data channel differential sending data TxP and TxN are respectively connected to the left ends of a positive terminal sending capacitor Ctp and a negative terminal sending capacitor Ctn, the right ends of the positive terminal sending capacitor Ctp and the negative terminal sending capacitor Ctn are respectively connected to the left ends of a positive terminal receiving capacitor Crp and a negative terminal receiving capacitor Crn, and data channel differential receiving data RxP and RxN are respectively generated at the right ends of the positive terminal receiving capacitor Crp and the negative terminal receiving capacitor Crn; the data channel differential receiving data RxP and RxN are connected to the input end of the protection channel high common mode transient suppression differential signal receiving circuit, receiving output data Dout is obtained after processing, the receiving output data Dout is connected to the input end of the output driving circuit, and the output driving circuit outputs an output driving signal DG with large driving current;

the protection channel digital control circuit obtains differential protection data PxP and PxN according to the states of an undervoltage protection signal UVLO _ P provided by the receiving end undervoltage protection circuit, an over-temperature protection signal OTP _ P provided by the receiving end over-temperature protection circuit and an over-current protection signal OCP _ P provided by the receiving end over-current protection circuit, and the differential protection data is connected to the input end of the protection channel modulation sending circuit; the protection channel modulation sending circuit outputs protection channel differential sending data TxPP and TxNP which are respectively connected to the right ends of a positive terminal sending capacitor Ctpp and a negative terminal sending capacitor Ctnp; the left ends of the positive terminal sending capacitor Ctpp and the negative terminal sending capacitor Ctnp are respectively connected to the right ends of the positive terminal receiving capacitor Crpp and the negative terminal receiving capacitor Crnp, the left ends of the positive terminal receiving capacitor Crpp and the negative terminal receiving capacitor Crnp generate protection channel differential receiving data RxP and RxN which are connected to the input end of the data channel high common mode transient suppression differential signal receiving circuit, and the output Error signal Error of the data channel high common mode transient suppression differential signal receiving circuit is connected to the input end of the data channel digital control circuit;

the transmitting end low-voltage generating circuit and the receiving end low-voltage generating circuit are realized by adopting the same low-voltage generating circuit; the transmitting end low-voltage generating circuit adopts transmitting end power supply voltage VCC to generate reference voltage and bias voltage required by each component circuit in the low-voltage power supply VCL and the driving circuit transmitting end circuit which are used for inputting the receiving circuit; the receiving end low voltage generating circuit adopts a receiving end power supply voltage VDD to generate reference voltage and bias voltage required by all the internal circuit components of the receiving end circuit of the driving circuit.

Specifically, the protection channel high common mode transient suppression differential signal receiving circuit includes: the device comprises a differential input receiving circuit, an X-level front-back cascade common-mode adjustable amplifying circuit, a high-sensitivity common-mode adjustable amplifying circuit, a first output shaping circuit and a common-mode self-adaptive adjusting circuit; the differential input receiving circuit firstly receives a positive terminal receiving signal RxP and a negative terminal receiving signal RxN of differential receiving data, and obtains a positive terminal input signal Vip and a negative terminal input signal Vin through filtering processing; the positive end input signal Vip and the negative end input signal Vin enter a first-stage common mode adjustable amplifying circuit in X-stage common mode adjustable amplifying circuits which are cascaded in front and at the back, and finally a positive end output signal VoXp and a negative end output signal VoXn of the X-stage common mode adjustable amplifying circuit are obtained; the positive end output signal VoXp and the negative end output signal VoXn are respectively connected with the positive input end and the negative input end of the high-sensitivity common-mode adjustable amplifying circuit, and the high-sensitivity common-mode adjustable amplifying circuit outputs a group of differential output signals which comprise the positive end output signal VoXp and the negative end output signal VoXn; the first output shaping circuit is used for processing to obtain final data output according to the positive end output signal VoXp and the negative end output signal VoXn, namely receiving output data Dout; the common mode self-adaptive adjusting circuit generates common mode adjusting signals C11, C12, C21, C22, …, CX1 and CX2 for each stage of amplifying circuit in a self-adaptive mode according to changes of power supply and ground voltage signals, and the common mode adjusting signals C11 and C12 generated by the common mode self-adaptive adjusting circuit are respectively connected to a common mode adjusting signal input end of the first stage of common mode adjustable amplifying circuit; the common mode adjusting signals C21 and C22 are respectively connected to the common mode adjusting signal input end of the second-stage common mode adjustable amplifying circuit; by analogy, the common mode adjusting signals CX1 and CX2 are respectively connected to the common mode adjusting signal input end of the X-th order common mode adjustable amplifying circuit; the common mode self-adaptive adjusting circuit also generates common mode adjusting signals CN1 and CN2 which are respectively connected to a common mode adjusting signal input end of the high-sensitivity common mode adjustable amplifying circuit; wherein X is a positive integer greater than 1, and N is a positive integer greater than X; the data channel high common mode transient suppression differential signal receiving circuit and the protection channel high common mode transient suppression differential signal receiving circuit are realized by adopting the same high common mode transient suppression differential signal receiving circuit, and data output by the data channel high common mode transient suppression differential signal receiving circuit is used as an Error signal Error.

Specifically, the differential input receiving circuit includes: the common-mode receiver comprises a positive-end isolation capacitor C51, a positive-end grounding resistor R51, a positive-end coupling capacitor C52, a positive-end common-mode resistor R53, a negative-end isolation capacitor C53, a negative-end grounding resistor R52, a negative-end coupling capacitor C54, a negative-end common-mode resistor R54 and a receiving common-mode generating circuit; the left end of the positive side isolation capacitor C51 and the left end of the negative side isolation capacitor C53 are connected to the positive side receive signal RxP and the negative side receive signal RxN, respectively; the right end of the positive side isolation capacitor C51 is connected to the lower end of the positive side ground resistor R51 and the left end of the positive side coupling capacitor C52; the right end of the negative side isolation capacitor C53 is connected to the lower end of the negative side ground resistor R52 and the left end of the negative side coupling capacitor C54; the right end of the positive terminal coupling capacitor C52 is connected to the upper end of the positive terminal common mode resistor R53 and serves as the output terminal of the positive terminal input signal Vip; the right end of the negative end coupling capacitor C54 is connected to the lower end of the negative end common mode resistor R54 and serves as the output end of a negative end input signal Vin; the lower end of the positive end common mode resistor R53 is connected with the upper end of the negative end common mode resistor R54 and is simultaneously connected to a common mode output end Vicm of the receiving common mode generating circuit; the receiving common mode generating circuit dynamically tracks and adjusts the size of a common mode output end Vicm according to the change of an input common mode Vcm, and the influence of an input common mode is reduced.

Specifically, the receiving common mode generating circuit includes: an NMOS transistor M60, an NMOS transistor M61, a PMOS transistor M62, an NMOS transistor M63, a PMOS transistor M64, a PMOS transistor M65, an NMOS transistor M66, an NMOS transistor M67, a PMOS transistor M68, an NMOS transistor M69, a PMOS transistor M610, an NMOS transistor M611, a PMOS transistor M612, an NMOS transistor M613, an NMOS transistor M614, a PMOS transistor M615, a resistor R61 and a first Schmidt trigger;

the grid electrode of the NMOS tube M60 is connected to an input common mode voltage Vcm; the drain electrode of the NMOS tube M60 is connected to the drain electrode and the gate electrode of the PMOS tube M62 and the gate electrode of the NMOS tube M63; the grid electrode of the NMOS tube M61 is connected to an input common mode control signal Vctrl; the drain electrode of the NMOS tube M61 is connected with the drain electrode of the NMOS tube M63 and is connected to the input end of the first Schmitt trigger; the output end of the first Schmitt trigger is simultaneously connected to the grid electrode of the PMOS tube M610, the grid electrode of the NMOS tube M611, the grid electrode of the PMOS tube M612 and the grid electrode of the NMOS tube M613; the drain electrode of the PMOS tube M610 is connected with the drain electrode of the NMOS tube M611 and is also connected to the grid electrode of the NMOS tube M614; the drain of the PMOS tube M612 is connected with the drain of the NMOS tube M613, and is also connected to the gate of the PMOS tube M615; the source electrode of the NMOS tube M614 is connected with the source electrode of the PMOS tube M615 and is also used as an output port of the common mode output end Vicm; the drain electrode of the NMOS tube M614 is connected to a high input common mode level Vcmh, and the drain electrode of the PMOS tube M615 is connected to a low input common mode level Vcml; the source of the NMOS transistor M613 is connected to the upper end of the resistor R61; the source electrode of the NMOS transistor M60, the source electrode of the NMOS transistor M61, the source electrode of the NMOS transistor M611 and the lower end of the resistor R61 are simultaneously connected to the ground voltage; the source of the PMOS transistor M62, the source of the NMOS transistor M63 and the source of the PMOS transistor M610 are simultaneously connected to a power supply voltage.

Specifically, the common-mode adaptive adjustment circuit includes: the common mode detection circuit comprises a first common mode detection circuit, a common mode detection signal transmission circuit, an adjustment common mode signal generation circuit and a common mode adjustment signal selection circuit; the first common mode detection circuit is used for detecting power supply and substrate noise and changing the size of a common mode detection signal Vcm _ det when the noise is larger than a certain threshold value, the common mode detection signal Vcm _ det is connected to a common mode detection signal transmission circuit, common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2, NN1 and NN2 are generated through the common mode detection signal transmission circuit and output to the common mode adjustment signal selection circuit; the common mode adjusting signal selection circuit generates and adjusts the size of common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2 and CN1, CN2 according to the common mode selecting switch control signal and outputs the common mode adjusting signals; the adjusting common-mode signal generating circuit is used for generating various common-mode bias signals required by the common-mode adjusting signal selecting circuit and outputting the common-mode bias signals to the common-mode adjusting signal selecting circuit.

Specifically, the first common mode detection circuit includes: a PMOS transistor M111, a PMOS transistor M112 and an NMOS transistor M113; the grid electrode and the drain electrode of the PMOS tube M111 are connected, and the grid electrode is connected with the drain electrode of the PMOS tube M112 and the grid electrode of the NMOS tube M113; the grid electrode of the PMOS tube M112 is connected with the drain electrode of the NMOS tube M113 and is used as an output node of a common mode detection signal Vcm _ det; the source of the PMOS transistor M111 and the source of the PMOS transistor M112 are connected with a power supply voltage, and the source of the NMOS transistor M113 is connected with a ground voltage.

Specifically, the sending end over-temperature protection circuit and the receiving end over-temperature protection circuit adopt the same over-temperature protection circuit, and comprise a clamping circuit, a temperature detection circuit, a wide voltage range comparator circuit and a first output shaping circuit which are connected in sequence, wherein the temperature detection circuit obtains a first temperature detection output signal Vin1 and a second temperature detection output signal Vin2 according to a bias voltage Vb provided by the clamping circuit; the wide voltage range comparator circuit compares the first temperature detection output signal Vin1 with the second temperature detection output signal Vin2 to obtain a comparison output signal Vo 1; the first output shaping circuit processes the comparison output signal Vo1 to output a temperature protection signal OTLock, the OTLock is a digital logic signal, the OTLock is connected to the input end of the clamping circuit and used for controlling the magnitude of the bias voltage Vb, and the OTLock is also used as a control signal to be output to other circuit modules of the high-voltage insulation isolation SiC MOSFET gate driving circuit.

Specifically, the temperature detection circuit includes: a PMOS tube M21, a PMOS tube M22, a resistor R21, a triode Q1 and a triode Q2; the triode Q1 is connected with the base electrode of the triode Q2 and is connected with the bias voltage Vb output node of the clamping circuit; an emitter of the triode Q1 is connected to the gate and the drain of the PMOS transistor M21 and serves as an output node of the first temperature detection output signal Vin 1; an emitter of the triode Q2 is connected to the gate and the drain of the PMOS transistor M22 and serves as an output node of the second temperature detection output signal Vin 2; the source electrode of the PMOS tube M21 and the source electrode of the PMOS tube M22 are connected to a power supply voltage, the collector electrode of the triode Q2 is connected to the upper end of the resistor R21, the lower end of the resistor R21 and the collector electrode of the triode Q1 are connected to a ground voltage; the width-length ratio of the PMOS tube M21 to the length-width ratio of the PMOS tube M22 are equal, and the base area ratio of the triode Q1 to the base area ratio of the triode Q2 is 1: n and N are any natural number.

Specifically, the wide voltage range comparator circuit includes: a PMOS tube M31, a PMOS tube M33, a PMOS tube M35, a PMOS tube M36, a PMOS tube M37, a PMOS tube M39, an NMOS tube M32, an NMOS tube M34, an NMOS tube M38, an NMOS tube M310 and a second common mode detection circuit; the grid electrode of the PMOS tube M31 is connected to the first temperature detection output signal Vin1, and the grid electrode of the PMOS tube M33 is connected to the second temperature detection output signal Vin 2; the drain electrode of the PMOS tube M31 is connected to the drain electrode and the gate electrode of the NMOS tube M32, the gate electrode of the NMOS tube M34 and the gate electrode of the NMOS tube M310; the drain electrode of the PMOS tube M33 is connected to the drain electrode of the NMOS tube M34 and the gate electrode of the PMOS tube M37; the drain electrode of the PMOS tube M37 is connected to the drain electrode and the grid electrode of the NMOS tube M38, and the source electrode of the PMOS tube M37 is connected to the grid electrode of the PMOS tube M39 and the drain electrode of the PMOS tube M36; the source electrode of the PMOS tube M36 is connected to the drain electrode of the PMOS tube M35, and the grid electrodes of the PMOS tube M36 and the PMOS tube M35 are both connected to the control signal output by the second common mode detection circuit; the drain electrode of the PMOS tube M39 is connected with the drain electrode of the NMOS tube M310 and outputs a comparison output signal Vo 1; the sources of the PMOS transistor M31, the PMOS transistor M33, the PMOS transistor M35 and the PMOS transistor M39 are simultaneously connected to a power supply voltage; the sources of the NMOS transistor M32, the NMOS transistor M34, the NMOS transistor M38 and the NMOS transistor M310 are simultaneously connected to the ground voltage.

Specifically, the second common mode detection circuit automatically detects common mode noise generated by the power supply voltage and the substrate potential, and changes the common mode control signal Vcm _ det when the common mode noise exceeds a certain threshold; when the common-mode noise does not exceed the threshold, the common-mode control signal Vcm _ det is at a high level, the PMOS tube M36 and the PMOS tube M35 are both in an off state, and the grid electrode of the PMOS tube M39 is controlled by the source electrode of the PMOS tube M37; when the common-mode noise exceeds the threshold value, the common-mode control signal Vcm _ det is at a low level, the PMOS transistor M36 and the PMOS transistor M35 are both in a conducting state, the PMOS transistor M39 enters a closing state, and the comparison output signal Vo1 is clamped to the low level, so that the common-mode noise is prevented from influencing the normal work of the comparator.

The invention has the advantages that: on one hand, the high-precision protection circuit is adopted to prevent the SiC MOSFET from separating from the safe working area, so that the reliability is improved; on the other hand, the ultrahigh voltage-resistant insulating capacitor can be realized by adopting a high-voltage insulating and isolating technology; in addition, the circuit can automatically detect the magnitude of the ground potential common mode transient noise and dynamically compensate the error generated by the common mode transient noise when the noise exceeds a threshold value.

Drawings

Fig. 1 is a structure diagram of a gate driving circuit of a high-voltage insulated isolated SiC MOSFET with a protection function according to the present invention.

FIG. 2 is a block diagram of an input receiving circuit according to the present invention.

FIG. 3 is a diagram of a digital control circuit according to the present invention.

Fig. 4 is a structural diagram of a modulation transmission circuit of the present invention.

Fig. 5 is a structural diagram of a high common mode transient suppression differential signal receiving circuit according to the present invention.

Fig. 6 shows an embodiment of the differential input receiving circuit of the present invention.

Fig. 7 is a diagram of an embodiment of a receiving common mode generating circuit according to the present invention.

Fig. 8 is a diagram of an embodiment of a common mode adjustable amplifier circuit according to the invention.

Fig. 9 shows an embodiment of the high-sensitivity common-mode tunable amplifier circuit according to the present invention.

Fig. 10 shows an embodiment of a first output shaping circuit according to the present invention.

Fig. 11 is a diagram of an embodiment of a common mode adaptive adjustment circuit according to the invention.

FIG. 12 is a diagram of an embodiment of a common mode detection circuit according to the invention.

Fig. 13 is an operating waveform of the circuit shown in fig. 12.

Fig. 14 shows an embodiment of a high voltage isolation capacitor according to the present invention.

Fig. 15 shows an embodiment of the low voltage generation circuit of the present invention.

Fig. 16 is a structural diagram of the high-precision wide-voltage-range over-temperature protection circuit of the present invention.

Fig. 17 shows an embodiment of a clamp circuit according to the present invention.

FIG. 18 shows an embodiment of a temperature detection circuit according to the present invention.

FIG. 19 is a diagram of an embodiment of a wide voltage range comparator circuit according to the present invention.

Fig. 20 shows a second embodiment of the output shaping circuit according to the present invention.

FIG. 21 is a diagram of the structure of the high-precision under-voltage protection circuit of the present invention.

Fig. 22 is a diagram showing the structure of the high-precision overcurrent protection circuit according to the present invention.

Fig. 23 shows an embodiment of an output driving circuit according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

As shown in fig. 1, the high-voltage insulated isolated SiC MOSFET gate driving circuit with protection function according to the present invention includes an input receiving circuit 1, a data channel digital control circuit 2, a data channel modulation transmitting circuit 5, a first high-voltage isolating circuit 11, a protection channel high common mode transient suppression differential signal receiving circuit 6, a protection channel digital control circuit 10, a protection channel modulation transmitting circuit 9, a second high-voltage isolating circuit 12, a data channel high common mode transient suppression differential signal receiving circuit 4, an output driving circuit 7, a transmitting end low voltage generating circuit 3, a receiving end low voltage generating circuit 8, a transmitting end undervoltage protection circuit 13, a transmitting end over-temperature protection circuit 14, a transmitting end over-current protection circuit 15, a receiving end undervoltage protection circuit 16, a receiving end over-temperature protection circuit 17, and a receiving end over-current protection circuit 18.

The input receiving circuit 1, the data channel digital control circuit 2, the data channel modulation transmitting circuit 5, the data channel high common mode transient suppression differential signal receiving circuit 4, the transmitting end under-voltage protection circuit 13, the transmitting end over-temperature protection circuit 14, the transmitting end over-current protection circuit 15 and the transmitting end low-voltage generation circuit 3 form a driving circuit transmitting end circuit; the protection channel digital control circuit 10, the protection channel modulation transmitting circuit 9, the protection channel high common mode transient suppression differential signal receiving circuit 6, the output driving circuit 7, the receiving end under-voltage protection circuit 16, the receiving end over-temperature protection circuit 17, the receiving end over-current protection circuit 18 and the receiving end low-voltage generation circuit 8 form a driving circuit receiving end circuit. The ground potentials of all circuits inside the transmitting-end circuit of the driving circuit are connected to a transmitting-end ground voltage Vgnd1, and the ground potentials of all circuits inside the receiving-end circuit of the driving circuit are connected to a receiving-end ground voltage Vgnd 2.

The high-voltage isolation circuit is used for isolating the drive circuit sending end circuit from the drive circuit receiving end circuit. The first high-voltage isolation circuit 11 comprises a positive end sending capacitor Ctp, a negative end sending capacitor Ctn, a positive end receiving capacitor Crp and a negative end receiving capacitor Crn, and the second high-voltage isolation circuit 12 comprises a positive end sending capacitor Ctpp, a negative end sending capacitor Ctnp, a positive end receiving capacitor Crpp and a negative end receiving capacitor Crnp.

The input receiving circuit 1 receives external low-level logic input data DI and a control signal Adj, and converts the external low-level logic input data DI and the control signal Adj into input data Din with a high level VCC and a control signal Adjin through processing; the input data Din then enters a data channel digital control circuit 2, and the data channel digital control circuit 2 obtains differential input data dxP and dxN according to the states of an undervoltage protection signal UVLO provided by a sending end undervoltage protection circuit 13, an over-temperature protection signal OTP provided by a sending end over-temperature protection circuit 14, an over-current protection signal OCP provided by a sending end over-current protection circuit 15, an Error signal Error output by a data channel high common mode transient suppression differential signal receiving circuit 4 and a control signal Adjin; the differential input data dxP and dxN enter a data channel modulation transmitting circuit 5 to obtain data channel differential transmitting data TxP and TxN; the data channel differential sending data TxP and TxN are respectively connected to the left ends of a positive terminal sending capacitor Ctp and a negative terminal sending capacitor Ctn; the right ends of the positive terminal sending capacitor Ctp and the negative terminal sending capacitor Ctn are respectively connected to the left ends of the positive terminal receiving capacitor Crp and the negative terminal receiving capacitor Crn; the right ends of the positive terminal receiving capacitor Crp and the negative terminal receiving capacitor Crn are data channel differential receiving data RxP and RxN; the data channel differential receiving data RxP and RxN enter a protection channel high common mode transient suppression differential signal receiving circuit 6, and receiving output data Dout is obtained after processing; the received output data Dout finally enters the output drive circuit 7, which generates an output drive signal DG with a large drive current.

Similarly to the data channel digital control circuit 2, the protection channel digital control circuit 10 obtains differential protection data PxP and PxN according to the states of the undervoltage protection signal UVLO _ P provided by the receiving-end undervoltage protection circuit 16, the over-temperature protection signal OTP _ P provided by the receiving-end over-temperature protection circuit 17, and the over-current protection signal OCP _ P provided by the receiving-end over-current protection circuit 18; differential protection data PxP and PxN enter a protection channel modulation transmitting circuit 9 to obtain protection channel differential transmission data TxPP and TxNP; the protection channel differential sending data TxPp and TxNP are respectively connected to the right ends of the positive terminal sending capacitor Ctpp and the negative terminal sending capacitor Ctnp; the left ends of the positive terminal sending capacitor Ctpp and the negative terminal sending capacitor Ctnp are respectively connected to the right ends of the positive terminal receiving capacitor Crpp and the negative terminal receiving capacitor Crnp; the left ends of the positive terminal receiving capacitor Crpp and the negative terminal receiving capacitor Crnp are protection channel differential receiving data RxP and RxN; the protection channel differential receiving data RxP and RxN enter the data channel high common mode transient suppression differential signal receiving circuit 4, and are processed to obtain an Error signal Error output.

The sending end low voltage generating circuit 3 adopts sending end power supply voltage VCC to generate various reference voltages and bias voltages required by the low voltage power supply VCL input to the receiving circuit 1 and various internal component circuits of the sending end circuit of the driving circuit. The receiving-end low-voltage generating circuit 8 generates various reference voltages and bias voltages required for driving each component circuit inside the receiving-end circuit of the circuit by using the receiving-end power supply voltage VDD. The sending end low voltage generating circuit 3 and the receiving end low voltage generating circuit 8 are realized by the same low voltage generating circuit.

The sending end undervoltage protection circuit 13 and the receiving end undervoltage protection circuit 16 are realized by the same high-precision undervoltage protection circuit; the sending end over-temperature protection circuit 14 and the receiving end over-temperature protection circuit 17 are realized by adopting the same high-precision wide-voltage-range over-temperature protection circuit; the sending end overcurrent protection circuit 15 and the receiving end overcurrent protection circuit 18 are implemented by the same high-precision overcurrent protection circuit.

In the circuit shown in fig. 1, a sending-end undervoltage protection circuit 13, a sending-end over-temperature protection circuit 14, and a sending-end over-current protection circuit 15 respectively provide an undervoltage protection signal UVLO, an over-temperature protection signal OTP, and an over-current protection signal OCP, and a data channel digital control circuit 2 determines whether the chip state is correct. When the circuit is subjected to overcurrent (OCP is effective), overtemperature (OTP is effective) or power supply voltage undervoltage (UVLO is effective), the data channel digital control circuit 2 can block two paths of output DxP and DxN; when the overcurrent and overtemperature alarm is relieved and the power supply recovers to normal working voltage, the data channel digital control circuit 2 indicates that the circuit works normally. According to the invention, an undervoltage protection signal UVLO _ P, an over-temperature protection signal OTP _ P and an over-current protection signal OCP _ P which are respectively provided by a receiving end undervoltage protection circuit 16, a receiving end over-temperature protection circuit 17 and a receiving end over-current protection circuit 18 and used for monitoring the state of an output driving SIC MOSFET are fed back to a transmitting end through a protection channel modulation transmitting circuit 9, a second high-voltage isolation circuit 12 and a data channel high common mode transient suppression differential signal receiving circuit 4 to obtain an Error signal Error, and the Error signal Error is fed back to a data channel digital control circuit 2 on one hand and is also output to an external CPU controller.

The structure of a basic input receiving circuit 1 of the high-voltage SiC MOSFET gate driving circuit is shown in figure 2, two channels of same input receiving circuits are adopted, and each channel of receiving circuit comprises an input ESD protection circuit, a level discrimination circuit and a medium-voltage level shift circuit. The input receiving circuit 1 not only needs to complete the transmission of signals, but also needs to complete the ESD protection of the internal circuit of the chip, so as to prevent the circuit from being damaged due to the impact of ESD to the internal circuit. Circuits commonly used for ESD protection in integrated circuit designs are: lateral SCR clamps, reverse parallel diode clamps, zener clamps, CDM clamps, and the like. The level discriminating circuit is used for discriminating whether an external input level is logic '0' or '1', and the level discriminating circuit must have enough interference noise tolerance due to the existence of large interference of an external signal, and the specific circuit implementation usually comprises 2 types, one type is a Schmitt trigger, and the other type is a hysteresis comparator. According to different speeds of driving objects and input logic signals of the driving chip, the implementation circuits of the Schmitt trigger and the hysteresis comparator are greatly different. Since the power supply voltage VCC of the gate driving chip is usually a medium voltage level of 10-20V, and the input logic level is an external digital logic lower than 5V, in order to more accurately complete the judgment of the input logic level, the input ESD and level judgment circuit must use a relatively lower power supply voltage VCL, usually a voltage of 3-10V. Therefore, before the logic signal output by the level discrimination circuit enters the chip internal control logic, a medium-voltage level shift circuit is required to convert the logic signal with the high level of VCL into the logic signal with the high level of VCC to obtain Din and Adjin signals.

The digital control circuit of the invention has the functions of integrating the chip state monitoring signals, judging whether the circuit is normal or not, and shutting off data output when the chip is abnormal. One implementation of a digital control circuit provided in an embodiment is shown in fig. 3, and the circuit is composed of combinational logic gates. The control process realized by the circuit is as follows: when the circuit is subjected to overcurrent (OCP is effective), overtemperature (OTP is effective) or power supply voltage undervoltage (UVLO is effective), the error logic circuit in the first row in the figure outputs a low level signal to indicate that the circuit is abnormal, and blocks two paths of output DxP and DxN; when the over-current and over-temperature alarm is released and the power supply recovers to normal working voltage, the error logic circuit immediately outputs a high-level signal to indicate that the circuit works normally. The signals of the data channel digital control circuit 2 are identified in fig. 3 as an example. Its output is also controlled by a control signal Adjin from the outside and an Error signal Error from the data channel high common mode transient suppression differential signal receiving circuit 4. The protection channel digital control circuit 10 may also be implemented by using the same digital control circuit, except that the signals Adjin, Error, and Din are not connected.

Fig. 4 is a structural diagram of a modulation transmission circuit according to the present invention, in which the modulation scheme adopted by the modulation transmission circuit is pulse counting modulation, and the rising edge and the falling edge of the input signal are separated by using a method of double-pulse depicting the rising edge of the input signal and single-pulse depicting the falling edge of the input signal to generate the corresponding pulse driving signal. The modulation transmission circuit of the invention adopts 2 groups of circuits shown in fig. 4, signals in the figure are marked by taking a data channel modulation transmission circuit 5 as an example: DxP is input data, R1 and R2 are high frequency refresh signals, and the output is a modulated pulse signal TxN. The refresh signals R1 and R2 correspond to the refresh command signals of a falling edge single pulse and a rising edge double pulse, respectively, and the circuit operates normally when the signal is high, and performs a refresh operation to refresh the circuit when the signal is low. Besides logic gates, the DELAY module for time DELAY is also arranged in the circuit and consists of inverters, capacitors and Schmitt triggers. The specific length of the delay is controllable, and the delay time can be controlled by changing the size of the capacitor or the number of the inverters. And the Schmitt trigger is connected behind the capacitor to avoid the uncertain influence caused by unstable voltage at two ends of the capacitor.

Because of the large voltage difference in the substrate potential between the transmitting-side circuit and the receiving-side circuit, electrical isolation between the high-voltage and low-voltage circuits is necessary. Due to the wide difference in application scenarios of power semiconductor devices, the voltage difference VGND (VGND1-VGND2) existing between the maximum values of the high and low voltage regions can span from 40V to 6500V. The VGND directly determines the electrical isolation grade in the chip, and different grades of electrical isolation are realized in the chip to form a circuit, so that the technology and cost quality grade of circuit devices required to be adopted are greatly different. The invention adopts the insulation isolation technology of capacitance isolation to isolate the high-low voltage signal processing circuit in physical space, thus realizing ultra-high voltage electrical isolation of more than 3000V.

In the implementation of the present invention shown in fig. 1, the transmitting-side circuit and the receiving-side circuit are connected to the ground voltages Vgnd1 and Vgnd2, respectively, wherein an isolation circuit is provided to isolate the two ground voltages Vgnd1 and Vgnd 2. However, since there is usually a certain level of common mode transient noise between the two ground voltages Vgnd1 and Vgnd2, the signal will generate errors during transmission. The common mode transient noise VGND is generally defined to be equal to the voltage difference (VGND1-VGND2), and for a typical application scenario of a 1200V SiC MOSFET, the common mode transient noise VGND will periodically rise rapidly from 0V to 1200V, and then fall rapidly from 1200V to 0V. Under the interference of the common mode transient noise VGND, the voltage Vcm (Vcm ═ RxP + RxN)/2) will produce a spike error, inevitably causing data error of the receiving circuit, and the common mode transient noise effect will be further worsened as the switching frequency increases. Therefore, in order to realize the high-reliability driving of the SiC MOSFET device and effectively suppress the common-mode transient noise, the invention adopts the high-common-mode transient suppression differential signal receiving circuit.

In the invention, the protection channel high common mode transient suppression differential signal receiving circuit 6 and the data channel high common mode transient suppression differential signal receiving circuit 4 are realized by adopting the same high common mode transient suppression differential signal receiving circuit. Fig. 5 is a structural diagram of a high common mode transient suppression differential signal receiving circuit according to the present invention, in which signals are identified by taking a protection channel high common mode transient suppression differential signal receiving circuit 6 as an example, the circuit includes: the circuit comprises a differential input receiving circuit 1, an X-stage tandem common mode adjustable amplifying circuit 602(CM 1-CMX), a high-sensitivity common mode adjustable amplifying circuit 603(CMN), a first output shaping circuit 604 and a common mode adaptive adjusting circuit 605. The differential input receiving circuit 1 first receives the differential signals (positive terminal receiving signal RxP and negative terminal receiving signal RxN) coupled from the transmitting terminal circuit shown in fig. 2 through the isolation circuit 10, and obtains a positive terminal input signal Vip and a negative terminal input signal Vin through filtering processing; vip and Vin enter a first-pole common-mode adjustable amplifying circuit CM1 of an X-stage common-mode adjustable amplifying circuit 602 cascaded in front and behind, and finally a positive-end output signal VoXp and a negative-end output signal VoXn of the X-stage common-mode adjustable amplifying circuit are obtained; VoXp and VoXn are respectively connected to the positive input terminal and the negative input terminal of the high-sensitivity common-mode adjustable amplifier circuit 603(CMN), so as to obtain differential output signals (a positive-side output signal VoNp and a negative-side output signal VoNn) of the high-sensitivity common-mode adjustable amplifier circuit 603; the first output shaping circuit 604 processes the resulting data output Dout according to the magnitudes of von p and von. The common mode adaptive adjusting circuit 605 adaptively generates common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2, CN1 and CN2 for each stage of amplifying circuit according to the change of power supply and ground voltage signals, and common mode adjusting signals C11 and C12 generated by the common mode adaptive adjusting circuit 605 are respectively connected to a common mode adjusting signal input end of the first stage of common mode adjustable amplifying circuit CM 1; the common mode adjusting signal C21 and the common mode adjusting signal C22 are respectively connected to a common mode adjusting signal input end of the second-stage common mode adjustable amplifying circuit CM 2; … … and so on, the common mode adjusting signal CX1 and the common mode adjusting signal CX2 are respectively connected to the common mode adjusting signal input terminal of the X-th common mode adjustable amplifying circuit CMX; the common mode adjustment signal CN1 and the common mode adjustment signal CN2 are respectively connected to the common mode adjustment signal input terminal of the high-sensitivity common mode adjustable amplification circuit 603 (CMN). Wherein X is a positive integer greater than 1, and N is a positive integer greater than X.

In fig. 5, the internal of the common-mode adaptive adjustment circuit 605 automatically detects the magnitude of the transient common-mode noise caused by the fluctuation of the power supply voltage VDD and the ground potential Vgnd2 of the receiving circuit, and when the transient common-mode noise exceeds a certain threshold, adjusts the values of the common-mode adjustment signals C11, C12, C21, C22, …, CX1, CX2, CN1, and CN2 and correspondingly outputs the values to the X-stage front-and-back cascade common-mode adjustable amplification circuits CM1 to CMX and the high-sensitivity common-mode adjustable amplification circuit 603(CMN), so as to adjust the common-mode levels of the X-stage front-and-back cascade common-mode adjustable amplification circuits CM1 to CMX and the high-sensitivity common-mode adjustable amplification circuit 3, and compensate the influence of the. Besides the common mode adaptive adjustment, the invention also adopts the high-reliability first output shaping circuit 604 and adopts the combined filtering of RC low-pass filtering and Schmitt trigger to filter the influence of high-frequency noise, and finally obtains the data output Dout which is not influenced by the transient common mode noise.

Fig. 6 shows an implementation of the differential input receiving circuit 601 of the present invention, which is composed of a positive side isolation capacitor C51, a positive side ground resistor R51, a positive side coupling capacitor C52, a positive side common mode resistor R53, a negative side isolation capacitor C53, a negative side ground resistor R52, a negative side coupling capacitor C54, a negative side common mode resistor R54, and a receiving common mode generating circuit 6011. The left end of the positive side isolation capacitor C51 and the left end of the negative side isolation capacitor C53 are connected to the positive side receive signal RxP and the negative side receive signal RxN, respectively; the right end of the positive side isolation capacitor C51 is connected to the lower end of the positive side ground resistor R51 and the left end of the positive side coupling capacitor C52; the right end of the negative side isolation capacitor C53 is connected to the lower end of the negative side ground resistor R52 and the left end of the negative side coupling capacitor C54; the right end of the positive terminal coupling capacitor C52 is connected to the upper end of the positive terminal common mode resistor R53 and serves as the output terminal of the positive terminal input signal Vip; the right end of the negative end coupling capacitor C54 is connected to the lower end of the negative end common mode resistor R54 and serves as the output end of a negative end input signal Vin; the lower end of the positive common-mode resistor R53 is connected to the upper end of the negative common-mode resistor R54, and is also connected to the common-mode output terminal Vicm of the receiving common-mode generating circuit 6011.

In the circuit shown in FIG. 6, the positive side isolation capacitor C51 and the negative side isolation capacitor C53 are high-voltage capacitors, and the size of the capacitors is usually dozens of fp; the positive side coupling capacitor C52 and the negative side coupling capacitor C54 are low voltage capacitors, and the capacitance values thereof are relatively small. The positive side receiving signal RxP and the negative side receiving signal RxN are input to output, and are filtered by 2 stages of DC blocking coupling to obtain a positive side input signal Vip and a negative side input signal Vin. The common mode level of the positive side input signal Vip and the negative side input signal Vin is provided by the receive common mode generation circuit 6011.

Fig. 7 shows an implementation manner of the receiving common mode generating circuit 6011 according to the present invention. The circuit is composed of an NMOS tube M60, an NMOS tube M61, a PMOS tube M62, an NMOS tube M63, a PMOS tube M64, a PMOS tube M65, an NMOS tube M66, an NMOS tube M67, a PMOS tube M68, an NMOS tube M69, a PMOS tube M610, an NMOS tube M611, a PMOS tube M612, an NMOS tube M613, an NMOS tube M614, a PMOS tube M615 and a resistor R61; the schmitt trigger 600 is composed of a PMOS transistor M64, a PMOS transistor M65, an NMOS transistor M66, an NMOS transistor M67, a PMOS transistor M68 and an NMOS transistor M69.

The grid electrode of the NMOS tube M60 is connected to an input common mode voltage Vcm; the drain electrode of the NMOS tube M60 is connected to the drain electrode and the gate electrode of the PMOS tube M62 and the gate electrode of the NMOS tube M63; the grid electrode of the NMOS tube M61 is connected to an input common mode control signal Vctrl; the drain electrode of the NMOS tube M61 is connected with the drain electrode of the NMOS tube M63 and is connected to the input end of the Schmitt trigger 600; the output end of the Schmitt trigger 600 is simultaneously connected to the gates of a PMOS transistor M610, an NMOS transistor M611, a PMOS transistor M612 and an NMOS transistor M613; the drain electrode of the PMOS tube M610 is connected with the drain electrode of the NMOS tube M611 and is also connected to the grid electrode of the NMOS tube M614; the drain of the PMOS tube M612 is connected with the drain of the NMOS tube M613, and is also connected to the gate of the PMOS tube M615; the source electrode of the NMOS tube M614 is connected with the source electrode of the PMOS tube M615 and is also used as an output port of the common mode output end Vicm; the drain electrode of the NMOS tube M614 is connected to a high input common mode level Vcmh, and the drain electrode of the PMOS tube M615 is connected to a low input common mode level Vcml; the source of the NMOS transistor M613 is connected to the upper end of the resistor R61; the source electrode of the NMOS tube M60, the source electrode of the NMOS tube M61, the source electrode of the NMOS tube M611 and the lower end of the resistor R61 are connected to the ground voltage; the source electrode of the PMOS transistor M62, the source electrode of the NMOS transistor M63, the source electrode of the PMOS transistor M64 and the source electrode of the PMOS transistor M610 are simultaneously connected to a power supply voltage. The ground terminals of this circuit are each connected to the receiving circuit ground voltage.

The function of the circuit shown in fig. 7 is to dynamically track and adjust the size of the common-mode output end Vicm according to the change of the input common-mode Vcm, so as to reduce the influence of the input common-mode. If the input common mode Vcm is reduced, the input end of the schmitt trigger 600 will be synchronously reduced, and if the fluctuation exceeds the threshold of the schmitt trigger 600, the output of the schmitt trigger 600 will become high level, the PMOS transistor M615 will be turned on, and the common mode output end Vicm will output low input common mode level Vcml to match with the input common mode; assuming that the input common mode Vcm increases and exceeds the threshold of the schmitt trigger 600, the NMOS transistor M614 is turned on, and the common mode output terminal Vicm outputs a high input common mode level Vcmh; it can be seen that the circuit of fig. 7 can achieve dynamic compensation of input common mode variation for different input common mode fluctuations. In the circuit shown in fig. 7, in order to better realize the output of the common mode signal at the common mode output end Vicm, an NMOS transistor is used for transmitting a high input common mode level Vcmh, and a PMOS transistor is used for transmitting a low input common mode level Vcml.

Fig. 8 shows an implementation of a cascade unit of the common mode adjustable amplifier circuit according to the present invention. The circuit is a fully differential single-stage amplifying circuit, and the left side of the circuit comprises a PMOS tube M71 and an NMOS tube M73 which are connected in series through a drain electrode; the source electrode of the PMOS tube M71 is connected with a power supply VDD, a capacitor C71 is connected between the grid electrode and the source electrode of the PMOS tube M71, and a bias resistor R71 is connected between the grid electrode and the drain electrode of the PMOS tube; the drain output negative terminal output signal Vo1n of the NMOS transistor M73 is connected to the negative input terminal of the next cascade unit (the second cascade unit outputs the negative terminal output signal Vo2n to the next cascade unit, and so on), and the gate of the NMOS transistor M73 is connected to the positive input terminal Vip of the common mode adjustable amplifier circuit 602; the right side of the circuit comprises: a PMOS transistor M72 and an NMOS transistor M74 which are connected in series through drains; the source electrode of the PMOS tube M72 is connected with a power supply VDD, a capacitor C72 is connected between the grid electrode and the source electrode of the PMOS tube M72, and a bias resistor R72 is connected between the grid electrode and the drain electrode of the PMOS tube M72; the drain of the NMOS transistor M74 outputs a positive end output signal Vo1p to the positive input terminal of the next cascade unit (the second cascade unit outputs a positive end output signal Vo2p to the next cascade unit, and so on), and the gate of the NMOS transistor M74 is connected to the negative input terminal Vin of the common mode adjustable amplifier circuit 602; the sources of the PMOS tube M71 and the PMOS tube M72 at the two sides of the amplifying circuit are connected in parallel, and the sources of the NMOS tube M73 and the NMOS tube M74 are connected in parallel; the source electrodes of the NMOS transistor M73 and the NMOS transistor M74 are connected with the drain electrodes of the NMOS transistor M75, the NMOS transistor M76 and the NMOS transistor M77 which are grounded; the grid electrode of the ground NMOS tube M75 is connected with a bias voltage Vb1, and provides bias current required by normal operation of the amplifier; the gates of the NMOS transistor M76 and the NMOS transistor M77 are connected to common mode adjustment signals C11 and C12, respectively.

As can be seen from the circuit of fig. 8, by changing the magnitudes of the common mode adjustment signals C11 and C12, the bias currents flowing through the NMOS transistor M73 and the NMOS transistor M74 change, and the output voltages of the negative side output signal Vo1n and the positive side output signal Vo1p of the cascade unit change correspondingly and simultaneously, so as to adjust the output common mode voltage. The invention adopts a plurality of stages of the same common-mode adjustable amplifying circuits which are cascaded in front and back as shown in fig. 9, and the positive-end output signal VoXp and the negative-end output signal VoXn are output by the X-th stage common-mode adjustable amplifying circuit CMX, so that the dynamic compensation of the common-mode noise is finally realized.

Fig. 9 shows an implementation of the high-sensitivity common-mode tunable amplifier circuit 603 according to the present invention. The circuit is a front-stage and a rear-stage fully differential amplifying circuits, the front-stage common mode adjustable amplifying circuit adopts an amplifying circuit structure similar to that of fig. 9, and the rear-stage amplifying circuit is a differential amplifying circuit (DDA). The positive input end of the preceding common mode adjustable amplifier circuit is the positive input end of the high-sensitivity common mode adjustable amplifier circuit 603, and the negative input end of the preceding common mode adjustable amplifier circuit is the negative input end of the high-sensitivity common mode adjustable amplifier circuit 603; the positive output terminal VoNp of the differential amplifier circuit is the positive output terminal of the high-sensitivity common mode adjustable amplifier circuit 603, and the negative output terminal VoNn of the differential amplifier circuit is the negative output terminal of the high-sensitivity common mode adjustable amplifier circuit 603.

The left side of the front-stage common mode adjustable amplifying circuit comprises a PMOS tube M81 and an NMOS tube M83 which are connected in series through a drain electrode; the source electrode of the PMOS tube M81 is connected with a power supply VDD, a capacitor C81 is connected between the grid electrode and the source electrode of the PMOS tube M81, the grid electrode of the PMOS tube M81 is also connected to the upper end of a bias resistor R81, and the drain electrode of the PMOS tube M81 is also connected to the lower end of the bias resistor R82; the lower end of the bias resistor R81 is connected with the upper end of the bias resistor R82 and is also used as a first signal input end of the differential amplification circuit; the drain of the NMOS transistor M83 is connected with the drain of a PMOS transistor M81 and is also connected with the third signal input end of the differential amplifying circuit; the grid electrode of the NMOS tube M83 is connected with the positive input end VoXp of the preceding-stage common-mode adjustable amplifying circuit; the right side of the circuit comprises a PMOS tube M82 and an NMOS tube M84 which are connected in series through a drain electrode; the source electrode of the PMOS tube M82 is connected with a power supply VDD, a capacitor C82 is connected between the grid electrode and the source electrode of the PMOS tube M82, the grid electrode of the PMOS tube M82 is also connected to the upper end of a bias resistor R83, and the drain electrode of the PMOS tube M82 is also connected to the lower end of the bias resistor R84; the lower end of the bias resistor R83 is connected with the upper end of the bias resistor R84 and is also used as a second signal input end of the differential amplifying circuit; the drain of the NMOS transistor M84 is connected with the drain of a PMOS transistor M82 and is also connected with the fourth signal input end of the differential amplifying circuit; the grid electrode of the NMOS tube M84 is connected with the negative input end VoXn of the preceding-stage common-mode adjustable amplifying circuit; the sources of the PMOS tube M81 and the PMOS tube M82 at the two sides of the amplifying circuit are connected in parallel, and the sources of the NMOS tube M83 and the NMOS tube M84 are connected in parallel; the source electrodes of the NMOS transistor M83 and the NMOS transistor M84 are connected with the drain electrodes of the NMOS transistor M85, the NMOS transistor M86 and the NMOS transistor M87 which are grounded; the grid electrode of the ground NMOS tube M85 is connected with a bias voltage Vb1, and provides bias current required by normal operation of the amplifier; the gates of the NMOS transistor M86 and the NMOS transistor M87 are connected to common mode adjustment signals CN1 and CN2, respectively.

The differential amplifier circuit includes: PMOS transistor M88, PMOS transistor M89, PMOS transistor M812, PMOS transistor M813, NMOS transistor M810, NMOS transistor M811, NMOS transistor M814, NMOS transistor M815 and resistor 85; the grid of the PMOS tube M88 is a first signal input end of the differential amplification circuit, the grid of the PMOS tube M89 is a second signal input end of the differential amplification circuit, the PMOS tube M812 is a third signal input end of the differential amplification circuit, and the PMOS tube M813 is a fourth signal input end of the differential amplification circuit; the drain electrode of the PMOS tube M88 is connected with the drain electrode of the PMOS tube M89, is connected with the drain electrode of the NMOS tube M810 and is used as a positive output end VoNp of the differential amplifying circuit; the drain electrode of the PMOS pipe M812 is connected with the drain electrode of the PMOS pipe M813 and is connected to the upper end of the resistor R85; the lower end of the resistor R85 is connected with the drain electrode of the NMOS tube M814 and is used as the negative output end VoNn of the differential amplifying circuit; the NMOS transistor M810 and the NMOS transistor M811 form a cascode current source structure, the NMOS transistor M814 and the NMOS transistor M815 form the cascode current source structure, the gates of the NMOS transistor M810 and the NMOS transistor M814 are connected with the same bias voltage Vb81, and the gates of the NMOS transistor M811 and the NMOS transistor M815 are connected with the same bias voltage Vb 82.

Fig. 10 is an implementation manner of the first output shaping circuit 604 of the present invention, which includes a PMOS transistor M401, a PMOS transistor M402, a PMOS transistor M403, a PMOS transistor M404, a PMOS transistor M405, a PMOS transistor M406, a PMOS transistor M409, an NMOS transistor M407, an NMOS transistor M408, an NMOS transistor M4010, a resistor R401, a resistor R402, a PMOS transistor M41, a PMOS transistor M43, a PMOS transistor M45, a PMOS transistor M46, a PMOS transistor M49, a PMOS transistor M411, an NMOS transistor M42, an NMOS transistor M44, an NMOS transistor M47, an NMOS transistor M48, an NMOS transistor M410, an NMOS transistor M412, a resistor R41, a resistor R42, and a capacitor C41.

The PMOS transistor M401, the PMOS transistor M402, the PMOS transistor M403, the PMOS transistor M404, the PMOS transistor M405, the PMOS transistor M406, the PMOS transistor M409, the NMOS transistor M407, the NMOS transistor M408, the NMOS transistor M4010, the resistor R401 and the resistor R402 form a three-stage comparator; the PMOS tube M41, the PMOS tube M43, the NMOS tube M42, the NMOS tube M44, the resistor R41, the resistor R42 and the capacitor C41 form a buffer with an RC filtering function; a Schmitt trigger is formed by a PMOS tube M45, a PMOS tube M46, a PMOS tube M49, an NMOS tube M47, an NMOS tube M48 and an NMOS tube M410; the PMOS transistor M411 and the NMOS transistor M412 form an output inverter. The input end of the buffer with the RC filtering function is connected to the comparison output voltage Vo1 of the wide voltage range comparator circuit, the output end of the buffer with the RC filtering function is connected to the input end of the schmitt trigger, the output end of the schmitt trigger is connected to the input end of the output inverter, and the output end of the output inverter is the final data output Dout of the high common mode transient suppression differential signal receiving circuit 6.

The internal circuit structure of the three-level comparator is as follows: the PMOS tube M401, the PMOS tube M402, the PMOS tube M403, the resistor R401 and the resistor R402 form an input stage of a three-stage comparator, the PMOS tube M404, the PMOS tube M405, the PMOS tube M406, the NMOS tube M407 and the NMOS tube M408 form an amplification stage of the three-stage comparator, and the PMOS tube M409 and the NMOS tube M4010 form an output stage of the three-stage comparator; the connection relationship of the internal circuit of the buffer with the RC filtering function is as follows: the grid electrodes of the PMOS tube M41 and the NMOS tube M42 are connected to the comparison output voltage of the three-stage comparator, the drain electrodes of the PMOS tube M41 and the NMOS tube M42 are connected to the grid electrodes of the PMOS tube M43 and the NMOS tube M44, the drain electrode of the PMOS tube M43 is connected to the upper end of the resistor R41, the lower end of the resistor R41 is connected to the upper end of the resistor R42, the upper end of the capacitor C41 and the input end of the Schmidt trigger, the lower end of the resistor R42 is connected to the drain electrode of the NMOS tube M44, the simultaneous source electrodes of the PMOS tube M41 and the PMOS tube M43 are connected to the power supply voltage, and the source electrodes of the NMOS tube M42 and the NMOS tube M44 and the lower end.

The first output shaping circuit 604 of the present invention shown in fig. 10 provides, on the one hand, a three-stage comparator for converting an input differential signal into a standard digital logic signal Dout; on the other hand, the RC low-pass filtering and the Schmitt trigger combined filtering are adopted, and a certain hysteresis quantity is kept so as to effectively filter the high-frequency interference influence caused by the common-mode noise.

Fig. 11 is a specific implementation of the common mode adaptive adjustment circuit 605 of the present invention, which includes a first common mode detection circuit 100, a common mode detection signal transmission circuit 101, an adjustment common mode signal generation circuit 102, and a common mode adjustment signal selection circuit 103. The first common mode detection circuit 100 is configured to detect power supply and substrate noise, and change the magnitude of a common mode detection signal Vcm _ det when the noise is greater than a certain threshold, where the common mode detection signal Vcm _ det is connected to the common mode detection signal transmission circuit 101, and the Vcm _ det generates common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2, NN1, NN2 through the common mode detection signal transmission circuit 101, and outputs the common mode selection switch control signals N11, N12, N21, N22, N2, NX1, NX2, NN1, and NN 2; the common mode adjusting signal selecting circuit 103 generates and adjusts the magnitude of the common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2, CN1 and CN2 according to the common mode selecting switch control signal and outputs the common mode adjusting signals; the adjustment common mode signal generating circuit 102 is configured to generate various common mode bias signals required by the common mode adjustment signal selecting circuit 103, and output the common mode bias signals to the common mode adjustment signal selecting circuit 503.

In the circuit shown in fig. 11, the common mode detection signal transmission circuit 101 is implemented by using a distributed inverter chain, and the common mode detection signal Vcm _ det is propagated through N sets of distributed inverter chains to obtain N sets of common mode control signals. The adjustment common mode signal generating circuit 102 generates a high input common mode level Vcmh and a low input common mode level Vcml through a bias signal path from the power supply voltage VDD to SW. For the implementation of Vcmh and Vcml, an implementation with the minimum hardware overhead is shown in the figure, and the same function can be realized by adopting reference voltage division or other circuits such as LDO and the like, which are not described herein. The common mode adjusting signal selecting circuit 103 has an internal circuit of a switch selecting array, and the switch array determines the outputs of the common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2, CN1 and CN2 according to the values of the common mode selecting switch control signals N11, N12, N21, N22, …, NX1, NX2, NN1 and NN 2.

Fig. 12 and 13 show the implementation and operation waveforms of the common mode detection circuit according to the present invention. The common mode detection circuit is used for detecting power supply and substrate noise, and changing the size of a common mode detection signal Vcm _ det when the noise is larger than a certain threshold value so as to control the output of the common mode self-adaptive adjusting circuit provided in the figure 11. The common mode detection circuit is composed of a PMOS tube M111, a PMOS tube M112 and an NMOS tube M113; the grid electrode and the drain electrode of the PMOS tube M111 are connected, and the grid electrode is connected with the drain electrode of the PMOS tube M112 and the grid electrode of the NMOS tube M113; the grid electrode of the PMOS tube M112 is connected with the drain electrode of the NMOS tube M113 and is used as an output node of a common mode detection signal Vcm _ det; the sources of the PMOS transistors M111 and M112 are connected to a power supply voltage, and the source of the NMOS transistor M113 is connected to a ground voltage.

Take the operating voltage of the first common mode detection circuit 100 as an example. The typical high-voltage half-bridge gate driving circuit is divided into two paths of driving circuit channels of a high side and a low side, and the high side driving circuit adopts a bootstrap boosting mode to realize signal transmission control. Assuming that the circuit operates in a high side driver circuit of a half bridge gate driver chip, Vgnd2 is connected to a half bridge output SW, which swings between 0 and Vgnd; VDD is connected to a power supply voltage VHB of the high-side driver circuit, and VHB is bootstrap-floated by a bootstrap capacitor based on the SW potential, so that the bootstrap voltage VDD is VHB SW + VCC during normal operation. Because capacitor bootstrap charging also needs a certain charging time, in the capacitor charging process, the bootstrap voltage cannot completely synchronize with the fluctuation of the SW, which leads to a certain delay of VDD relative to the SW, the voltage difference between the power supply and the ground in the delay interval is not strictly equal to VCC, which is equivalent to power supply common mode noise, when the noise amplitude is large enough, the circuit function is influenced, and false triggering of the comparator is generated.

As shown by the waveforms on the right side of fig. 13, when the half-bridge output SW is stable, the VDD and Vgnd2 voltages are in a stable state, M111 is on, M113 is on, and Vcm _ det will be pulled down to Vgnd2 by M113, and is at a low level; when the half-bridge output SW is switched from 0 to VGND, Vgnd2 is synchronously switched to VGND, but VDD has a certain delay, a certain delay interval is generated, VDD does not reach VGND + VCC in the delay interval, the grid voltage of M113 is not enough to enable M113 to be turned on, M113 is turned off, Vcm _ det is influenced by Vgnd2 under the action of parasitic capacitance to generate a peak-high pulse until VDD reaches VGND + VCC, at the moment, M113 is turned on again, and Vcm _ det is pulled down to Vgnd2 by M113.

As shown in fig. 1, the total isolation of the capacitive isolation SiC MOSFET driving chip of the present invention is realized by two sets of isolation capacitors (Ctp and Crp form a set of P-end series isolation capacitors, Ctn and Crn form a set of N-end series isolation capacitors) arranged in series to achieve voltage-withstanding isolation, and the middle is connected to the upper plates of the two series isolation capacitors through Bonding wires (Bonding wires), so that the total voltage-withstanding value of the capacitive isolator chip is the sum of the voltage-withstanding values of the two capacitors in the series capacitors. Usually SiO₂If the first layer M1 is used as the lower plate of the isolation capacitor and the sixth layer M6 is used as the upper plate of the isolation capacitor, then SiO between the metal layers is formed₂The total thickness is about 6-7 um, that is to say, the withstand voltage of a single isolation capacitor is about 3000V-3500V, and the withstand voltage of two isolation capacitors is about 6000V-7000V. The voltage resistance can meet common and conventional application, and cannot meet the voltage resistance requirement of ultrahigh voltage isolation.

As shown in fig. 14, the present invention provides an ultra high withstand voltage separating capacitor, including: a deep N-well isolation region DNWELL 50, a lower plate (a first layer M1)51, an upper plate 54 and SiO arranged between the lower plate 51 and the upper plate 54 from bottom to top₂A layer 52 and a passivation layer 53, the passivation layer 53 being SiO₂And Si₃N₄And (3) superposition. Wherein, SiO₂The layer thickness mainly is VIA12, M2 (second layer), VIA23, M3 (third layer), VIA34, M4 (fourth layer), VIA45, M5 (fifth layer), VIA56, M6 (sixth layer), and the sum thickness is 8 ~ 9um, and the thickness of passivation layer 53 is 2 ~ 3 um. Si in the passivation layer 53₃N₄Is arranged on SiO in an overlapping way₂Above because of Si₃N₄Having a specific SiO ratio₂Better compactness and pressure resistance. The upper plate 54 is made of metal Cu, and the upper plate 54 is formed by processing the rear end of the wafer, and a layer of metal Cu is formed on the passivation layer 53, and the metal Cu also serves as a PAD. A deep N-well isolation region DNWELL 50 is arranged below the lower polar plate 51, and a substrate of a wafer is arranged below the deep N-well isolation region 50; the area of the deep N-well isolation region 50 should be larger than the plane surface of the lower polar plate 51And entirely covers the lower surface of the lower plate 51.

According to the scheme of the ultrahigh voltage-withstanding isolation capacitor, the thickness of a passivation layer is controlled to be about 2.5um through process adjustment, the thickness of a single isolation capacitor is about 12um approximately, and the voltage withstanding value can reach 6000V, so that the total thickness of two isolation capacitors connected in series is about 24um, the total voltage withstanding value can reach 12000V, the requirement of isolation enhancement can be met, the capacitance value is reduced after the isolation capacitors are thickened, the area of an isolation capacitor plate can be properly increased, the capacitance value of the isolation capacitors can be basically kept unchanged, and the transmission quality of the whole isolation signal is not influenced.

The low voltage power supply circuit is a basic functional module that any analog IC must be equipped with, and a block diagram of an implementation structure that the transmitting-side low voltage generation circuit 3 and the receiving-side low voltage generation circuit 8 of the present invention can use is shown in fig. 15. The circuit internally comprises: a start-up circuit 801, a bandgap reference voltage generation circuit 802, a reference voltage generation circuit and buffer circuit 803, a bias signal generation circuit 804, and an input low voltage generation circuit 805. Taking the sending terminal low voltage generating circuit 3 as an example, after the chip VCC voltage is powered on, the starting circuit 801 is the circuit which is started first in the whole chip, and the starting circuit usually provides a certain initial bias signal to generate a fixed reference voltage and a fixed reference current for the band gap reference voltage generating circuit 802; the reference voltage is then used for generating various reference voltages V required by the internal work of the chip through a reference voltage generating circuit_R1、V_R2～V_RnOutput through a buffer circuit; the reference current typically enters bias signal generation circuit 804, which generates various types of bias signals for biasing other analog circuits within the chip, as well as providing bias to reference voltage generation circuit and input low voltage generation circuit 805. The input low voltage generation circuit 805 typically generates a 3-10V floatable low voltage supply voltage VCL.

Fig. 16 is a structural diagram of the high-precision wide-voltage-range overheat protection circuit of the present invention. The circuit of the present invention includes a clamp circuit 1401, a temperature detection circuit 1402, a wide voltage range comparator circuit 1403, and a second output shaping circuit 1404. The temperature detection circuit 1402 obtains a first temperature detection output signal Vin1 and a second temperature detection output signal Vin2 according to the bias voltage Vb provided by the clamping circuit 1401; the wide voltage range comparator circuit 1403 compares the first temperature detection output signal Vin1 and the second temperature detection output signal Vin2 to obtain a comparison output signal Vo 1; the second output shaping circuit 1404 processes the comparison output signal Vo1 to obtain a temperature protection signal OTLock and an OTP, where the OTLock is a digital logic signal, the OTLock is connected to the clamping circuit 1401 for controlling the magnitude of the bias voltage Vb, and the OTP is output to the digital control circuit as a control signal.

When the temperature of the chip is normal, the temperature protection signal OTLock is at a high level, and the high level of the OTLock controls the clamp circuit 1401 to generate a higher bias voltage Vb; the temperature detection circuit 1402 generates a first temperature detection output signal Vin1 and a second temperature detection output signal Vin2 according to the bias voltage Vb and the temperature signal. The comparison output signal Vo1 obtained by the wide voltage range comparator circuit 1403 according to the first temperature detection output signal Vin1 and the second temperature detection output signal Vin2 should be a high level signal in the normal case; the second output shaping circuit 1404 processes the comparison output signal Vo1 to obtain a temperature protection signal OTLock which is also a high-level logic signal.

When the chip temperature is abnormal, the first temperature detection output signal Vin1 and the second temperature detection output signal Vin2 generated by the temperature detection circuit 1402 will change, the wide voltage range comparator circuit 1403 changes the comparison output signal Vo1 obtained according to the first temperature detection output signal Vin1 and the second temperature detection output signal Vin2 into a low level signal, the temperature protection signal OTLock obtained by the second output shaping circuit 1404 also changes into a low level logic signal, the temperature protection signal OTLock becomes a low level, the OTLock low level will control the clamp circuit to generate a lower bias voltage Vb, and the bias voltage Vb will further change the magnitude of the first temperature detection output signal Vin1 and the second temperature detection output signal Vin2, so that the comparison output signal Vo1 of the wide voltage range comparator circuit 1403 is further locked into a low level signal.

When the high-voltage gate driving chip works normally, the power supply voltage and the substrate potential of the high-voltage gate driving chip usually have huge fluctuation, and very serious common mode noise is generated. In order to overcome the serious influence of the common mode noise, on one hand, the wide voltage range comparator circuit 1403 is adopted to compare the first temperature detection output signal Vin1 and the second temperature detection output signal Vin2 generated by the temperature detection circuit 1402, the wide voltage range comparator circuit 1403 can automatically detect the common mode noise generated by the power supply voltage and the substrate potential, and automatically close the output of the wide voltage range comparator circuit 1403 when the common mode noise exceeds a certain threshold value, so that the effectiveness of the comparison output signal Vo1 is not influenced by the common mode noise. On the other hand, the second output shaping circuit 1404 further employs RC low-pass filtering and schmitt trigger combined filtering to filter the influence of high-frequency noise, so as to generate a stable and reliable temperature protection output signal OTLock.

Fig. 17 shows an implementation of the clamp 1401 of the present invention, which is composed of a PMOS transistor M11, an NMOS transistor M12, an NMOS transistor M13, a resistor R11, a resistor R12, and a resistor R13; the source electrode of the PMOS pipe M11 is connected with the upper end of the resistor R11 and is also connected to the power supply voltage; the grid electrode of the PMOS tube M11 is connected with the grid electrode of the NMOS tube M12 and is simultaneously connected with a temperature protection signal OTLock; the drain electrode of the PMOS tube M11 is connected with the drain electrode of the NMOS tube M12 and is simultaneously connected with the grid electrode of the NMOS tube M13; the source electrode of the NMOS transistor M12 is connected with the lower end of the resistor R13 and the source electrode of the NMOS transistor M13 and is simultaneously connected to the ground voltage; the drain electrode of the NMOS tube M13 is simultaneously connected with the upper end of the resistor R13 and the lower end of the resistor R12; the upper end of the resistor R12 is connected to the lower end of the resistor R11 and serves as an output node of the bias voltage Vb of the clamp 1401.

In the clamp circuit 101, a power supply voltage VCC is subjected to real-time voltage division detection by voltage division resistors R11, R12 and R13, a voltage value Vb obtained by voltage division is input into a temperature detection circuit 1402, a resistance value of the R13 is controlled by M13, and the on and off of the M13 are controlled by an OTLock signal. When the OTLock signal is at a high level, the gate of M13 is low, M13 is in an off state, R13 is a large resistor, and the voltage value Vb obtained by voltage division is a high bias voltage; when the OTLock signal is at a low level, the gate of M13 is high, M13 is in a conducting state, R13 is shorted by M13 to be a small resistor, and at this time, the divided voltage value Vb is a low bias voltage.

Fig. 18 shows an implementation of the temperature detecting circuit 1402 of the present invention, which is composed of a PMOS transistor M21, a PMOS transistor M22, a resistor R21, a transistor Q1, and a transistor Q2; the base electrode of the triode Q1 and the base electrode of the triode Q2 are connected, and the triode Q1 and the base electrode of the triode Q2 are connected to the bias voltage Vb output node of the clamping circuit 101; an emitter of the triode Q1 is connected to a gate and a drain of the PMOS transistor M21, and the node voltage of the triode Q1 is used as a first temperature detection output signal Vin 1; an emitter of the triode Q2 is connected to the gate and the drain of the PMOS transistor M22, and the node voltage of the triode Q2 is used as a second temperature detection output signal Vin 2; the source electrode of the PMOS pipe M21 is connected with the source electrode of the PMOS pipe M22 and is connected to a power supply voltage; the collector of the transistor Q2 is connected to the upper end of the resistor R21; the lower end of the resistor R21 is connected to the collector of the transistor Q1 and to the ground voltage GND. The width-length ratio of the PMOS tube M21 to the length-width ratio of the PMOS tube M22 are equal, and the base area ratio of the triode Q1 to the base area ratio of the triode Q2 is 1: n (N is a natural number).

The principle adopted by the circuit temperature detection in fig. 18 is that the voltage of the Vbe junction of the transistor has a negative temperature coefficient characteristic, and the negative temperature coefficients of the Vbe junctions with different current densities are different, so under the same bias voltage condition, the voltages generated on the two Vbe junctions with different current densities generate a voltage difference with the temperature change, and the voltage difference is linearly increased with the temperature change. In fig. 18, the base area ratio of transistor Q1 to transistor Q2 is 1: n, the emitters output voltages respectively, and the first temperature detection output signal Vin1 and the second temperature detection output signal Vin2 generate a voltage difference Vt which varies linearly with temperature, Vin1-Vin 2. By adjusting the size of the resistor R21, Vt is set to be a negative value less than 0 when the temperature is low; when the temperature rises, the value of the second temperature detection output signal Vin2 will decrease at a faster rate due to the larger base area of the transistor Q2, and the voltage difference Vt will increase with the rise of the temperature; when the temperature exceeds a certain value, Vt will change from negative voltage to positive voltage, and the comparison output voltage Vo1 of the wide voltage range comparator circuit 103 will change, and the output voltage Vo1 will change from high to low. When the base voltages Vb of the transistor Q1 and the transistor Q2 decrease, the voltage difference Vt will further increase, thereby locking the comparison output voltage Vo 1.

Fig. 19 shows an implementation manner of the wide voltage range comparator circuit 1403, which is composed of a PMOS transistor M31, a PMOS transistor M33, a PMOS transistor M35, a PMOS transistor M36, a PMOS transistor M37, a PMOS transistor M39, an NMOS transistor M32, an NMOS transistor M34, an NMOS transistor M38, an NMOS transistor M310, and a second common mode detection circuit 1031. The grid electrode of the PMOS tube M31 is connected to the first temperature detection output signal Vin1, and the grid electrode of the PMOS tube M33 is connected to the second temperature detection output signal Vin 2; the drain electrode of the PMOS tube M31 is connected to the drain electrode and the gate electrode of the NMOS tube M32, the gate electrode of the NMOS tube M34 and the gate electrode of the NMOS tube M310; the drain electrode of the PMOS tube M33 is connected to the drain electrode of the NMOS tube M34 and the gate electrode of the PMOS tube M37; the drain electrode of the PMOS tube M37 is connected to the drain electrode and the grid electrode of the NMOS tube M38, and the source electrode of the PMOS tube M37 is connected to the grid electrode of the PMOS tube M39 and the drain electrode of the PMOS tube M36; the source electrode of the PMOS tube M36 is connected to the drain electrode of the PMOS tube M35, and the grid electrodes of the PMOS tube M36 and the PMOS tube M35 are both connected to the output control signal of the common mode detection circuit 1031; the drain of the PMOS transistor M39 is connected to the drain of the NMOS transistor M310 and outputs a comparison output voltage Vo 1; the sources of the PMOS transistor M31, the PMOS transistor M33, the PMOS transistor M35 and the PMOS transistor M39 are simultaneously connected to a power supply voltage; the sources of the NMOS transistor M32, the NMOS transistor M34, the NMOS transistor M38 and the NMOS transistor M310 are simultaneously connected to the ground voltage.

The second common mode detection circuit 1031 and the operation principle thereof employed in fig. 19 of the present invention may employ the same implementation manner as in fig. 12. In the circuit shown in fig. 19, the gate control signals of the PMOS transistor M36 and the PMOS transistor M35 are the same common mode control signal Vcm _ det, and the second common mode detection circuit 1031 can automatically detect the common mode noise generated by the power voltage and the substrate potential, and change the common mode control signal Vcm _ det when the common mode noise exceeds a certain threshold. When the common-mode noise amplitude and influence are limited and do not exceed the threshold, the common-mode control signal Vcm _ det is at a high level, the PMOS transistor M36 and the PMOS transistor M35 are both in an off state, and the grid electrode of the PMOS transistor M39 is controlled by the source electrode of the PMOS transistor M37; when the amplitude of the common mode noise is abnormal and exceeds a threshold value, the common mode control signal Vcm _ det is at a low level, the PMOS tube M36 and the PMOS tube M35 are both in a conducting state, the grid of the PMOS tube M39 is pulled high and enters a closing state, the comparison output voltage Vo1 is clamped to the low level, and the common mode noise is prevented from influencing the normal work of the comparator. The load resistors of the single-stage amplifying circuits adopted by the comparator circuit in fig. 19 are all realized by active diodes, so that the circuit can work under a wide range of power supply voltage conditions, and the applicable voltage conditions of the circuit are further expanded.

Fig. 20 shows an implementation of the second output shaping circuit 1404, which has a structure substantially identical to that of the output shaping circuit on the right side in fig. 10, and includes a buffer with an RC filtering function, a schmitt trigger, and an output inverter, which are connected in this order. The output end of the Schmitt trigger is connected to the input end of the output inverter, the output end of the output inverter is the temperature protection output signal OTLock, and the temperature protection output signal OTLock is output through one inverter to obtain the output signal OTP. The output shaping circuit of fig. 20, on the one hand, provides a standard digital logic signal, and converts the comparison output voltage Vo1 into a standard digital logic signal temperature protection output signal OTLock; another aspect is to filter out the high frequency interference effects caused by common mode noise and temperature fluctuations. The circuit adopts RC low-pass filtering and Schmitt trigger combined filtering, and a certain hysteresis quantity is kept to effectively prevent thermal shock of temperature and prevent the system from being frequently turned on and off when the circuit works at a certain temperature point to cause adverse effects on the system.

Fig. 21 and 22 are a structure diagram of an under-voltage protection circuit and a structure diagram of an over-current protection circuit, respectively, the circuit structures of the two protection circuits are similar to the over-temperature protection circuit structure shown in fig. 16, and both include: a clamp circuit, a wide voltage range comparator circuit and an output shaping circuit. Compared with the over-temperature protection circuit shown in fig. 16, the under-voltage protection circuit shown in fig. 21 is different in that a voltage detection circuit is used for detecting the magnitude of the power supply voltage, and the obtained sampling voltage is compared with a reference voltage signal to obtain output under-voltage protection signals UVLO and UVlock; UVlock is connected to the clamp circuit and is used for controlling bias voltage Vb size, and UVLO is given the digital control circuit as a control signal output. The voltage detection circuit can be realized by adopting a conventional resistance voltage division circuit. Compared with the over-temperature protection circuit shown in fig. 16, the over-current protection circuit shown in fig. 22 is different in that the current detection circuit is used to detect the magnitude of the current of the output power device, the obtained sampling current is usually converted into a voltage through a resistor, and the voltage is compared with a reference voltage signal to obtain output under-voltage protection signals OCP and OClock. OClock is connected to the clamping circuit and is used for controlling the size of the bias voltage Vb, and OCP serves as a control signal and is output to the digital control circuit.

Fig. 23 shows an implementation of the output driver circuit 7 according to the present invention. The power supply of the output driving circuit 7 is also VCC, the output driving circuit 7 is composed of a plurality of inverter chains with size amplified step by step and MOS tubes M221 and M222, the branch where the M221 and M222 tubes are located determines the output current of the driving circuit and also determines the output impedance of the circuit, therefore, the width-to-length ratio of the M221 and M222 is designed according to the requirements of the driving device. In order to make the SiC MOSFET device controlled by the output to be rapidly saturated on and reliably off, the output impedance of the output drive circuit 7 is required to be small and the output current to be large (several amperes).

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. High voltage insulation isolation SiC MOSFET gate drive circuit with protect function, characterized by includes: the device comprises an input receiving circuit (1), a data channel digital control circuit (2), a data channel modulation sending circuit (5), a first high-voltage isolation circuit (11), a protection channel high common mode transient suppression differential signal receiving circuit (6), a protection channel digital control circuit (10), a protection channel modulation sending circuit (9), a second high-voltage isolation circuit (12), a data channel high common mode transient suppression differential signal receiving circuit (4), an output driving circuit (7), a transmitting end low-voltage generating circuit (3), a receiving end low-voltage generating circuit (8), a transmitting end undervoltage protection circuit (13), a transmitting end over-temperature protection circuit (14), a transmitting end over-current protection circuit (15), a receiving end undervoltage protection circuit (16), a receiving end over-temperature protection circuit (17) and a receiving end over-current protection circuit (18);

the input receiving circuit (1), the data channel digital control circuit (2), the data channel modulation transmitting circuit (5), the data channel high common mode transient suppression differential signal receiving circuit (4), the transmitting end under-voltage protection circuit (13), the transmitting end over-temperature protection circuit (14), the transmitting end over-current protection circuit (15) and the transmitting end low-voltage generation circuit (3) form a driving circuit transmitting end circuit; the protection channel digital control circuit (10), the protection channel modulation transmitting circuit (9), the protection channel high common mode transient suppression differential signal receiving circuit (6), the output driving circuit (7), the receiving end under-voltage protection circuit (16), the receiving end over-temperature protection circuit (17), the receiving end over-current protection circuit (18) and the receiving end low-voltage generation circuit (8) form a driving circuit receiving end circuit; the ground potentials of all circuits in the sending end circuit of the driving circuit are connected to a sending end ground voltage Vgnd1, and the ground potentials of all circuits in the receiving end circuit of the driving circuit are connected to a receiving end ground voltage Vgnd 2; the first high-voltage isolation circuit (11) comprises a positive end sending capacitor Ctp, a negative end sending capacitor Ctn, a positive end receiving capacitor Crp and a negative end receiving capacitor Crn, and the second high-voltage isolation circuit (12) comprises a positive end sending capacitor Ctpp, a negative end sending capacitor Ctnp, a positive end receiving capacitor Crpp and a negative end receiving capacitor Crnp;

the input receiving circuit (1) receives external low-level logic input data DI and control signals Adj, converts the external low-level logic input data DI and the control signals Adjin into input data Din with high level VCC through processing, and is connected to the input end of the data channel digital control circuit (2); the data channel digital control circuit (2) converts Din into differential input data DxP and DxN according to the states of an undervoltage protection signal UVLO provided by a sending end undervoltage protection circuit (13), an over-temperature protection signal OTP provided by a sending end over-temperature protection circuit (14), an over-current protection signal OCP provided by a sending end over-current protection circuit (15), an Error signal Error output by a data channel high common mode transient suppression differential signal receiving circuit (4) and a control signal Adjin, and is connected to the input end of the data channel modulation sending circuit (5), and the data channel modulation sending circuit (5) outputs data channel differential sending data TxP and TxN; data channel differential sending data TxP and TxN are respectively connected to the left ends of a positive terminal sending capacitor Ctp and a negative terminal sending capacitor Ctn, the right ends of the positive terminal sending capacitor Ctp and the negative terminal sending capacitor Ctn are respectively connected to the left ends of a positive terminal receiving capacitor Crp and a negative terminal receiving capacitor Crn, and data channel differential receiving data RxP and RxN are respectively generated at the right ends of the positive terminal receiving capacitor Crp and the negative terminal receiving capacitor Crn; the data channel differential receiving data RxP and RxN are connected to the input end of the protection channel high common mode transient suppression differential signal receiving circuit (6), receiving output data Dout is obtained through processing, the receiving output data Dout is connected to the input end of the output driving circuit (7), and the output driving circuit (7) outputs an output driving signal DG with large driving current;

the protection channel digital control circuit (10) obtains differential protection data PxP and PxN according to the states of an undervoltage protection signal UVLO _ P provided by a receiving end undervoltage protection circuit (16), an over-temperature protection signal OTP _ P provided by a receiving end over-temperature protection circuit (17) and an over-current protection signal OCP _ P provided by a receiving end over-current protection circuit (18), and is connected to the input end of a protection channel modulation sending circuit (9); the protection channel modulation sending circuit (9) outputs protection channel differential sending data TxPP and TxNP which are respectively connected to the right ends of a positive end sending capacitor Ctpp and a negative end sending capacitor Ctnp; the left ends of the positive terminal sending capacitor Ctpp and the negative terminal sending capacitor Ctnp are respectively connected to the right ends of the positive terminal receiving capacitor Crpp and the negative terminal receiving capacitor Crnp, the left ends of the positive terminal receiving capacitor Crpp and the negative terminal receiving capacitor Crnp generate protection channel differential receiving data RxP and RxN which are connected to the input end of the data channel high common mode transient suppression differential signal receiving circuit (4), and the output Error signal Error of the data channel high common mode transient suppression differential signal receiving circuit (4) is connected to the input end of the data channel digital control circuit (2);

the sending end low-voltage generating circuit (3) and the receiving end low-voltage generating circuit (8) are realized by adopting the same low-voltage generating circuit; the sending end low voltage generating circuit (3) adopts sending end power supply voltage VCC to generate reference voltage and bias voltage required by each component circuit inside a low voltage power supply VCL and a driving circuit sending end circuit which are used for inputting the receiving circuit (1); the receiving end low voltage generating circuit (8) adopts a receiving end power supply voltage VDD to generate a reference voltage and a bias voltage which are used for driving each component circuit in the receiving end circuit of the circuit.

2. The gate drive circuit of the high-voltage insulation isolation SiC MOSFET with the protection function as claimed in claim 1, wherein the protection channel high common mode transient suppression differential signal receiving circuit (6) comprises: the device comprises a differential input receiving circuit (601), an X-level front-back cascade common mode adjustable amplifying circuit (602), a high-sensitivity common mode adjustable amplifying circuit (603), a first output shaping circuit (604) and a common mode self-adaptive adjusting circuit (605); the differential input receiving circuit (601) receives a positive terminal receiving signal RxP and a negative terminal receiving signal RxN of differential receiving data at first, and obtains a positive terminal input signal Vip and a negative terminal input signal Vin through filtering processing; the positive end input signal Vip and the negative end input signal Vin enter a first-stage common mode adjustable amplifying circuit in an X-stage common mode adjustable amplifying circuit (602) which is cascaded in front and at the back, and finally a positive end output signal VoXp and a negative end output signal VoXn of the X-stage common mode adjustable amplifying circuit are obtained; the positive end output signal VoXp and the negative end output signal VoXn are respectively connected with the positive input end and the negative input end of the high-sensitivity common mode adjustable amplifying circuit (603), and the high-sensitivity common mode adjustable amplifying circuit (603) outputs a group of differential output signals which comprise the positive end output signal VoXp and the negative end output signal VoXn; the first output shaping circuit (604) obtains final data output by processing according to the magnitude of the positive end output signal VoXp and the negative end output signal VoXn, namely receiving output data Dout; the common mode self-adaptive adjusting circuit (605) generates common mode adjusting signals C11, C12, C21, C22, …, CX1 and CX2 for each stage of amplifying circuit in a self-adaptive mode according to changes of power supply and ground voltage signals, and the common mode adjusting signals C11 and C12 generated by the common mode self-adaptive adjusting circuit (605) are respectively connected to a common mode adjusting signal input end of the first stage of common mode adjustable amplifying circuit; the common mode adjusting signals C21 and C22 are respectively connected to the common mode adjusting signal input end of the second-stage common mode adjustable amplifying circuit; by analogy, the common mode adjusting signals CX1 and CX2 are respectively connected to the common mode adjusting signal input end of the X-th order common mode adjustable amplifying circuit; the common mode adaptive adjusting circuit (605) also generates common mode adjusting signals CN1 and CN2 which are respectively connected to the common mode adjusting signal input end of the high-sensitivity common mode adjustable amplifying circuit (603); wherein X is a positive integer greater than 1, and N is a positive integer greater than X; the data channel high common mode transient suppression differential signal receiving circuit (4) and the protection channel high common mode transient suppression differential signal receiving circuit (6) are realized by adopting the same high common mode transient suppression differential signal receiving circuit, and data output by the data channel high common mode transient suppression differential signal receiving circuit (4) is used as an Error signal Error.

3. The gate drive circuit of the high voltage isolation SiC MOSFET with protection function as claimed in claim 2, wherein the differential input receiving circuit (601) comprises: a positive side isolation capacitor C51, a positive side grounding resistor R51, a positive side coupling capacitor C52, a positive side common mode resistor R53, a negative side isolation capacitor C53, a negative side grounding resistor R52, a negative side coupling capacitor C54, a negative side common mode resistor R54 and a receiving common mode generating circuit (6011); the left end of the positive side isolation capacitor C51 and the left end of the negative side isolation capacitor C53 are connected to the positive side receive signal RxP and the negative side receive signal RxN, respectively; the right end of the positive side isolation capacitor C51 is connected to the lower end of the positive side ground resistor R51 and the left end of the positive side coupling capacitor C52; the right end of the negative side isolation capacitor C53 is connected to the lower end of the negative side ground resistor R52 and the left end of the negative side coupling capacitor C54; the right end of the positive terminal coupling capacitor C52 is connected to the upper end of the positive terminal common mode resistor R53 and serves as the output terminal of the positive terminal input signal Vip; the right end of the negative end coupling capacitor C54 is connected to the lower end of the negative end common mode resistor R54 and serves as the output end of a negative end input signal Vin; the lower end of the positive end common mode resistor R53 is connected with the upper end of the negative end common mode resistor R54 and is simultaneously connected to a common mode output end Vicm of the receiving common mode generating circuit (6011); the receiving common mode generating circuit (6011) dynamically tracks and adjusts the size of a common mode output end Vicm according to the change of an input common mode Vcm, and the influence of an input common mode is reduced.

4. The gate driver circuit of high voltage isolation SiC MOSFET with protection function as claimed in claim 3, wherein said receiving common mode generating circuit (6011) comprises: NMOS transistor M60, NMOS transistor M61, PMOS transistor M62, NMOS transistor M63, PMOS transistor M64, PMOS transistor M65, NMOS transistor M66, NMOS transistor M67, PMOS transistor M68, NMOS transistor M69, PMOS transistor M610, NMOS transistor M611, PMOS transistor M612, NMOS transistor M613, NMOS transistor M614, PMOS transistor M615, resistor R61, and first Schmidt trigger (600);

the grid electrode of the NMOS tube M60 is connected to an input common mode voltage Vcm; the drain electrode of the NMOS tube M60 is connected to the drain electrode and the gate electrode of the PMOS tube M62 and the gate electrode of the NMOS tube M63; the grid electrode of the NMOS tube M61 is connected to an input common mode control signal Vctrl; the drain electrode of the NMOS tube M61 is connected with the drain electrode of the NMOS tube M63 and is connected to the input end of the first Schmitt trigger (600); the output end of the first Schmitt trigger (600) is simultaneously connected to the grid electrode of the PMOS tube M610, the grid electrode of the NMOS tube M611, the grid electrode of the PMOS tube M612 and the grid electrode of the NMOS tube M613; the drain electrode of the PMOS tube M610 is connected with the drain electrode of the NMOS tube M611 and is also connected to the grid electrode of the NMOS tube M614; the drain of the PMOS tube M612 is connected with the drain of the NMOS tube M613, and is also connected to the gate of the PMOS tube M615; the source electrode of the NMOS tube M614 is connected with the source electrode of the PMOS tube M615 and is also used as an output port of the common mode output end Vicm; the drain electrode of the NMOS tube M614 is connected to a high input common mode level Vcmh, and the drain electrode of the PMOS tube M615 is connected to a low input common mode level Vcml; the source of the NMOS transistor M613 is connected to the upper end of the resistor R61; the source electrode of the NMOS transistor M60, the source electrode of the NMOS transistor M61, the source electrode of the NMOS transistor M611 and the lower end of the resistor R61 are simultaneously connected to the ground voltage; the source of the PMOS transistor M62, the source of the NMOS transistor M63 and the source of the PMOS transistor M610 are simultaneously connected to a power supply voltage.

5. The gate driver circuit of high voltage isolation SiC MOSFET with protection function as claimed in claim 2, wherein the common mode adaptive adjustment circuit (605) comprises: the common mode detection circuit comprises a first common mode detection circuit (100), a common mode detection signal transmission circuit (101), an adjustment common mode signal generation circuit (102) and a common mode adjustment signal selection circuit (103); the first common mode detection circuit (100) is used for detecting power supply and substrate noise and changing the size of a common mode detection signal Vcm _ det when the noise is larger than a certain threshold, the common mode detection signal Vcm _ det is connected to a common mode detection signal transmission circuit (101), common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2, NN1 and NN2 are generated through the common mode detection signal transmission circuit (101) and output to a common mode adjustment signal selection circuit (103); the common mode adjusting signal selection circuit (103) generates and adjusts the magnitude of common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2, CN1 and CN2 according to the common mode selecting switch control signal and outputs the common mode adjusting signals; the adjusting common-mode signal generating circuit (102) is used for generating various common-mode bias signals required by the common-mode adjusting signal selecting circuit (103) and outputting the common-mode bias signals to the common-mode adjusting signal selecting circuit (103).

6. The gate driver circuit of a high voltage isolation SiC MOSFET with protection according to claim 5, characterized in that the first common mode detection circuit (100) comprises: a PMOS transistor M111, a PMOS transistor M112 and an NMOS transistor M113; the grid electrode and the drain electrode of the PMOS tube M111 are connected, and the grid electrode is connected with the drain electrode of the PMOS tube M112 and the grid electrode of the NMOS tube M113; the grid electrode of the PMOS tube M112 is connected with the drain electrode of the NMOS tube M113 and is used as an output node of a common mode detection signal Vcm _ det; the source of the PMOS transistor M111 and the source of the PMOS transistor M112 are connected with a power supply voltage, and the source of the NMOS transistor M113 is connected with a ground voltage.

7. The high-voltage insulation isolation SiC MOSFET gate driving circuit with the protection function as claimed in claim 1, wherein the sending end over-temperature protection circuit (14) and the receiving end over-temperature protection circuit (17) adopt the same over-temperature protection circuit, and comprise a clamping circuit (1401), a temperature detection circuit (1402), a wide voltage range comparator circuit (1403) and a first output shaping circuit (1404) which are connected in sequence, wherein the temperature detection circuit (1402) obtains a first temperature detection output signal Vin1 and a second temperature detection output signal Vin2 according to a bias voltage Vb provided by the clamping circuit (1401); the wide voltage range comparator circuit (1403) compares the first temperature detection output signal Vin1 and the second temperature detection output signal Vin2 to obtain a comparison output signal Vo 1; the first output shaping circuit (1404) processes the comparison output signal Vo1 to output a temperature protection signal OTLock, wherein the OTLock is a digital logic signal, the OTLock is connected to the input end of the clamping circuit (1401) and is used for controlling the magnitude of the bias voltage Vb, and the OTLock is also used as a control signal to be output to other circuit modules of the high-voltage insulation isolation SiC MOSFET gate driving circuit.

8. The high voltage isolated SiC MOSFET gate driver circuit with protection of claim 7, wherein the temperature sensing circuit (1402) comprises: a PMOS tube M21, a PMOS tube M22, a resistor R21, a triode Q1 and a triode Q2; the triode Q1 is connected with the base electrode of the triode Q2 and is connected with the bias voltage Vb output node of the clamping circuit (101); an emitter of the triode Q1 is connected to the gate and the drain of the PMOS transistor M21 and serves as an output node of the first temperature detection output signal Vin 1; an emitter of the triode Q2 is connected to the gate and the drain of the PMOS transistor M22 and serves as an output node of the second temperature detection output signal Vin 2; the source electrode of the PMOS tube M21 and the source electrode of the PMOS tube M22 are connected to a power supply voltage, the collector electrode of the triode Q2 is connected to the upper end of the resistor R21, the lower end of the resistor R21 and the collector electrode of the triode Q1 are connected to a ground voltage; the width-length ratio of the PMOS tube M21 to the length-width ratio of the PMOS tube M22 are equal, and the base area ratio of the triode Q1 to the base area ratio of the triode Q2 is 1: n and N are any natural number.

9. The high voltage isolation SiC MOSFET gate drive circuit with protection function of claim 7, wherein the wide voltage range comparator circuit (1403) comprises: a PMOS tube M31, a PMOS tube M33, a PMOS tube M35, a PMOS tube M36, a PMOS tube M37, a PMOS tube M39, an NMOS tube M32, an NMOS tube M34, an NMOS tube M38, an NMOS tube M310 and a second common mode detection circuit (1031); the grid electrode of the PMOS tube M31 is connected to the first temperature detection output signal Vin1, and the grid electrode of the PMOS tube M33 is connected to the second temperature detection output signal Vin 2; the drain electrode of the PMOS tube M31 is connected to the drain electrode and the gate electrode of the NMOS tube M32, the gate electrode of the NMOS tube M34 and the gate electrode of the NMOS tube M310; the drain electrode of the PMOS tube M33 is connected to the drain electrode of the NMOS tube M34 and the gate electrode of the PMOS tube M37; the drain electrode of the PMOS tube M37 is connected to the drain electrode and the grid electrode of the NMOS tube M38, and the source electrode of the PMOS tube M37 is connected to the grid electrode of the PMOS tube M39 and the drain electrode of the PMOS tube M36; the source electrode of the PMOS tube M36 is connected to the drain electrode of the PMOS tube M35, and the grid electrodes of the PMOS tube M36 and the PMOS tube M35 are both connected to the control signal output by the second common mode detection circuit (1031); the drain electrode of the PMOS tube M39 is connected with the drain electrode of the NMOS tube M310 and outputs a comparison output signal Vo 1; the sources of the PMOS transistor M31, the PMOS transistor M33, the PMOS transistor M35 and the PMOS transistor M39 are simultaneously connected to a power supply voltage; the sources of the NMOS transistor M32, the NMOS transistor M34, the NMOS transistor M38 and the NMOS transistor M310 are simultaneously connected to the ground voltage.

10. The gate driving circuit of high voltage isolation SiC MOSFET with protection function as claimed in claim 9, wherein said second common mode detection circuit (1031) automatically detects common mode noise generated by power supply voltage and substrate potential and changes the common mode control signal Vcm _ det when the common mode noise exceeds a certain threshold; when the common-mode noise does not exceed the threshold, the common-mode control signal Vcm _ det is at a high level, the PMOS tube M36 and the PMOS tube M35 are both in an off state, and the grid electrode of the PMOS tube M39 is controlled by the source electrode of the PMOS tube M37; when the common-mode noise exceeds the threshold value, the common-mode control signal Vcm _ det is at a low level, the PMOS transistor M36 and the PMOS transistor M35 are both in a conducting state, the PMOS transistor M39 enters a closing state, and the comparison output signal Vo1 is clamped to the low level, so that the common-mode noise is prevented from influencing the normal work of the comparator.