CN113078801B

CN113078801B - Ultrahigh-voltage insulated isolation IGBT half-bridge gate driving circuit

Info

Publication number: CN113078801B
Application number: CN202110347587.3A
Authority: CN
Inventors: 周德金; 马君健; 黄伟; 陈珍海
Original assignee: Wuxi Innosys Technology Co ltd; Wuxi Research Institute of Applied Technologies of Tsinghua University
Current assignee: Wuxi Innosys Technology Co ltd; Wuxi Research Institute of Applied Technologies of Tsinghua University
Priority date: 2021-03-31
Filing date: 2021-03-31
Publication date: 2022-04-05
Anticipated expiration: 2041-03-31
Also published as: CN113078801A

Abstract

The invention relates to an ultrahigh voltage insulated isolation IGBT half-bridge gate driving circuit required by gate driving of a high voltage IGBT device, which comprises an input receiving circuit, a dead time generating circuit, a low-side delay circuit, a low-side output driving circuit, a modulation transmitting circuit, 4 high-voltage capacitors, a high common-mode transient suppression differential signal receiving circuit, a high-side output driving circuit, a transmitting end low-voltage generating circuit and a receiving end low-voltage generating circuit. On one hand, the ultrahigh voltage insulation isolation SiC MOSFET gate drive circuit provided by the invention adopts a high voltage insulation isolation technology to realize ultrahigh voltage-resistant insulation capacitance; on the other hand, the magnitude of the ground potential common mode transient noise can be automatically detected, and the error generated by the common mode transient noise is dynamically compensated when the noise exceeds a threshold value. The invention can be widely applied to driving various high-voltage power devices.

Description

Ultrahigh-voltage insulated isolation IGBT half-bridge gate driving circuit

Technical Field

The invention relates to an ultrahigh voltage insulated isolation IGBT half-bridge gate driving circuit for a power electronic system, and belongs to the technical field of integrated circuits.

Background

In the 21 st century, under the traction of emerging industries such as smart grid, mobile communication and new energy automobile, power electronic application systems require further improvement of system efficiency, miniaturization and added functions, and particularly require trade-offs between circuit application size, quality, power and efficiency, such as server power management, battery charger and micro-inverter of solar electric field. The above applications require power electronics systems to be efficient in design>95% of the total power, and also has high power density (>500W/in³I.e. 30.5W/cm³) High specific power (10 kW/lb, 22kW/kg) and high total load point(s) ((>1000W). With semiconductor technology andwith the continuous development and improvement of the manufacturing process, the IGBT device gradually moves to the center of the stage of the power semiconductor, and becomes the mainstream power output device. As a composite power semiconductor, the IGBT integrates the advantages of GTR and MOSFET, and has the characteristics of high switching speed, high voltage resistance, large current bearing capacity, good thermal stability and the like. Especially in high power applications, IGBTs have been widely used in energy conversion and management. The new generation of power electronic application system has increasingly higher requirements on the driving technology of the power semiconductor device, and the most central factor of the new generation of power electronic application system is a high-voltage gate driving chip for controlling the functions of the power semiconductor device. The new generation of power electronic complete machine system puts forward higher requirements on the driving speed and the intellectualization of the high-voltage grid driving chip, thereby further improving the reliability of the complete machine and reducing the design complexity of the complete machine system.

The drive circuit of the IGBT plays a decisive role for reliable operation of the overall system. In a half-bridge or full-bridge topology, the function performed by the drive circuit is the interface between the main circuit and the control loop. The output signal of the control circuit is generally PWM pulse, which is not enough to drive power devices such as IGBT, and the drive circuit amplifies the PWM signal, so that the PWM signal has certain power processing capacity, and the control of the power switching device is realized. The final goal of gate drive circuit design is to operate the power switching device in a near ideal switching state, reduce its switching losses, and improve the efficiency and reliability of the overall system. Compared with the MOSFET gate driving circuit, the IGBT gate driving circuit has the following main characteristics: (1) higher isolation voltage, in order to adapt to the application of higher voltage, a driving chip with higher isolation voltage must be developed; (2) higher switching frequency, the application of power devices is developing towards high frequency, so the driving chip must be able to provide larger instantaneous driving current, and have higher switching frequency; (3) the driving power is larger, the capacity of the power device module is continuously increased, and the maximum output current of the driving chip is also increased, so that the larger driving power can be provided; (4) the driver has more complete functions, has complete protection functions of overcurrent, undervoltage, overvoltage, overtemperature and the like, can effectively control instant di/dt and dv/dt caused by the switching of the power device, and has stronger anti-jamming capability.

Among many gate driving chips, a half-bridge gate driving chip is one of the most commonly used chip architectures, and a typical half-bridge gate driving chip is composed of high-side and low-side driving circuits. The core function of the half-bridge gate drive IC in the whole machine system is to convert a low-power level signal (1mA/3-5V) output by a CPU controller into a high-voltage high-current signal (0.5-5A/5-20V) required by gate drive of a high-power device, and amplify output current and output voltage swing amplitude; since signal connections must also be made between the high-voltage and low-voltage circuits, an isolation area signal transmission module must be present in the chip, which is responsible for the signal transmission function between the two sides of the isolation area. Due to the wide difference of application scenarios of power semiconductor devices, the voltage difference of VH existing between the maximum values of the high/low voltage regions can span from 40V to 6500V. The size of VH directly determines the electrical isolation grade in the chip, and different grades of electrical isolation functional modules are realized in the chip, and the technology and cost quality grade of circuit devices required to be adopted are greatly different. The high-voltage electrical isolation technology for the gate drive IC mainly includes two major types, namely, monolithic integration isolation technology and physical insulation isolation technology. The isolation technology of the monolithic integration is mainly a PN junction isolation technology which is commonly used for realizing a monolithic integration gate drive IC product below 650V; the insulation isolation technology isolates the high-voltage and low-voltage signal processing circuit in a physical space, and the ultra-high voltage electrical isolation exceeding 6500V can be realized. The IGBT device has many application scenes larger than 1200V, so the insulation isolation technology is a high-voltage isolation technology more suitable for an IGBT half-bridge gate drive IC.

Disclosure of Invention

The invention aims to provide an ultrahigh-voltage insulated isolated IGBT half-bridge gate driving circuit aiming at the gate driving application requirement of an IGBT power device.

According to the technical scheme provided by the invention, the ultrahigh voltage insulated isolation IGBT half-bridge gate drive circuit comprises: the circuit comprises an input receiving circuit, a dead time generating circuit, a low-side delay circuit, a low-side output driving circuit, a modulation transmitting circuit, an isolation circuit consisting of 4 high-voltage capacitors, a high common-mode transient suppression differential signal receiving circuit, a high-side output driving circuit, a transmitting end low-voltage generating circuit and a receiving end low-voltage generating circuit; the isolation circuit comprises a positive end sending capacitor Ctp, a negative end sending capacitor Ctn, a positive end receiving capacitor Crp and a negative end receiving capacitor Crn;

the low-voltage digital input signals HI and LI firstly enter an input receiving circuit, signal level discrimination and logic level high-voltage conversion are carried out, medium-voltage signals H and L are obtained and are connected to a dead time generating circuit; the dead time generating circuit obtains high-side differential input data HIP and HIN according to the medium-voltage signal H, and obtains low-side differential input data LIP and LIN according to the medium-voltage signal L; high-side differential input data HIP and HIN are connected to a modulation transmitting circuit to obtain differential transmitting data TxP and TxN; the differential sending data TxP and TxN are respectively connected to the left end of a positive terminal sending capacitor Ctp and the left end of a negative terminal sending capacitor Ctn; the right end of the positive end sending capacitor Ctp and the right end of the negative end sending capacitor Ctn are respectively connected to the left end of the positive end receiving capacitor Crp and the left end of the negative end receiving capacitor Crn; the right end of the positive terminal receiving capacitor Crp and the right end of the negative terminal receiving capacitor Crn respectively generate differential receiving data RxP and RxN; the differential receiving data RxP and RxN are connected to a high common mode transient suppression differential signal receiving circuit and processed to obtain high-side receiving output data Douth; the high-side receiving output data Douth is finally connected to the input end of the high-side output driving circuit to generate an output driving signal HO with large driving current; the low-side differential input data LIP and LIN are connected to the low-side delay circuit to obtain low-side drive data Doutl, and output to the low-side output drive circuit, and a low-side output signal LO is obtained through drive amplification;

the high common mode transient suppression differential signal receiving circuit, the high side output driving circuit and the receiving end low voltage generating circuit form a receiving end circuit; the input receiving circuit, the dead time generating circuit, the sending end low-voltage generating circuit, the modulation sending circuit, the low-side delay circuit and the low-side output driving circuit form a sending end circuit; the high common-mode transient suppression differential signal receiving circuit, the high-side output driving circuit and the receiving end low-voltage generating circuit commonly use a floating ground SW, and the input receiving circuit, the dead time generating circuit, the transmitting end low-voltage generating circuit, the modulation transmitting circuit, the low-side delay circuit and the low-side output driving circuit commonly use a low-voltage ground GND; the low-side output driving circuit and the high-side output driving circuit are output driving circuits with the same circuit structure; the transmitting end low-voltage generating circuit and the receiving end low-voltage generating circuit are low-voltage generating circuits with the same structure; the transmitting terminal low-voltage generating circuit is connected with a transmitting terminal power supply voltage VCC, and generates various reference voltages and bias voltages required by a low-voltage power supply VCL for inputting the receiving circuit and each component circuit in the transmitting terminal circuit; the receiving end low voltage generating circuit is connected with a receiving end power supply voltage VDD and generates various reference voltages and bias voltages required by all the components in the receiving end circuit.

Specifically, the positive terminal sending capacitor Ctp, the negative terminal sending capacitor Ctn, the positive terminal receiving capacitor Crp, and the negative terminal receiving capacitor Crn are equal in size and are all ultrahigh voltage-resistant isolation capacitors.

Specifically, the high common-mode transient suppression differential signal receiving circuit includes: the device comprises a differential input receiving circuit, an X-level front-back cascade common mode adjustable amplifying circuit, a high-sensitivity common mode adjustable amplifying circuit, an output shaping circuit and a common mode self-adaptive adjusting circuit;

the differential input receiving circuit firstly receives a positive terminal receiving signal RxP and a negative terminal receiving signal RxN of differential receiving data, and obtains a positive terminal input signal Vip and a negative terminal input signal Vin through filtering processing; the positive end input signal Vip and the negative end input signal Vin enter a first-stage common mode adjustable amplifying circuit in X-stage common mode adjustable amplifying circuits which are cascaded in front and at the back, and finally a positive end output signal VoXp and a negative end output signal VoXn of the X-stage common mode adjustable amplifying circuit are obtained; the positive end output signal VoXp and the negative end output signal VoXn are respectively connected with the positive input end and the negative input end of the high-sensitivity common-mode adjustable amplifying circuit, and the high-sensitivity common-mode adjustable amplifying circuit outputs a group of differential output signals which comprise a positive end output signal VoNp and a negative end output signal VoNn; the output shaping circuit is used for processing to obtain final data output, namely high-side receiving output data Douth, according to the magnitude of the positive end output signal VoNp and the negative end output signal VoNn; the common mode self-adaptive adjusting circuit generates common mode adjusting signals C11, C12, C21, C22, …, CX1 and CX2 for each stage of amplifying circuit in a self-adaptive mode according to changes of power supply and ground voltage signals, and the common mode adjusting signals C11 and C12 generated by the common mode self-adaptive adjusting circuit are respectively connected to a common mode adjusting signal input end of the first stage of common mode adjustable amplifying circuit; the common mode adjusting signals C21 and C22 are respectively connected to the common mode adjusting signal input end of the second-stage common mode adjustable amplifying circuit; by analogy, the common mode adjusting signals CX1 and CX2 are respectively connected to the common mode adjusting signal input end of the X-th order common mode adjustable amplifying circuit; the common mode self-adaptive adjusting circuit also generates common mode adjusting signals CN1 and CN2 which are respectively connected to a common mode adjusting signal input end of the high-sensitivity common mode adjustable amplifying circuit; wherein X is a positive integer greater than 1, and N is a positive integer greater than X.

Specifically, the differential input receiving circuit includes: the common-mode receiver comprises a positive-end isolation capacitor C51, a positive-end grounding resistor R51, a positive-end coupling capacitor C52, a positive-end common-mode resistor R53, a negative-end isolation capacitor C53, a negative-end grounding resistor R52, a negative-end coupling capacitor C54, a negative-end common-mode resistor R54 and a receiving common-mode generating circuit; the left end of the positive side isolation capacitor C51 and the left end of the negative side isolation capacitor C53 are connected to the positive side receive signal RxP and the negative side receive signal RxN, respectively; the right end of the positive side isolation capacitor C51 is connected to the lower end of the positive side ground resistor R51 and the left end of the positive side coupling capacitor C52; the right end of the negative side isolation capacitor C53 is connected to the lower end of the negative side ground resistor R52 and the left end of the negative side coupling capacitor C54; the right end of the positive terminal coupling capacitor C52 is connected to the upper end of the positive terminal common mode resistor R53 and serves as the output terminal of the positive terminal input signal Vip; the right end of the negative end coupling capacitor C54 is connected to the lower end of the negative end common mode resistor R54 and serves as the output end of a negative end input signal Vin; the lower end of the positive end common mode resistor R53 is connected with the upper end of the negative end common mode resistor R54 and is simultaneously connected to a common mode output end Vicm of the receiving common mode generating circuit; the receiving common mode generating circuit dynamically tracks and adjusts the size of a common mode output end Vicm according to the change of an input common mode Vcm, and the influence of an input common mode is reduced.

Specifically, the receiving common mode generating circuit includes: an NMOS transistor M60, an NMOS transistor M61, a PMOS transistor M62, a PMOS transistor M63, a PMOS transistor M64, a PMOS transistor M65, an NMOS transistor M66, an NMOS transistor M67, a PMOS transistor M68, an NMOS transistor M69, a PMOS transistor M610, an NMOS transistor M611, a PMOS transistor M612, an NMOS transistor M613, an NMOS transistor M614, a PMOS transistor M615, a resistor R61 and a first Schmidt trigger;

the grid electrode of the NMOS tube M60 is connected to an input common mode voltage Vcm; the drain electrode of the NMOS tube M60 is connected to the drain electrode and the gate electrode of the PMOS tube M62 and the gate electrode of the PMOS tube M63; the grid electrode of the NMOS tube M61 is connected to an input common mode control signal Vctrl; the drain electrode of the NMOS tube M61 is connected with the drain electrode of the PMOS tube M63 and is connected to the input end of the first Schmitt trigger; the output end of the first Schmitt trigger is simultaneously connected to the grid electrode of the PMOS tube M610, the grid electrode of the NMOS tube M611, the grid electrode of the PMOS tube M612 and the grid electrode of the NMOS tube M613; the drain electrode of the PMOS tube M610 is connected with the drain electrode of the NMOS tube M611 and is also connected to the grid electrode of the NMOS tube M614; the drain of the PMOS tube M612 is connected with the drain of the NMOS tube M613, and is also connected to the gate of the PMOS tube M615; the source electrode of the NMOS tube M614 is connected with the source electrode of the PMOS tube M615 and is also used as an output port of the common mode output end Vicm; the drain electrode of the NMOS tube M614 is connected to a high input common mode level Vcmh, and the drain electrode of the PMOS tube M615 is connected to a low input common mode level Vcml; the source of the NMOS transistor M613 is connected to the upper end of the resistor R61; the source electrode of the NMOS tube M60, the source electrode of the NMOS tube M61, the source electrode of the NMOS tube M611 and the lower end of the resistor R61 are simultaneously connected to the floating ground SW; the source of the PMOS transistor M62, the source of the PMOS transistor M63 and the source of the PMOS transistor M610 are simultaneously connected to the receiving terminal power voltage VDD.

Specifically, the high-sensitivity common-mode adjustable amplifying circuit is a front-stage and a rear-stage fully differential amplifying circuit, and comprises a front-stage common-mode adjustable amplifying circuit and a rear-stage differential amplifying circuit which are connected with each other; the positive input end of the preceding common mode adjustable amplifying circuit is the positive input end of the high-sensitivity common mode adjustable amplifying circuit, and the negative input end of the preceding common mode adjustable amplifying circuit is the negative input end of the high-sensitivity common mode adjustable amplifying circuit; a positive output end VoNp of the differential amplifying circuit is a positive output end of the high-sensitivity common-mode adjustable amplifying circuit, and a negative output end VoNn of the differential amplifying circuit is a negative output end of the high-sensitivity common-mode adjustable amplifying circuit;

the left side of the front-stage common mode adjustable amplifying circuit comprises a PMOS tube M81 and an NMOS tube M83 which are connected in series through a drain electrode; the source electrode of the PMOS tube M81 is connected with a power supply VDD, a capacitor C81 is connected between the grid electrode and the source electrode of the PMOS tube M81, the grid electrode of the PMOS tube M81 is also connected to the upper end of a bias resistor R81, and the drain electrode of the PMOS tube M81 is also connected to the lower end of the bias resistor R82; the lower end of the bias resistor R81 is connected with the upper end of the bias resistor R82 and is also used as a first signal input end of the differential amplification circuit; the drain of the NMOS transistor M83 is connected with the drain of a PMOS transistor M81 and is also connected with the third signal input end of the differential amplifying circuit; the grid electrode of the NMOS tube M83 is connected with the positive input end of the preceding-stage common-mode adjustable amplification circuit and receives a positive-end output signal VoXp; the right side of the front-stage common mode adjustable amplifying circuit comprises a PMOS tube M82 and an NMOS tube M84 which are connected in series through a drain electrode; the source electrode of the PMOS tube M82 is connected with a power supply VDD, a capacitor C82 is connected between the grid electrode and the source electrode of the PMOS tube M82, the grid electrode of the PMOS tube M82 is also connected to the upper end of a bias resistor R83, and the drain electrode of the PMOS tube M82 is also connected to the lower end of the bias resistor R84; the lower end of the bias resistor R83 is connected with the upper end of the bias resistor R84 and is also used as a second signal input end of the differential amplifying circuit; the drain of the NMOS transistor M84 is connected with the drain of a PMOS transistor M82 and is also connected with the fourth signal input end of the differential amplifying circuit; the grid electrode of the NMOS tube M84 is connected with the negative input end of the preceding-stage common-mode adjustable amplifying circuit and receives a negative end output signal VoXn; the PMOS tube M81 and the PMOS tube M82 on the left side and the right side of the preceding stage common mode adjustable amplifying circuit are connected in parallel, and the NMOS tube M83 and the NMOS tube M84 are connected in parallel; the source electrodes of the NMOS transistor M83 and the NMOS transistor M84 are connected with the drain electrodes of the NMOS transistor M85, the NMOS transistor M86 and the NMOS transistor M87 which are grounded; the grid electrode of the ground NMOS tube M85 is connected with a bias voltage Vb1, and provides bias current required by normal operation of the amplifier; the gates of the NMOS transistor M86 and the NMOS transistor M87 are respectively connected to common mode adjusting signals CN1 and CN 2;

the differential amplifier circuit includes: PMOS transistor M88, PMOS transistor M89, PMOS transistor M812, PMOS transistor M813, PMOS transistor M810, NMOS transistor M811, PMOS transistor M814, NMOS transistor M815 and resistor R85; the grid of the PMOS tube M88 is a first signal input end of the differential amplification circuit, the grid of the PMOS tube M89 is a second signal input end of the differential amplification circuit, the grid of the PMOS tube M812 is a third signal input end of the differential amplification circuit, and the grid of the PMOS tube M813 is a fourth signal input end of the differential amplification circuit; the drain electrode of the PMOS tube M88 is connected with the drain electrode of the PMOS tube M89, is connected with the source electrode of the PMOS tube M810 and is used as the positive output end VoNp of the differential amplifying circuit; the drain electrode of the PMOS pipe M812 is connected with the drain electrode of the PMOS pipe M813 and is connected to the upper end of the resistor R85; the lower end of the resistor R85 is connected with the source electrode of the PMOS tube M814 and is used as the negative output end VoNn of the differential amplifying circuit; the PMOS transistor M810 and the NMOS transistor M811 form a cascode current source structure, the PMOS transistor M814 and the NMOS transistor M815 form a cascode current source structure, the gates of the PMOS transistor M810 and the PMOS transistor M814 are connected with the same bias voltage Vb81, and the gates of the NMOS transistor M811 and the NMOS transistor M815 are connected with the same bias voltage Vb 82.

Specifically, the output shaping circuit comprises a three-level comparator, a buffer with an RC filtering function, a second schmitt trigger and an output inverter which are connected in sequence, wherein an output end of the output inverter is final output data, namely high-side received output data Douth; the connection relationship of the internal circuit of the buffer with the RC filtering function is as follows: the grid of the PMOS tube M41 and the grid of the NMOS tube M42 are simultaneously connected to the comparison output voltage of the three-stage comparator, the drain of the PMOS tube M41 and the drain of the NMOS tube M42 are simultaneously connected to the grid of the PMOS tube M43 and the grid of the NMOS tube M44, the drain of the PMOS tube M43 is connected to the upper end of a resistor R41, the lower end of the resistor R41 is connected to the upper end of a resistor R42, the upper end of a capacitor C41 and the input end of a second Schmidt trigger, the lower end of the resistor R42 is connected to the drain of the NMOS tube M44, the source of the PMOS tube M41 and the source of the PMOS tube M43 are simultaneously connected to the ground voltage VCC, and the source of the NMOS tube M42, the source of the NMOS tube M44 and the lower end of the capacitor C41 are simultaneously connected to GND.

Specifically, the common-mode adaptive adjustment circuit includes: the common mode detection circuit, the common mode detection signal transmission circuit, the common mode adjustment signal generation circuit and the common mode adjustment signal selection circuit; the common mode detection circuit is used for detecting power supply and substrate noise, and changing the size of a common mode detection signal Vcm _ det when the noise is larger than a certain threshold value, the common mode detection signal Vcm _ det is connected to the common mode detection signal transmission circuit, common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2, NN1 and NN2 are generated through the common mode detection signal transmission circuit and output to the common mode adjustment signal selection circuit; the common mode adjusting signal selection circuit generates and adjusts the size of common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2 and CN1, CN2 according to the common mode selecting switch control signal and outputs the common mode adjusting signals; the adjusting common-mode signal generating circuit is used for generating various common-mode bias signals required by the common-mode adjusting signal selecting circuit and outputting the common-mode bias signals to the common-mode adjusting signal selecting circuit.

Specifically, the common mode detection circuit includes: a PMOS transistor M111, a PMOS transistor M112 and an NMOS transistor M113; the grid electrode and the drain electrode of the PMOS tube M111 are connected, and the grid electrode is connected with the drain electrode of the PMOS tube M112 and the grid electrode of the NMOS tube M113; the grid electrode of the PMOS tube M112 is connected with the drain electrode of the NMOS tube M113 and is used as an output node of a common mode detection signal Vcm _ det; the sources of the PMOS transistors M111 and M112 are connected to the power supply voltage VDD, and the source of the NMOS transistor M113 is connected to the floating ground SW.

The invention has the advantages that: on one hand, by adopting an insulation isolation technology, ultrahigh voltage resistance physical isolation can be realized, and the ultrahigh voltage resistance physical isolation has high-speed transmission characteristics; on the other hand, the common CMOS process is adopted to realize the ultra-high voltage-resistant capacitor, so that the insulation voltage-resistant grade between the signal sending end and the receiving end can be improved to the greatest extent; in addition, the common-mode transient suppression technology is adopted, the magnitude of ground potential common-mode transient noise can be automatically detected, and the error generated by the common-mode transient noise is dynamically compensated when the noise exceeds a threshold value. The invention can be widely applied to driving various high-voltage power devices.

Drawings

Fig. 1 is a structural diagram of an ultra-high voltage insulated isolated IGBT half-bridge gate driving circuit according to the present invention.

FIG. 2 is a block diagram of an input receiving circuit according to the present invention.

Fig. 3 is a diagram showing a dead time generation circuit according to the present invention.

Fig. 4 is a diagram of a low-side delay circuit according to the present invention.

Fig. 5 is a structural diagram of a modulation transmission circuit of the present invention.

Fig. 6 is a structural diagram of a high common mode transient suppression differential signal receiving circuit according to the present invention.

Fig. 7 is a diagram of an embodiment of a differential input receiving circuit according to the invention.

Fig. 8 is a diagram of an embodiment of a receiving common mode generating circuit according to the present invention.

Fig. 9 is a diagram illustrating an embodiment of a common mode adjustable amplifier circuit according to the invention.

Fig. 10 is a diagram illustrating an embodiment of a high-sensitivity common-mode tunable amplifier circuit according to the present invention.

Fig. 11 shows an embodiment of the output shaping circuit of the present invention.

Fig. 12 is a diagram of an embodiment of a common mode adaptive adjustment circuit according to the invention.

FIG. 13 is a diagram of a common mode detection circuit according to an embodiment of the present invention.

Fig. 14 is a waveform of the circuit shown in fig. 13.

FIG. 15 is a cross-sectional view of a semiconductor structure of an embodiment of a high voltage isolation capacitor of the present invention.

Fig. 16 shows an embodiment of the low voltage generating circuit of the present invention.

FIG. 17 shows an embodiment of an output driving circuit according to the present invention.

Detailed Description

The present invention is described in further detail below with reference to the attached drawings and examples.

As shown in fig. 1, the ultra-high voltage insulated isolated IGBT half-bridge gate driving circuit according to the present invention includes an input receiving circuit 1, a dead time generating circuit 2, a low-side delay circuit 3, a low-side output driving circuit 4, a modulation transmitting circuit 5, an isolation circuit 10 composed of 4 high-voltage capacitors, a high common mode transient suppression differential signal receiving circuit 6, a high-side output driving circuit 7, a transmitting end low-voltage generating circuit 8, and a receiving end low-voltage generating circuit 9. The isolation circuit 10 includes a positive terminal sending capacitor Ctp, a negative terminal sending capacitor Ctn, a positive terminal receiving capacitor Crp, and a negative terminal receiving capacitor Crn. The 4 capacitors are equal in size and are all ultrahigh voltage-resistant isolation capacitors.

The low-voltage digital input signals HI and LI firstly enter an input receiving circuit 1, signal level discrimination and logic level high-voltage conversion are carried out, medium-voltage signals H and L are obtained and are connected to a dead time generating circuit 2; the dead time generation circuit 2 obtains high-side differential input data HIP and HIN according to the medium-voltage signal H, and obtains low-side differential input data LIP and LIN according to the medium-voltage signal L; high-side differential input data HIP and HIN enter a modulation transmitting circuit 5 to obtain differential transmitting data TxP and TxN; the differential sending data TxP and TxN are respectively connected to the left ends of the positive terminal sending capacitor Ctp and the negative terminal sending capacitor Ctn; the right ends of the positive terminal sending capacitor Ctp and the negative terminal sending capacitor Ctn are respectively connected to the left ends of the positive terminal receiving capacitor Crp and the negative terminal receiving capacitor Crn; the right ends of the positive terminal receiving capacitor Crp and the negative terminal receiving capacitor Crn respectively generate differential receiving data RxP and RxN; the differential receiving data RxP and RxN enter a high common mode transient suppression differential signal receiving circuit 6, and high side receiving output data Douth is obtained after processing; the high-side receives the output data Douth and finally enters a high-side output driving circuit 7 to generate an output driving signal HO with large driving current; the low-side differential input data LIP and LIN enter the low-side delay circuit 3 to obtain low-side drive data Doutl, and are output to the low-side output drive circuit 4, and a low-side output signal LO with large drive capability is obtained through drive amplification.

The high common mode transient suppression differential signal receiving circuit 6, the high side output driving circuit 7 and the receiving end low voltage generating circuit 9 form a receiving end circuit. The ground terminals of the receiving side circuits commonly use a floating ground SW.

The input receiving circuit 1, the dead time generating circuit 2, the transmitting end low voltage generating circuit 8, the modulation transmitting circuit 5, the low-side delay circuit 3 and the low-side output driving circuit 4 form a transmitting end circuit. The ground terminals of the transmitting-side circuits commonly use the low-voltage ground GND.

The low-side output driver circuit 4 and the high-side output driver circuit 7 are output driver circuits having the same circuit structure.

The sending end low voltage generating circuit 8 and the receiving end low voltage generating circuit 9 are realized by the same low voltage generating circuit. The sending end low voltage generating circuit 8 adopts sending end power supply voltage VCC to generate various reference voltages and bias voltages required by the low voltage power supply VCL input to the receiving circuit 1 and each component circuit in the sending end circuit; the receiving-end low-voltage generating circuit 9 generates various reference voltages and bias voltages required by each component circuit inside the receiving-end circuit by using the receiving-end power supply voltage VDD.

A basic input receiving circuit 1 of a gate driving chip that can be used with the circuit structure of the present invention is shown in fig. 2, and includes two identical input channels, each of which includes an input ESD protection circuit, a level discrimination circuit, and a medium voltage level shift circuit, which are connected in sequence. The input receiving circuit 1 not only needs to complete the transmission of signals, but also needs to complete the ESD protection of the internal circuit of the chip, so as to prevent the circuit from being damaged due to the impact of ESD to the internal circuit. Circuits commonly used for ESD protection in integrated circuit designs are: lateral SCR clamps, reverse parallel diode clamps, zener clamps, CDM clamps, and the like. The level decision circuit is used for identifying whether an external input level is logic "0" or "1", and the level decision circuit must have enough interference noise tolerance due to the existence of large interference of an external signal, and a specific circuit implementation usually includes 2 types, one type is a Schmitt trigger, and the other type is a hysteresis comparator. The implementation circuits of the schmitt trigger and the hysteresis comparator are greatly different according to the different speeds of the driving object and the input logic signal of the driving chip. Since the power supply voltage VCC of the gate driving chip is usually a medium voltage level of 10-20V, and the input logic level is an external digital logic lower than 5V, in order to more accurately complete the judgment of the input logic level, the input ESD and level judgment circuit must use a relatively lower power supply voltage VCL, usually a voltage of 3-10V. Therefore, before the logic signal output by the level discrimination circuit enters the chip internal control logic, the logic signal with the high level of VCL must be converted into the logic signal with the high level of VCC through a medium-voltage level shift circuit, so as to obtain H and L signals.

Due to the existence of a large grid parasitic capacitance, when the power device is switched on or switched off, a certain time is required for charging and discharging the capacitance, and direct connection between two power devices of driven upper and lower bridge arms must be prevented. The dead time is a control means for ensuring the reliable operation of the high-side and low-side power devices, and is aimed at avoiding the simultaneous conduction, i.e. the shoot-through phenomenon, of the high-side and low-side devices to prevent the devices from being destroyed under the condition, and the dead time is to ensure that one device is turned on after being completely turned off. The dead time generating circuit 2 adds the input square wave to the dead time as the driving signal of the high-low side grid. A block diagram of the basic structure of the dead time generation circuit 2 of the present invention is shown in fig. 3. The dead zone generating mode of the circuit is to adopt a delay circuit to enable two paths of input signals to generate phase difference, and then carry out logic operation on the input signals to obtain dead zone time. The magnitude of the dead time is determined by the delay time generated by the delay circuit, and thus the delay circuit is the core of the dead time circuit. The simplest structure of the delay circuit is an inverter + RC network, but the accuracy of the method is not enough, and the method can only meet the requirements of medium-low speed application occasions. The implementation of the more accurate delay circuit can be through a capacitive structure, a current source structure and a resistive structure, which is not the focus of the present invention and is not described in detail herein.

After the high-side differential input data HIP and HIN pass through the modulation transmitting circuit 5, the 4 high-voltage capacitors and the high common-mode transient suppression differential signal receiving circuit 6, a certain delay is generated compared with a low-side signal. For medium and high frequency applications, this time already causes phase mismatch of the high and low end signals, which may affect the normal operation of the system. Therefore, a delay matching circuit must be added to the low-side signal path to match the phases of the high-side and low-side signals. The structure of the low-side delay circuit 3 according to the present invention is shown in fig. 4. Structurally, the delay circuit is firstly subjected to signal conversion by the RS trigger, then a cross coupling circuit is adopted, so that the rising edge and the falling edge of the signal are steeper, and the delay of the signal is realized through the RC network. The delay circuit in fig. 3 may also adopt the same circuit structure as that in fig. 4, and may be implemented by adjusting the delay resistance and capacitance according to different delay time requirements.

The modulation scheme adopted by the circuit shown in fig. 5 is pulse counting modulation, and the rising edge and the falling edge of the input signal are separated by using a method of describing the rising edge of the input signal by double pulses and describing the falling edge of the input signal by single pulses, so as to generate corresponding pulse driving signals. The modulation transmission circuit 5 of the present invention employs 2 sets of transmission circuits shown in fig. 5, HIP being input data, R1 and R2 being high frequency refresh signals, and output being modulated pulse signal TxP. The refresh signals R1 and R2 correspond to the refresh command signals of a falling edge single pulse and a rising edge double pulse, respectively, and the circuit operates normally when the signal is high, and performs a refresh operation to refresh the circuit when the signal is low. Besides the logic gate, the DELAY module for time DELAY is also arranged in the circuit, and is composed of an inverter, a capacitor and a Schmitt trigger, and the DELAY module can be realized by adopting the circuit structure shown in FIG. 4. The specific length of the delay is controllable, and the delay time can be controlled by changing the size of the capacitor or the number of the inverters. And the Schmitt trigger is connected behind the capacitor so as to avoid the uncertain influence caused by unstable voltage at two ends of the capacitor.

Since a large voltage difference exists in the substrate potential between the transmitting-side circuit and the receiving-side circuit, electrical isolation must be performed between the high-voltage and low-voltage circuits. Due to the wide variation of the application scenarios of power semiconductor devices, the voltage difference VGND ═ between the maximum values of the high and low voltage regions (VGND-Vsw) can span from 40V to 6500V. The invention adopts the insulation isolation technology of capacitance isolation to isolate the high-low voltage signal processing circuit in physical space, thus realizing ultra-high voltage electrical isolation of more than 3000V. In the solution presented in fig. 1, the transmitting-side circuit and the receiving-side circuit are connected to GND and SW, respectively, wherein an isolation circuit 10 is provided to isolate the two ground voltages Vgnd and Vsw. However, since there is usually a certain level of common mode transient noise between the two ground voltages Vgnd and Vsw, the signal will generate errors during transmission. The common mode transient noise VGND is usually defined as a voltage difference equal to (VGND-Vsw), and for a typical application scenario of a 1200V IGBT, the common mode transient noise VGND will periodically rise rapidly from 0V to 1200V, and then fall rapidly from 1200V to 0V. Under the interference of the common mode transient noise VGND, the voltage Vcm (Vcm ═ RxP + RxN)/2) will produce a spike error, inevitably causing data error of the receiving circuit, and the common mode transient noise effect will be further worsened as the switching frequency increases. Therefore, in order to realize the high-reliability driving of the high-voltage IGBT device and effectively suppress the common-mode transient noise, the high-common-mode transient suppression differential signal receiving circuit 6 is adopted in the invention.

Fig. 6 is a block diagram of the high common mode transient suppression differential signal receiving circuit 6 according to the present invention. The circuit includes: the circuit comprises a differential input receiving circuit 601, an X-stage tandem common mode adjustable amplifying circuit 602(CM 1-CMX), a high-sensitivity common mode adjustable amplifying circuit 603(CMN), an output shaping circuit 604 and a common mode adaptive adjusting circuit 605. The differential input receiving circuit 601 first receives the differential signals (positive terminal receiving signal RxP and negative terminal receiving signal RxN) coupled from the transmitting terminal circuit shown in fig. 2 through the isolation circuit 10, and obtains a positive terminal input signal Vip and a negative terminal input signal Vin through filtering processing; vip and Vin enter a first-pole common-mode adjustable amplifying circuit CM1 of an X-stage common-mode adjustable amplifying circuit 602 cascaded in front and behind, and finally a positive-end output signal VoXp and a negative-end output signal VoXn of the X-stage common-mode adjustable amplifying circuit are obtained; VoXp and VoXn are respectively connected to the positive input terminal and the negative input terminal of the high-sensitivity common-mode adjustable amplifier circuit 603(CMN), so as to obtain differential output signals (a positive-side output signal VoNp and a negative-side output signal VoNn) of the high-sensitivity common-mode adjustable amplifier circuit 603; the output shaping circuit 604 obtains the final data output Douth through processing according to the sizes of the von p and the von. The common mode adaptive adjusting circuit 605 adaptively generates common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2, CN1 and CN2 for each stage of amplifying circuit according to the change of power supply and ground voltage signals, and common mode adjusting signals C11 and C12 generated by the common mode adaptive adjusting circuit 605 are respectively connected to a common mode adjusting signal input end of the first stage of common mode adjustable amplifying circuit CM 1; the common mode adjusting signal C21 and the common mode adjusting signal C22 are respectively connected to a common mode adjusting signal input end of the second-stage common mode adjustable amplifying circuit CM 2; … … and so on, the common mode adjusting signal CX1 and the common mode adjusting signal CX2 are respectively connected to the common mode adjusting signal input terminal of the X-th common mode adjustable amplifying circuit CMX; the common mode adjustment signal CN1 and the common mode adjustment signal CN2 are respectively connected to the common mode adjustment signal input terminal of the high-sensitivity common mode adjustable amplification circuit 603 (CMN). Wherein X is a positive integer greater than 1, and N is a positive integer greater than X.

In fig. 6, the internal of the common mode adaptive adjusting circuit 605 automatically detects the magnitude of the transient common mode noise caused by the fluctuation of the power supply voltage VDD and the ground voltage Vsw of the receiving circuit, and when the transient common mode noise exceeds a certain threshold, adjusts the values of the common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2, CN1, and CN2 and correspondingly outputs the values to the common mode adjustable amplifying circuits CM1 to CMX and the high-sensitivity common mode adjustable amplifying circuit 603(CMN) cascaded in the X-stage front-back stage, so as to adjust the common mode levels of the common mode adjustable amplifying circuits CM1 to CMX and the high-sensitivity common mode adjustable amplifying circuit 603 cascaded in the X-stage front-back stage, and compensate the influence of the transient common mode noise. Besides the common mode adaptive adjustment, the invention also adopts a high-reliability output shaping circuit 604, and adopts RC low-pass filtering and Schmitt trigger combined filtering to filter the influence of high-frequency noise, and finally obtains the data output Douth which is not influenced by transient common mode noise.

Fig. 7 shows an implementation of the differential input receiving circuit 601 of the present invention, which is composed of a positive side isolation capacitor C51, a positive side ground resistor R51, a positive side coupling capacitor C52, a positive side common mode resistor R53, a negative side isolation capacitor C53, a negative side ground resistor R52, a negative side coupling capacitor C54, a negative side common mode resistor R54, and a receiving common mode generating circuit 6011. The left end of the positive side isolation capacitor C51 and the left end of the negative side isolation capacitor C53 are connected to the positive side receive signal RxP and the negative side receive signal RxN, respectively; the right end of the positive side isolation capacitor C51 is connected to the lower end of the positive side ground resistor R51 and the left end of the positive side coupling capacitor C52; the right end of the negative side isolation capacitor C53 is connected to the lower end of the negative side ground resistor R52 and the left end of the negative side coupling capacitor C54; the right end of the positive terminal coupling capacitor C52 is connected to the upper end of the positive terminal common mode resistor R53 and serves as the output terminal of the positive terminal input signal Vip; the right end of the negative end coupling capacitor C54 is connected to the lower end of the negative end common mode resistor R54 and serves as the output end of a negative end input signal Vin; the lower end of the positive common-mode resistor R53 is connected to the upper end of the negative common-mode resistor R54, and is also connected to the common-mode output terminal Vicm of the receiving common-mode generating circuit 6011.

In the circuit of FIG. 7, the positive side isolation capacitor C51 and the negative side isolation capacitor C53 are both high-voltage capacitors, and the size of the capacitors is usually dozens of fp; the positive side coupling capacitor C52 and the negative side coupling capacitor C54 are low voltage capacitors, and the capacitance values thereof are relatively small. The positive side receiving signal RxP and the negative side receiving signal RxN are input to output, and are filtered by 2 stages of DC blocking coupling to obtain a positive side input signal Vip and a negative side input signal Vin. The common mode levels of Vip and Vin are provided by receive common mode generating circuit 6011.

Fig. 8 is an implementation of the receiving common mode generating circuit 6011 according to the present invention. The circuit is composed of an NMOS tube M60, an NMOS tube M61, a PMOS tube M62, a PMOS tube M63, a PMOS tube M64, a PMOS tube M65, an NMOS tube M66, an NMOS tube M67, a PMOS tube M68, an NMOS tube M69, a PMOS tube M610, an NMOS tube M611, a PMOS tube M612, an NMOS tube M613, an NMOS tube M614, a PMOS tube M615 and a resistor R61; the schmitt trigger 600 is composed of a PMOS transistor M64, a PMOS transistor M65, an NMOS transistor M66, an NMOS transistor M67, a PMOS transistor M68 and an NMOS transistor M69.

The grid electrode of the NMOS tube M60 is connected to an input common mode voltage Vcm; the drain electrode of the NMOS tube M60 is connected to the drain electrode and the gate electrode of the PMOS tube M62 and the gate electrode of the PMOS tube M63; the grid electrode of the NMOS tube M61 is connected to an input common mode control signal Vctrl; the drain electrode of the NMOS tube M61 is connected with the drain electrode of the PMOS tube M63 and is connected to the input end of the Schmitt trigger 600; the output end of the Schmitt trigger 600 is simultaneously connected to the gates of a PMOS transistor M610, an NMOS transistor M611, a PMOS transistor M612 and an NMOS transistor M613; the drain electrode of the PMOS tube M610 is connected with the drain electrode of the NMOS tube M611 and is also connected to the grid electrode of the NMOS tube M614; the drain of the PMOS tube M612 is connected with the drain of the NMOS tube M613, and is also connected to the gate of the PMOS tube M615; the source electrode of the NMOS tube M614 is connected with the source electrode of the PMOS tube M615 and is also used as an output port of the common mode output end Vicm; the drain electrode of the NMOS tube M614 is connected to a high input common mode level Vcmh, and the drain electrode of the PMOS tube M615 is connected to a low input common mode level Vcml; the source of the NMOS transistor M613 is connected to the upper end of the resistor R61; the source electrode of the NMOS tube M60, the source electrode of the NMOS tube M61, the source electrode of the NMOS tube M611 and the lower end of the resistor R61 are connected to the floating ground SW; the source electrode of the PMOS transistor M62, the source electrode of the PMOS transistor M63, the source electrode of the PMOS transistor M64 and the source electrode of the PMOS transistor M610 are simultaneously connected to the receiving end power supply voltage VDD. The ground terminals of this circuit are all connected to a floating ground SW.

The function of the circuit shown in fig. 8 is to dynamically track and adjust the size of the common-mode output end Vicm according to the change of the input common-mode Vcm, so as to reduce the influence of the input common-mode. If the input common mode Vcm is reduced, the input end of the schmitt trigger 600 will be synchronously reduced, and if the fluctuation exceeds the threshold of the schmitt trigger 600, the output of the schmitt trigger 600 will become high level, the PMOS transistor M615 will be turned on, and the common mode output end Vicm will output low input common mode level Vcml to match with the input common mode; assuming that the input common mode Vcm increases and exceeds the threshold of the schmitt trigger 600, the NMOS transistor M614 is turned on, and the common mode output terminal Vicm outputs a high input common mode level Vcmh; it can be seen that the circuit of fig. 8 can achieve dynamic compensation of input common mode variations for different input common mode fluctuations. In the circuit shown in fig. 8, in order to better realize the output of the common-mode signal at the common-mode output end Vicm, an NMOS transistor is used for transmitting a high input common-mode level Vcmh, and a PMOS transistor is used for transmitting a low input common-mode level Vcml.

Fig. 9 shows an implementation of a cascade unit of the common mode adjustable amplifier circuit according to the present invention. The circuit is a fully differential single-stage amplifying circuit, and the left side of the circuit comprises a PMOS tube M71 and an NMOS tube M73 which are connected in series through a drain electrode; the source electrode of the PMOS tube M71 is connected with a power supply VDD, a capacitor C71 is connected between the grid electrode and the source electrode of the PMOS tube M71, and a bias resistor R71 is connected between the grid electrode and the drain electrode of the PMOS tube; the drain output negative terminal output signal Vo1n of the NMOS transistor M73 is connected to the negative input terminal of the next cascade unit (the second cascade unit outputs the negative terminal output signal Vo2n to the next cascade unit, and so on), and the gate of the NMOS transistor M73 is connected to the positive input terminal Vip of the common mode adjustable amplifier circuit 602; the right side of the circuit comprises: a PMOS transistor M72 and an NMOS transistor M74 which are connected in series through drains; the source electrode of the PMOS tube M72 is connected with a power supply VDD, a capacitor C72 is connected between the grid electrode and the source electrode of the PMOS tube M72, and a bias resistor R72 is connected between the grid electrode and the drain electrode of the PMOS tube M72; the drain of the NMOS transistor M74 outputs a positive end output signal Vo1p to the positive input terminal of the next cascade unit (the second cascade unit outputs a positive end output signal Vo2p to the next cascade unit, and so on), and the gate of the NMOS transistor M74 is connected to the negative input terminal Vin of the common mode adjustable amplifier circuit 602; the sources of the PMOS tube M71 and the PMOS tube M72 at the two sides of the amplifying circuit are connected in parallel, and the sources of the NMOS tube M73 and the NMOS tube M74 are connected in parallel; the source electrodes of the NMOS transistor M73 and the NMOS transistor M74 are connected with the drain electrodes of the NMOS transistor M75, the NMOS transistor M76 and the NMOS transistor M77 which are grounded; the grid electrode of the ground NMOS tube M75 is connected with a bias voltage Vb1, and provides bias current required by normal operation of the amplifier; the gates of the NMOS transistor M76 and the NMOS transistor M77 are connected to common mode adjustment signals C11 and C12, respectively.

As can be seen from the circuit shown in fig. 9, by changing the magnitudes of the common mode adjustment signals C11 and C12, the bias currents flowing through the NMOS transistor M73 and the NMOS transistor M74 change, and the output voltages of the negative side output signal Vo1n and the positive side output signal Vo1p of the cascade unit change correspondingly and simultaneously, so as to adjust the output common mode voltage. The receiving end circuit of the invention adopts a plurality of stages of common mode adjustable amplifying circuits which are the same as those shown in figure 9 and are cascaded in front and back, and an X-th stage common mode adjustable amplifying circuit CMX outputs a positive end output signal VoXp and a negative end output signal VoXn, thereby finally realizing the dynamic compensation of common mode noise.

Fig. 10 shows an implementation of the high-sensitivity common-mode tunable amplifier circuit 603 according to the present invention. The circuit is a front-stage and a rear-stage fully differential amplifying circuits, the front-stage common mode adjustable amplifying circuit adopts an amplifying circuit structure similar to that of fig. 9, and the rear-stage amplifying circuit is a differential amplifying circuit (DDA). The positive input end of the preceding common mode adjustable amplifier circuit is the positive input end of the high-sensitivity common mode adjustable amplifier circuit 603, and the negative input end of the preceding common mode adjustable amplifier circuit is the negative input end of the high-sensitivity common mode adjustable amplifier circuit 603; the positive output terminal VoNp of the differential amplifier circuit is the positive output terminal of the high-sensitivity common mode adjustable amplifier circuit 603, and the negative output terminal VoNn of the differential amplifier circuit is the negative output terminal of the high-sensitivity common mode adjustable amplifier circuit 603.

The left side of the front-stage common mode adjustable amplifying circuit comprises a PMOS tube M81 and an NMOS tube M83 which are connected in series through a drain electrode; the source electrode of the PMOS tube M81 is connected with a power supply VDD, a capacitor C81 is connected between the grid electrode and the source electrode of the PMOS tube M81, the grid electrode of the PMOS tube M81 is also connected to the upper end of a bias resistor R81, and the drain electrode of the PMOS tube M81 is also connected to the lower end of the bias resistor R82; the lower end of the bias resistor R81 is connected with the upper end of the bias resistor R82 and is also used as a first signal input end of the differential amplification circuit; the drain of the NMOS transistor M83 is connected with the drain of a PMOS transistor M81 and is also connected with the third signal input end of the differential amplifying circuit; the grid electrode of the NMOS tube M83 is connected with the positive input end VoXp of the preceding-stage common-mode adjustable amplifying circuit; the right side of the circuit comprises a PMOS tube M82 and an NMOS tube M84 which are connected in series through a drain electrode; the source electrode of the PMOS tube M82 is connected with a power supply VDD, a capacitor C82 is connected between the grid electrode and the source electrode of the PMOS tube M82, the grid electrode of the PMOS tube M82 is also connected to the upper end of a bias resistor R83, and the drain electrode of the PMOS tube M82 is also connected to the lower end of the bias resistor R84; the lower end of the bias resistor R83 is connected with the upper end of the bias resistor R84 and is also used as a second signal input end of the differential amplifying circuit; the drain of the NMOS transistor M84 is connected with the drain of a PMOS transistor M82 and is also connected with the fourth signal input end of the differential amplifying circuit; the grid electrode of the NMOS tube M84 is connected with the negative input end VoXn of the preceding-stage common-mode adjustable amplifying circuit; the sources of the PMOS tube M81 and the PMOS tube M82 at the two sides of the amplifying circuit are connected in parallel, and the sources of the NMOS tube M83 and the NMOS tube M84 are connected in parallel; the source electrodes of the NMOS transistor M83 and the NMOS transistor M84 are connected with the drain electrodes of the NMOS transistor M85, the NMOS transistor M86 and the NMOS transistor M87 which are grounded; the grid electrode of the ground NMOS tube M85 is connected with a bias voltage Vb1, and provides bias current required by normal operation of the amplifier; the gates of the NMOS transistor M86 and the NMOS transistor M87 are connected to common mode adjustment signals CN1 and CN2, respectively.

Fig. 11 shows an implementation manner of the output shaping circuit 604 of the present invention, which includes a PMOS transistor M401, a PMOS transistor M402, a PMOS transistor M403, a PMOS transistor M404, a PMOS transistor M405, a PMOS transistor M406, a PMOS transistor M409, an NMOS transistor M407, an NMOS transistor M408, an NMOS transistor M4010, a resistor R401, a resistor R402, a PMOS transistor M41, a PMOS transistor M43, a PMOS transistor M45, a PMOS transistor M46, a PMOS transistor M49, a PMOS transistor M411, an NMOS transistor M42, an NMOS transistor M44, an NMOS transistor M47, an NMOS transistor M48, an NMOS transistor M410, an NMOS transistor M412, a resistor R41, a resistor R42, and a capacitor C41.

The PMOS transistor M401, the PMOS transistor M402, the PMOS transistor M403, the PMOS transistor M404, the PMOS transistor M405, the PMOS transistor M406, the PMOS transistor M409, the NMOS transistor M407, the NMOS transistor M408, the NMOS transistor M4010, the resistor R401 and the resistor R402 form a three-stage comparator; the PMOS tube M41, the PMOS tube M43, the NMOS tube M42, the NMOS tube M44, the resistor R41, the resistor R42 and the capacitor C41 form a buffer with an RC filtering function; a Schmitt trigger is formed by a PMOS tube M45, a PMOS tube M46, a PMOS tube M49, an NMOS tube M47, an NMOS tube M48 and an NMOS tube M410; the PMOS transistor M411 and the NMOS transistor M412 form an output inverter. The input end of the buffer with the RC filtering function is connected to the comparison output voltage Vo1 of the wide voltage range comparator circuit, the output end of the buffer with the RC filtering function is connected to the input end of the schmitt trigger, the output end of the schmitt trigger is connected to the input end of the output inverter, and the output end of the output inverter is the final data output Douth of the output shaping circuit 604.

The internal circuit structure of the three-level comparator is as follows: the PMOS tube M401, the PMOS tube M402, the PMOS tube M403, the resistor R401 and the resistor R402 form an input stage of a three-stage comparator, the PMOS tube M404, the PMOS tube M405, the PMOS tube M406, the NMOS tube M407 and the NMOS tube M408 form an amplification stage of the three-stage comparator, and the PMOS tube M409 and the NMOS tube M4010 form an output stage of the three-stage comparator; the connection relationship of the internal circuit of the buffer with the RC filtering function is as follows: the gates of the PMOS transistor M41 and the NMOS transistor M42 are simultaneously connected to the comparison output voltage of the three-stage comparator, the drains of the PMOS transistor M41 and the NMOS transistor M42 are simultaneously connected to the gates of the PMOS transistor M43 and the NMOS transistor M44, the drain of the PMOS transistor M43 is connected to the upper end of the resistor R41, the lower end of the resistor R41 is connected to the upper end of the resistor R42, the upper end of the capacitor C41 and the input end of the Schmidt trigger, the lower end of the resistor R42 is connected to the drain of the NMOS transistor M44, the simultaneous sources of the PMOS transistor M41 and the PMOS transistor M43 are connected to the power supply voltage VCC, and the sources of the NMOS transistor M42 and the NMOS transistor M44 and the lower end of the capacitor C41 are simultaneously connected to the floating ground SW.

The output shaping circuit 604 of the present invention shown in fig. 11 provides, on the one hand, three-stage comparators for converting the input differential signal into a standard digital logic signal Douth; on the other hand, the RC low-pass filtering and the Schmitt trigger combined filtering are adopted, and a certain hysteresis quantity is kept so as to effectively filter the high-frequency interference influence caused by the common-mode noise.

Fig. 12 is a specific implementation of the common mode adaptive adjustment circuit 605 according to the present invention, which includes a common mode detection circuit 100, a common mode detection signal transmission circuit 101, an adjustment common mode signal generation circuit 102, and a common mode adjustment signal selection circuit 103. The common mode detection circuit 100 is configured to detect power supply and substrate noise, and change the magnitude of a common mode detection signal Vcm _ det when the noise is greater than a certain threshold, where the common mode detection signal Vcm _ det is connected to the common mode detection signal transmission circuit 101, and the Vcm _ det generates common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2, NN1, NN2 through the common mode detection signal transmission circuit 101, and outputs the common mode selection switch control signals N11, N12, N21, N22, N1, N2, NN1, and NN2 to the common mode adjustment signal selection circuit 103; the common mode adjusting signal selecting circuit 103 generates and adjusts the magnitude of the common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2, CN1 and CN2 according to the common mode selecting switch control signal and outputs the common mode adjusting signals; the adjustment common mode signal generating circuit 102 is configured to generate various common mode bias signals required by the common mode adjustment signal selecting circuit 103, and output the common mode bias signals to the common mode adjustment signal selecting circuit 103.

In the circuit shown in fig. 12, the common mode detection signal transmission circuit 101 is implemented by using a distributed inverter chain, and the common mode detection signal Vcm _ det is propagated through N sets of distributed inverter chains to obtain N sets of common mode control signals. The adjustment common mode signal generating circuit 102 generates a high input common mode level Vcmh and a low input common mode level Vcml through a bias signal path from the power supply voltage VDD to SW. For the implementation of Vcmh and Vcml, an implementation with the minimum hardware overhead is shown in the figure, and the same function can be realized by adopting reference voltage division or other circuits such as LDO and the like, which are not described herein. The common mode adjusting signal selecting circuit 103 has an internal circuit of a switch selecting array, and the switch array determines the outputs of the common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2, CN1 and CN2 according to the values of the common mode selecting switch control signals N11, N12, N21, N22, …, NX1, NX2, NN1 and NN 2.

Fig. 13 shows an implementation of the common mode detection circuit 100 according to the present invention. The common mode detection circuit 100 is used to detect power supply and substrate noise, and change the magnitude of the common mode detection signal Vcm _ det when the noise is greater than a certain threshold value, so as to control the output of the common mode adaptive adjustment circuit 605 shown in fig. 12. The common mode detection circuit is composed of a PMOS tube M111, a PMOS tube M112 and an NMOS tube M113; the grid electrode and the drain electrode of the PMOS tube M111 are connected, and the grid electrode is connected with the drain electrode of the PMOS tube M112 and the grid electrode of the NMOS tube M113; the grid electrode of the PMOS tube M112 is connected with the drain electrode of the NMOS tube M113 and is used as an output node of a common mode detection signal Vcm _ det; the sources of the PMOS transistors M111 and M112 are connected to the power supply voltage VDD, and the source of the NMOS transistor M113 is connected to SW.

Fig. 14 shows a waveform diagram of the operation of the common mode detection circuit 100. Assuming the circuit is operating in a half-bridge driven high side circuit with SW connected to the half-bridge output, the SW signal needs to swing between 0 and VH. VH is the voltage difference existing between the maximum values of the high/low voltage regions of the power semiconductor device. VDD is a power supply voltage VHB of the high-side circuit, and bootstrap floating is performed by the bootstrap capacitor based on the SW potential, so that the bootstrap voltage VDD is VHB and SW + VCC during normal operation. Because the capacitor bootstrap charging also needs a certain charging time, in the capacitor charging process, VHB cannot completely synchronize the fluctuation of SW, which leads to a certain delay of VDD relative to SW, the voltage difference between the power supply and the ground in the delay interval is not strictly equal to VCC, which is equivalent to power supply common mode noise, and when the noise amplitude is large enough, the circuit function is influenced, and the false triggering of the comparator is generated.

As shown in the waveform of fig. 14, when the half-bridge output SW is stable, VDD and SW voltages are in a stable state, M111 is turned on, M113 is turned on, and Vcm _ det will be pulled down to SW by M113, and is at a low level; when SW switches from 0 to VH, SW voltage is synchronously switched to VH, but VDD has a certain delay, a certain delay interval is generated, VDD does not reach VH + VCC in the delay interval, the grid voltage of M113 is not enough to enable M113 to be conducted, M113 is closed, Vcm _ det is influenced by SW to generate a peak high pulse under the action of parasitic capacitance until VDD reaches VH + VCC, at the moment, M113 is conducted again, Vcm _ det is pulled down to SW by M113.

As shown in fig. 1, the total isolation of the capacitive isolation IGBT driver chip according to the present invention is realized by two sets of isolation capacitors (Ctp and Crp form a set of P-end series isolation capacitors, Ctn and Crn form a set of N-end series isolation capacitors) connected in series to achieve voltage isolation, and the middle is connected to the upper plates of the two series isolation capacitors through Bonding wires (Bonding wires), so that the total voltage value of the capacitive isolator chip is the sum of the voltage values of the two capacitors in the series capacitors. Usually, the withstand voltage of SiO2 is about 500V/um, and in a CMOS process of 0.18um, if M1 is used as the lower plate of the isolation capacitor and M6 is used as the upper plate of the isolation capacitor, the total thickness of SiO2 between metal layers is about 6-7 um, that is, the withstand voltage of a single isolation capacitor is about 3000V-3500V, and the withstand voltages of two isolation capacitors are about 6000V-7000V. The voltage resistance can meet common and conventional application, and cannot meet the voltage resistance requirement of ultrahigh voltage isolation.

As shown in fig. 15, the ultra-high withstand voltage isolation capacitor according to the present invention includes, from bottom to top: deep N-well isolation region DNWELL 50, lower plate 51 (first layer M1), SiO₂Layer 52, passivation layer 53 and top plate 54. The passivation layer 53 is SiO₂And Si₃N₄And (3) superposition. Wherein, SiO₂The layer thicknesses are mainly VIA12, M2 (second layer), VIA23, M3 (third layer), VIA34, M4 (fourth layer), VIA45, M5 (fifth layer), VIA56, M6 (sixth layer), and the total thickness is addedThe degree is 8-9 um. The thickness of the passivation layer 53 is 2-3 um. Si of the passivation layer 53₃N₄Is arranged on SiO in an overlapping way₂Above layer 52 because of Si₃N₄Having a specific SiO ratio₂Better compactness and pressure resistance. The upper electrode plate 54 is made of metal Cu, the upper electrode plate 54 is formed by processing the rear end of the wafer, a layer of metal Cu is formed on the passivation layer 53, and the metal Cu is also used as a PAD. A deep N-well isolation region DNWELL is arranged below the lower plate 51, and a substrate of the wafer is arranged below the deep N-well isolation region DNWELL. The deep N-well isolation region DNWELL should have an area larger than the planar area of the lower plate 51 and entirely cover the lower surface of the lower plate 51.

According to the scheme of the ultrahigh voltage-withstanding isolation capacitor, the thickness of a passivation layer is controlled to be about 2.5um through process adjustment, the thickness of a single isolation capacitor is about 12um approximately, and the voltage withstanding value can reach 6000V, so that the total thickness of two isolation capacitors connected in series is about 24um, the total voltage withstanding value can reach 12000V, the requirement of isolation enhancement can be met, the capacitance value is reduced after the isolation capacitors are thickened, the area of an isolation capacitor plate can be properly increased, the capacitance value of the isolation capacitors can be basically kept unchanged, and the transmission quality of the whole isolation signal is not influenced.

The low-voltage power supply circuit is a basic functional module that any analog IC must be equipped with, and a block diagram of an implementation structure that the transmitting-end low-voltage generation circuit 8 and the receiving-end low-voltage generation circuit 9 of the present invention can use is shown in fig. 16. The circuit internally comprises: a start-up circuit 801, a bandgap reference voltage generation circuit 802, a reference voltage generation circuit and buffer circuit 803, a bias signal generation circuit 804, and an input low voltage generation circuit 805. After the chip VCC voltage is powered on, the start-up circuit 801 is the first circuit to be turned on in the whole chip, and the start-up circuit usually provides a certain initial bias signal to generate a fixed reference voltage and a fixed reference current for the bandgap reference voltage generation circuit 802; the reference voltage is used for generating various reference voltages required by the internal work of the chip through a reference voltage generating circuit and is output through a buffer circuit; the reference current typically enters bias signal generation circuit 804, which generates various types of bias signals for biasing other analog circuits within the chip, as well as providing bias to reference voltage generation circuit and input low voltage generation circuit 805. The input low voltage generation circuit 805 typically generates a 3-10V floatable low voltage supply voltage VCL.

Fig. 17 shows an implementation of the low-side output driver circuit 4 according to the present invention. The power supply of the driving circuit is VCC, the output driving circuit is composed of a plurality of inverter chains with gradually-amplified sizes and MOS (metal oxide semiconductor) tubes M221 and M222, the branch circuit where the M221 and M222 tubes are located determines the output current of the driving circuit and the output impedance of the circuit, and therefore the width-length ratio of the M221 and M222 tubes is designed according to the requirements of driving devices. In order to make the IGBT controlled by the output to be rapidly saturated and turned on and reliably off, the output driving circuit is required to have a small output impedance and a large output current (several amperes). The high side output driver circuit 7 has the same structure as the low side output driver circuit 4 except that VDD is used for the power supply, a floating ground SW is connected to the ground terminal, Douth is input, and HO is output.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. The utility model provides an insulating IGBT half-bridge gate drive circuit of keeping apart of superhigh pressure, characterized by includes: the circuit comprises an input receiving circuit (1), a dead time generating circuit (2), a low-side delay circuit (3), a low-side output driving circuit (4), a modulation transmitting circuit (5), an isolating circuit (10) consisting of 4 high-voltage capacitors, a high common-mode transient suppression differential signal receiving circuit (6), a high-side output driving circuit (7), a transmitting end low-voltage generating circuit (8) and a receiving end low-voltage generating circuit (9); the isolation circuit (10) comprises a positive end sending capacitor Ctp, a negative end sending capacitor Ctn, a positive end receiving capacitor Crp and a negative end receiving capacitor Crn;

the low-voltage digital input signals HI and LI firstly enter an input receiving circuit (1) to carry out signal level discrimination and logic level high-voltage conversion to obtain medium-voltage signals H and L, and the medium-voltage signals H and L are connected to a dead time generating circuit (2); the dead time generating circuit (2) obtains high-side differential input data HIP and HIN according to the medium-voltage signal H, and obtains low-side differential input data LIP and LIN according to the medium-voltage signal L; high-side differential input data HIP and HIN are connected to a modulation transmitting circuit (5) to obtain differential transmitting data TxP and TxN; the differential sending data TxP and TxN are respectively connected to the left end of a positive terminal sending capacitor Ctp and the left end of a negative terminal sending capacitor Ctn; the right end of the positive end sending capacitor Ctp and the right end of the negative end sending capacitor Ctn are respectively connected to the left end of the positive end receiving capacitor Crp and the left end of the negative end receiving capacitor Crn; the right end of the positive terminal receiving capacitor Crp and the right end of the negative terminal receiving capacitor Crn respectively generate differential receiving data RxP and RxN; the differential receiving data RxP and RxN are connected to a high common mode transient suppression differential signal receiving circuit (6) and processed to obtain high-side receiving output data Douth; the high-side receiving output data Douth is finally connected to the input end of a high-side output driving circuit (7) to generate an output driving signal HO with large driving current; the low-side differential input data LIP and LIN are input into a low-side delay circuit (3), the low-side delay circuit (3) outputs low-side drive data Doutl, the low-side drive data Doutl is output to a low-side output drive circuit (4), and a low-side output signal LO is obtained through drive amplification;

the high common mode transient suppression differential signal receiving circuit (6), the high side output driving circuit (7) and the receiving end low voltage generating circuit (9) form a receiving end circuit; the input receiving circuit (1), the dead time generating circuit (2), the sending end low voltage generating circuit (8), the modulation sending circuit (5), the low-side delay circuit (3) and the low-side output driving circuit (4) form a sending end circuit; the high common mode transient suppression differential signal receiving circuit (6), the high side output driving circuit (7) and the receiving end low voltage generating circuit (9) share a floating ground SW, and the input receiving circuit (1), the dead time generating circuit (2), the transmitting end low voltage generating circuit (8), the modulation transmitting circuit (5), the low side delay circuit (3) and the low side output driving circuit (4) share a low voltage ground GND; the low-side output drive circuit (4) and the high-side output drive circuit (7) are output drive circuits with the same circuit structure; the transmitting end low voltage generating circuit (8) and the receiving end low voltage generating circuit (9) are low voltage generating circuits with the same structure; the transmitting end low-voltage generating circuit (8) is connected with a transmitting end power supply voltage VCC and generates various reference voltages and bias voltages required by a low-voltage power supply VCL input to the receiving circuit (1) and various component circuits in the transmitting end circuit; the receiving end low voltage generating circuit (9) is connected with a receiving end power supply voltage VDD to generate various reference voltages and bias voltages required by all the internal circuit components of the receiving end circuit;

the high common mode transient suppression differential signal receiving circuit (6) comprises: the device comprises a differential input receiving circuit (601), an X-level front-back cascade common mode adjustable amplifying circuit (602), a high-sensitivity common mode adjustable amplifying circuit (603), an output shaping circuit (604) and a common mode self-adaptive adjusting circuit (605);

the differential input receiving circuit (601) receives a positive terminal receiving signal RxP and a negative terminal receiving signal RxN of differential receiving data at first, and obtains a positive terminal input signal Vip and a negative terminal input signal Vin through filtering processing; the positive end input signal Vip and the negative end input signal Vin enter a first-stage common mode adjustable amplifying circuit in an X-stage common mode adjustable amplifying circuit (602) which is cascaded in front and at the back, and finally a positive end output signal VoXp and a negative end output signal VoXn of the X-stage common mode adjustable amplifying circuit are obtained; the positive end output signal VoXp and the negative end output signal VoXn are respectively connected with the positive input end and the negative input end of the high-sensitivity common mode adjustable amplifying circuit (603), and the high-sensitivity common mode adjustable amplifying circuit (603) outputs a group of differential output signals which comprise a positive end output signal VoNp and a negative end output signal VoNn; the output shaping circuit (604) processes the positive end output signal VoNp and the negative end output signal VoNn to obtain final data output, namely high-side receiving output data Douth; the common mode self-adaptive adjusting circuit (605) generates common mode adjusting signals C11, C12, C21, C22, …, CX1 and CX2 for each stage of amplifying circuit in a self-adaptive mode according to changes of power supply and ground voltage signals, and the common mode adjusting signals C11 and C12 generated by the common mode self-adaptive adjusting circuit (605) are respectively connected to a common mode adjusting signal input end of the first stage of common mode adjustable amplifying circuit; the common mode adjusting signals C21 and C22 are respectively connected to the common mode adjusting signal input end of the second-stage common mode adjustable amplifying circuit; by analogy, the common mode adjusting signals CX1 and CX2 are respectively connected to the common mode adjusting signal input end of the X-th order common mode adjustable amplifying circuit; the common mode adaptive adjusting circuit (605) also generates common mode adjusting signals CN1 and CN2 which are respectively connected to the common mode adjusting signal input end of the high-sensitivity common mode adjustable amplifying circuit (603); wherein X is a positive integer greater than 1, and N is a positive integer greater than X.

2. The half-bridge gate driving circuit of the ultra-high voltage insulated and isolated IGBT as claimed in claim 1, wherein the positive side transmitting capacitor Ctp, the negative side transmitting capacitor Ctn, the positive side receiving capacitor Crp and the negative side receiving capacitor Crn are equal in size and are ultra-high voltage-withstanding isolation capacitors.

3. The ultra-high voltage isolated IGBT half-bridge gate drive circuit of claim 1, wherein the differential input receiving circuit (601) comprises: a positive side isolation capacitor C51, a positive side grounding resistor R51, a positive side coupling capacitor C52, a positive side common mode resistor R53, a negative side isolation capacitor C53, a negative side grounding resistor R52, a negative side coupling capacitor C54, a negative side common mode resistor R54 and a receiving common mode generating circuit (6011); the left end of the positive side isolation capacitor C51 and the left end of the negative side isolation capacitor C53 are connected to the positive side receive signal RxP and the negative side receive signal RxN, respectively; the right end of the positive side isolation capacitor C51 is connected to the upper end of the positive side ground resistor R51 and the left end of the positive side coupling capacitor C52; the right end of the negative end isolation capacitor C53 is connected to the upper end of a negative end ground resistor R52 and the left end of a negative end coupling capacitor C54; the right end of the positive terminal coupling capacitor C52 is connected to the upper end of the positive terminal common mode resistor R53 and serves as the output terminal of the positive terminal input signal Vip; the right end of the negative end coupling capacitor C54 is connected to the lower end of the negative end common mode resistor R54 and serves as the output end of a negative end input signal Vin; the lower end of the positive end common mode resistor R53 is connected with the upper end of the negative end common mode resistor R54 and is simultaneously connected to a common mode output end Vicm of the receiving common mode generating circuit (6011); the receiving common mode generating circuit (6011) dynamically tracks and adjusts the size of a common mode output end Vicm according to the change of an input common mode Vcm, and the influence of an input common mode is reduced.

4. The ultra high voltage isolated IGBT half-bridge gate drive circuit according to claim 3, wherein the receiving common mode generating circuit (6011) comprises: NMOS transistor M60, NMOS transistor M61, PMOS transistor M62, PMOS transistor M63, PMOS transistor M64, PMOS transistor M65, NMOS transistor M66, NMOS transistor M67, PMOS transistor M68, NMOS transistor M69, PMOS transistor M610, NMOS transistor M611, PMOS transistor M612, NMOS transistor M613, NMOS transistor M614, PMOS transistor M615, resistor R61, and first Schmidt trigger (600);

the grid electrode of the NMOS tube M60 is connected to an input common mode voltage Vcm; the drain electrode of the NMOS tube M60 is connected to the drain electrode and the gate electrode of the PMOS tube M62 and the gate electrode of the PMOS tube M63; the grid electrode of the NMOS tube M61 is connected to an input common mode control signal Vctrl; the drain electrode of the NMOS tube M61 is connected with the drain electrode of the PMOS tube M63 and is connected to the input end of the first Schmitt trigger (600); the output end of the first Schmitt trigger (600) is simultaneously connected to the grid electrode of the PMOS tube M610, the grid electrode of the NMOS tube M611, the grid electrode of the PMOS tube M612 and the grid electrode of the NMOS tube M613; the drain electrode of the PMOS tube M610 is connected with the drain electrode of the NMOS tube M611 and is also connected to the grid electrode of the NMOS tube M614; the drain of the PMOS tube M612 is connected with the drain of the NMOS tube M613, and is also connected to the gate of the PMOS tube M615; the drain electrode of the NMOS tube M614 is connected with the source electrode of the PMOS tube M615 and is also used as an output port of the common mode output end Vicm; the source electrode of the NMOS tube M614 is connected to a high input common mode level Vcmh, and the drain electrode of the PMOS tube M615 is connected to a low input common mode level Vcml; the source of the NMOS transistor M613 is connected to the upper end of the resistor R61; the source electrode of the NMOS tube M60, the source electrode of the NMOS tube M61, the source electrode of the NMOS tube M611 and the lower end of the resistor R61 are simultaneously connected to the floating ground SW; the source of the PMOS transistor M62, the source of the PMOS transistor M63 and the source of the PMOS transistor M610 are simultaneously connected to the receiving terminal power voltage VDD.

5. The half-bridge gate driving circuit of the ultra-high voltage insulated isolation IGBT as claimed in claim 1, wherein the high-sensitivity common mode adjustable amplifying circuit (603) is a front-stage and a rear-stage fully differential amplifying circuit, and comprises a front-stage common mode adjustable amplifying circuit and a rear-stage differential amplifying circuit which are connected with each other; the positive input end of the preceding common mode adjustable amplifying circuit is the positive input end of the high-sensitivity common mode adjustable amplifying circuit (603), and the negative input end of the preceding common mode adjustable amplifying circuit is the negative input end of the high-sensitivity common mode adjustable amplifying circuit (603); a positive output end VoNp of the differential amplifying circuit is a positive output end of the high-sensitivity common-mode adjustable amplifying circuit (603), and a negative output end VoNn of the differential amplifying circuit is a negative output end of the high-sensitivity common-mode adjustable amplifying circuit (603);

6. The half-bridge gate driving circuit of the ultra-high voltage insulated isolation IGBT as claimed in claim 1, wherein the output shaping circuit (604) comprises a three-level comparator, a buffer with RC filtering function, a second Schmitt trigger and an output inverter, which are connected in sequence, and the output end of the output inverter is the final output data, i.e. the high-side received output data Douth; the connection relationship of the internal circuit of the buffer with the RC filtering function is as follows: the grid of the PMOS tube M41 and the grid of the NMOS tube M42 are simultaneously connected to the comparison output voltage of the three-stage comparator, the drain of the PMOS tube M41 and the drain of the NMOS tube M42 are simultaneously connected to the grid of the PMOS tube M43 and the grid of the NMOS tube M44, the drain of the PMOS tube M43 is connected to the upper end of a resistor R41, the lower end of the resistor R41 is connected to the upper end of a resistor R42, the upper end of a capacitor C41 and the input end of a second Schmidt trigger, the lower end of the resistor R42 is connected to the drain of the NMOS tube M44, the source of the PMOS tube M41 and the source of the PMOS tube M43 are simultaneously connected to a power supply voltage VDD, and the source of the NMOS tube M42, the source of the NMOS tube M44 and the lower end of the capacitor C41 are simultaneously connected to a floating ground SW.

7. The ultra high voltage isolated IGBT half-bridge gate drive circuit of claim 1, wherein the common mode adaptive adjustment circuit (605) comprises: the common mode detection circuit (100), the common mode detection signal transmission circuit (101), the adjustment common mode signal generation circuit (102) and the common mode adjustment signal selection circuit (103); the common mode detection circuit (100) is used for detecting power supply and substrate noise and changing the size of a common mode detection signal Vcm _ det when the noise is larger than a certain threshold, the common mode detection signal Vcm _ det is connected to the common mode detection signal transmission circuit (101), common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2, NN1 and NN2 are generated through the common mode detection signal transmission circuit (101) and output to the common mode adjustment signal selection circuit (103); the common mode adjusting signal selection circuit (103) generates and adjusts the magnitude of common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2, CN1 and CN2 according to the common mode selecting switch control signal and outputs the common mode adjusting signals; the adjusting common-mode signal generating circuit (102) is used for generating various common-mode bias signals required by the common-mode adjusting signal selecting circuit (103) and outputting the common-mode bias signals to the common-mode adjusting signal selecting circuit (103).

8. The ultra high voltage isolated IGBT half-bridge gate drive circuit of claim 7, wherein the common mode detection circuit (100) comprises: a PMOS transistor M111, a PMOS transistor M112 and an NMOS transistor M113; the grid electrode and the drain electrode of the PMOS tube M111 are connected, and the grid electrode is connected with the drain electrode of the PMOS tube M112 and the grid electrode of the NMOS tube M113; the grid electrode of the PMOS tube M112 is connected with the drain electrode of the NMOS tube M113 and is used as an output node of a common mode detection signal Vcm _ det; the sources of the PMOS transistors M111 and M112 are connected to the power supply voltage VDD, and the source of the NMOS transistor M113 is connected to the floating ground SW.