CN111464172B

CN111464172B - Low-delay high-side driving circuit suitable for GaN device

Info

Publication number: CN111464172B
Application number: CN202010314887.7A
Authority: CN
Inventors: 陈珍海; 吴勇; 何宁业; 汪礼; 许媛; 宁仁霞; 王东; 鲍婕; 吕海江
Original assignee: Huangshan University; Wuhu Research Institute of Xidian University
Current assignee: Huangshan University; Wuhu Research Institute of Xidian University
Priority date: 2020-04-21
Filing date: 2020-04-21
Publication date: 2023-03-14
Anticipated expiration: 2040-04-21
Also published as: CN111464172A

Abstract

The invention discloses a low-delay high-side driving circuit suitable for a GaN device, which comprises a low-delay high-voltage level shift circuit and an output driving circuit; the low-voltage input data firstly enter a low-delay high-voltage level shift circuit, drive data Din with floating low potential is obtained and enters an output drive circuit, and an output signal HO with larger drive capability is obtained through drive amplification; the low-delay high-voltage level shift circuit needs to use two groups of ground potentials of a low-voltage ground VSS and a floating ground SW, and the output drive circuit only needs to use the floating ground SW. The low-delay high-side driving circuit for the GaN device reduces the delay of the level shift circuit through a positive feedback driving current enhancement technology, can adaptively adjust the driving current according to the load size and the frequency of the input control pulse to improve the efficiency to the maximum extent, and can be widely applied to various gate driving chips.

Description

Low-delay high-side driving circuit suitable for GaN device

Technical Field

The invention relates to a high-side driving circuit for a half-bridge gate driving chip, and belongs to the technical field of integrated circuits.

Background

Under the traction of emerging industries such as smart grid, mobile communication and new energy automobile, power electronic application systems require further improvement of system efficiency, miniaturization and function increase, and particularly require circuitsTradeoffs between size, mass, power and efficiency apply, such as server power management, battery chargers and micro-inverters for solar farms. The above applications require power electronics systems to be efficient at design>95% of the total power, and also has high power density (>500W/in ³ I.e. 30.5W/cm ³ ) High specific power (10 kW/lb, 22 kW/kg) and high total load point(s) ((>1000W). With the emergence and popularization of super junction MOSFETs and Insulated Gate Bipolar Transistors (IGBTs), particularly with the rise of wide bandgap power semiconductor devices represented by SiC and GaN, the requirements of new generation power electronic application systems on the power semiconductor device driving technology are increasing, and the most central factor among them is the high-voltage gate driving chip for controlling the functions of the power semiconductor device. The new generation of power electronic complete machine system puts forward higher requirements on the driving speed and the intellectualization of the high-voltage grid driving chip, thereby further improving the reliability of the complete machine and reducing the design complexity of the complete machine system.

Fig. 1 shows a typical high-voltage half-bridge gate driver chip and an application circuit block diagram which are most commonly used in power electronic application systems. As shown in fig. 1, a typical half-bridge driving circuit is divided into a high-side and a low-side two-channel driving circuit, the high-side driving circuit implements signal transmission control by using a bootstrap boosting method, and two low-voltage inputs HI and LI enter the high-side and the low-side two-channel channels, respectively. During the period that the low side LI inputs high level, the LO outputs high level, the switch ML is turned on, the switch node (SW) is pulled down to ground, and at this time, VDD charges the bootstrap capacitor through the bootstrap diode so that the voltage difference between the two ends of the bootstrap capacitor approaches VDD. During the period when the high side HI inputs high level, HO outputs high level, the high side MH is turned on, and the switch node voltage rises to VH, that is, SW rises to VH. Since the voltage across the bootstrap capacitor is constant, the bootstrap voltage rail HB is bootstrapped to SW + VDD. The high-side circuit always keeps VHB-SW ≈ VDD. Since half-bridge output control signals HO and LO directly drive the gate terminals of power switches MH and ML, HO and LO must have relatively large drive currents provided by output driver H and output driver L circuits inside the half-bridge chip, respectively.

In the circuit of fig. 1, the transmission of the low voltage input HI signal to the HO output is all accomplished by the high side driver circuit. A typical high-side driving circuit structure is shown in fig. 2, and the circuit structure is from US patent No. 5552731, and the circuit is composed of a high-voltage level shift circuit, an RS flip-flop and an output driving circuit, and adopts a differential signal transmission technology to improve the common-mode rejection capability. Due to the high-low voltage isolation region between the high-side driving circuit and the low-side driving circuit, the high-voltage level shifting circuit is used for transmitting a low-voltage input HI signal to the high-side output driving circuit. In a typical BCD process, a high-voltage level shift circuit must use a high-voltage-resistant LDMOS to implement signal transmission, the high-voltage LDMOS has a large parasitic capacitance, which severely limits the signal processing speed of the circuit shown in fig. 2, and the speed of a 650V high-side driving circuit adopting this technology is usually limited below 200KHz, which cannot meet the processing speed requirement that a wide-bandgap power device represented by GaN and SiC exceeds MHz. It is therefore desirable to optimize the delay characteristics of the circuit of fig. 2 to provide a low-delay, high-speed, high-side driver circuit.

In addition, after the conventional half-bridge gate driver chip is designed, the output driving capability of the high-side output control signal HO is solidified. In practical applications, to prevent the HO output current from damaging the gate of the power switch MH, a resistor is usually connected in series with the HO output terminal to suppress the gate voltage overshoot. When the gate terminal equivalent capacitance of MH is large, the series protection resistor needs to be small, otherwise, the series protection resistor needs to be large. The larger series protection resistor brings 2 problems, firstly, the switch on the resistor is damaged and enlarged, and the efficiency of the driving circuit is reduced; secondly, the driving time delay is increased, and finally the switching frequency of the system is reduced. In addition, the use of series protection resistors also increases the design workload of design engineers and reduces the reliability of the overall system. Therefore, it is necessary to provide an output driving circuit capable of automatically adjusting the magnitude of the driving current according to the gate capacitance of the power switch transistor, thereby improving the efficiency of the overall high-side driving circuit.

Based on the above, the invention provides a high-side driving circuit with low delay and high efficiency for the gate driving application requirements of wide bandgap power devices represented by GaN and SiC.

Disclosure of Invention

The invention aims to overcome the defects in the prior art, provides a high-side driving circuit for a half-bridge gate driving chip, and is a low-delay high-efficiency high-side driving circuit suitable for a GaN device.

According to the technical scheme provided by the invention, the low-delay high-side driving circuit suitable for the GaN device comprises: the low-delay high-voltage level shift circuit and the output drive circuit are connected in sequence; low-voltage input data enters a low-delay high-voltage level shift circuit to obtain driving data Din with floating low potential, and then enters an output driving circuit, and an output control signal HO with driving capability is obtained through driving amplification; the low-delay high-voltage level shift circuit needs to use two groups of ground potentials of a low-voltage ground VSS and a floating ground SW, and the output drive circuit only needs to use the floating ground SW; the input end of the output driving circuit is also connected with a trigger control clock signal Clk-ctrl and a power-on signal Start-up, and the driving capability of the output driving circuit is controlled by the trigger control clock signal Clk-ctrl and the power-on signal Start-up.

Specifically, the low-delay high-voltage level shift circuit includes: the high-voltage LDMOS device comprises a high-voltage LDMOS transistor MD1, a high-voltage LDMOS transistor MD2, a protection diode D1, a protection diode D2, a resistor R3, a resistor R4, a resistor R1, a resistor R2, a coupling MOS transistor M1, a coupling MOS transistor M2, a speed enhancement transistor Me1, a speed enhancement transistor Me2, an error hysteresis filter circuit and a signal overturn detection circuit;

the source ends of the high-voltage LDMOS transistor MD1 and the high-voltage LDMOS transistor MD2 are connected with a low-voltage ground VSS; the drain terminal of the high-voltage LDMOS transistor MD1 is simultaneously connected to the source terminal of the coupling MOS transistor M1, the anode of the protection diode D1, the lower terminal of the resistor R3 and the gate terminal of the coupling MOS transistor M2; the drain terminal of the high-voltage LDMOS transistor MD2 is simultaneously connected to the source terminal of the coupling MOS transistor M2, the anode of the protection diode D2, the lower terminal of the resistor R4 and the gate terminal of the coupling MOS transistor M1; the drain end of the coupling MOS tube M1 is connected to the upper end of the resistor R1, and is also connected to the data input P end LSP of the error hysteresis filter circuit and the drain end of the speed enhancement transistor Me 1; the drain end of the coupling MOS tube M2 is connected to the upper end of the resistor R2, and is also connected to the data input N end LSN of the error hysteresis filter circuit and the drain end of the speed enhancement transistor Me 2; the lower ends of the resistor R1 and the resistor R2 are connected with a floating ground SW; the output of the error delay filter circuit is driving data Din, and the driving data Din is also connected with the input end of the signal overturn detection circuit; 2 output ends of the signal turnover detection circuit are respectively connected with the grid ends of the speed enhancement transistor Me1 and the speed enhancement transistor Me 2; the cathode of the protection diode D1, the cathode of the protection diode D2, the upper end of the resistor R3, the upper end of the resistor R4, the source end of the speed enhancement transistor Me1, and the source end of the speed enhancement transistor Me2 are simultaneously connected to a high-voltage power supply voltage.

Specifically, the error hysteresis filter circuit includes a P-side circuit and an N-side circuit that have the same structure, and the P-side circuit includes: p end coupling inverter, P end burring circuit, P end OR gate, P end data selector, N end circuit includes the same structure with it: the N-terminal coupling phase inverter, the N-terminal deburring circuit, the N-terminal OR gate and the N-terminal data selector are connected in series; wherein the connection relationship of the P-side circuit is as follows: the P-end deburring circuit internally comprises 3 two-input NAND gates and a two-input OR gate, wherein a first input end of a first NAND gate is connected with an input signal, a second input end of the first NAND gate is connected with an output end of the first OR gate, an output end of the first NAND gate is connected with a first input end of a third NAND gate, a second input end of the third NAND gate is connected with an output end of a second NAND gate, an output end of the third NAND gate is connected with a second input end of the first OR gate, a first input end of the second NAND gate and a control port C of a P-end data selector, a second input end of the P-end OR gate is connected with a first data port S0 of the P-end data selector, and an output end of the P-end OR gate is connected with a second data port S1 of the P-end data selector;

for the P-side circuit, the input signal is a signal HIP, and for the N-side circuit, the input signal is a signal HIN; meanwhile, the signal HIP is connected with a first input end of a P-end OR gate through a P-end coupling inverter, and a first input end of a first OR gate and a second input end of a second NAND gate in an N-end circuit; the signal HIN is connected with a first input end of an N-end OR gate through an N-end coupling phase inverter, and a first input end of a first OR gate of a P-end circuit and a second input end of a second NAND gate; the output port D of the P-end data selector outputs a signal LSP, and the D of the N-end data selector outputs a signal LSN.

Specifically, the output driving circuit includes: the device comprises an input P-end inverter chain, N P-end output inverters, N P-end output PMOS (P-channel metal oxide semiconductor) tubes, N P-end output inverter control switches, an input N-end inverter chain, N N-end output inverters, N N-end output NMOS (N-channel metal oxide semiconductor) tubes, N N-end output inverter control switches, a sampling switch SW, an input data switch Kin, a test data switch Kcal, a high-speed comparator array, an error filtering circuit, a load judging circuit, a driving current selecting circuit, an input pulse frequency judging circuit and a controller circuit;

the P-end inverter chain is k cascaded P-end input buffer inverters, and the driving capability of the k inverters is gradually increased from a front stage to a rear stage; the N-end inverter chain comprises k-1 cascaded N-end input buffer inverters and a delay unit connected in front of the most front-end inverter, and the driving capability of the k-1 inverters is gradually increased from the front stage to the rear stage; the delay time of the delay unit must be equal to the delay time of the front-end P-end input buffer inverter; the output of the P-end inverter chain is simultaneously connected to the left sides of the N P-end output inverter control switches, and the output of the N-end inverter chain is simultaneously connected to the left sides of the N N-end output inverter control switches; the P-terminal inverter chain is connected to the input end of the N-terminal inverter chain and is connected to the right side of the input data switch Kin and the test data switch Kcal; wherein n is a natural number, and k is a natural number greater than 1;

the right sides of the N P-end output inverter control switches are respectively connected with the grid ends of the N P-end output PMOS tubes, and the right sides of the N N-end output inverter control switches are respectively connected with the grid ends of the N N-end output NMOS tubes; the source ends of the N P-end output PMOS tubes are simultaneously connected to power supply voltage, the source ends of the N N-end output NMOS tubes are simultaneously connected to the ground, and the drain ends of the N P-end output PMOS tubes are simultaneously connected to the drain ends of the N N-end output NMOS tubes and the output end of a drive circuit, namely a port for outputting a control signal HO;

the output control signal HO enters a high-speed comparator array after being sampled by a sampling switch SW, is compared with n reference voltages, and then enters an error filtering circuit to output a load detection code Dtest; the input pulse frequency discrimination circuit compares and quantizes the frequency of the input driving data Din to obtain a Din frequency discrimination code Dfin; the load detection code Dtest and the frequency discrimination code Dfin enter a load discrimination circuit at the same time to calculate to obtain a load evaluation code Dev; the driving current selection circuit selects and outputs switch control signals of N P-end output inverter control switches and switch control signals of N N-end output inverter control switches according to the size of the load evaluation code Dev;

the load test signal Dcal output by the controller circuit is connected to the left side of a test data switch Kcal, a test clock Clkcal output by the controller circuit is connected to a clock input end of an input pulse frequency discrimination circuit, a load test control signal Ctrl _ test output by the controller circuit is respectively connected to a control signal input end of the high-speed comparator array and a control signal input end of the error filtering circuit, a control signal Ctrl _ ev output by the controller circuit is connected to a control signal input end of the load discrimination circuit, a Ctrl _ out signal output by the controller circuit is connected to a control signal input end of the driving current selection circuit, and a Ctrl _ fin signal output by the controller circuit is connected to a control signal input end of the input pulse frequency discrimination circuit; the input end of the controller circuit is connected with a trigger control clock signal Clk-ctrl and a power-on signal Start-up, and is controlled by the two signals; the frequency of the trigger control clock signal Clk-ctrl must be R times the frequency of the load test signal Dcal, R being a natural number greater than 1.

Specifically, the working state of the output driving circuit includes a driving capability adaptive adjustment mode and a normal working mode; when the power supply voltage is powered on, firstly, the driving capability adaptive adjustment mode is started, and then the normal working mode is entered.

Specifically, the workflow in the driving capability adaptive adjustment mode is as follows:

after the power supply voltage is electrified, the controller circuit closes the input data switch Kin, outputs a test clock Clkcal, and opens the input pulse frequency discrimination circuit, and the input pulse frequency discrimination circuit compares and quantizes the frequency of the input data Din based on the test clock Clkcal to obtain a Din frequency discrimination code Dfin;

when the output establishment time is met, the controller circuit starts a test data switch Kcal and outputs a load test signal Dcal, and additionally, a high-speed comparator array, an error filtering circuit, a load judging circuit and a driving current selection circuit are started, and at the moment, an output control signal HO of the driving circuit changes according to different loads;

the controller circuit starts a sampling switch SW to sample the voltage of an output end HO of the driving circuit, and a load detection code Dtest is obtained after the voltage is processed by a high-speed comparator array and an error filtering circuit;

the load judging circuit calculates to obtain a load evaluation code Dev according to the load detection code Dtest and the Din frequency judging code Dfin;

the driving current selection circuit sets the switch control signals of the N P-end output inverter control switches and the switch control signals of the N N-end output inverter control switches according to the load evaluation code Dev, and keeps the switch control signals unchanged;

the output setup time consists of M Clk-ctrl clock cycles, the time span of which must be less than 1 cycle time of the load test signal Dcal; wherein M is a natural number less than R;

the process of comparing and quantizing the frequency of the input data Din by the input pulse frequency discrimination circuit needs to quantize the frequency of the Din by using J test clock Clkcal periods, wherein the time length of the J test clock Clkcal periods must be greater than one period of the Din, namely the frequency of the test clock Clkcal is X times of the frequency of the input data Din; wherein X is more than 1, and J is a natural number more than X.

Specifically, the controller circuit includes: a frequency discrimination control generating circuit for generating a Ctrl _ fin signal to control the input pulse frequency discrimination circuit; a switch signal generation circuit for generating switch control signals Kcal, SW, and Kin; the load test control generation circuit is used for generating a load test control signal Ctrl _ test to control the high-speed comparator array and the error filtering circuit; the load discrimination control generation circuit is used for generating a Ctrl _ ev signal to control the load discrimination circuit; the drive current control generation circuit is used for generating a Ctrl _ out signal to control the drive current selection circuit; a test code generation circuit for generating a load test code Dcal and a test clock Clkcal; the output end of the counter circuit is respectively connected with the frequency discrimination control generating circuit, the switching signal generating circuit, the load test control generating circuit, the load discrimination control generating circuit, the driving current control generating circuit and the test code generating circuit, and is used for providing the Ctrl _ fin, kcal, SW, kin, ctrl _ test, ctrl _ ev, ctrl _ out, dcal and Clkcal signals according to the sequence to generate the required trigger signals according to the trigger control clock signal Clk-Ctrl and the power-on signal Start-up which are input from the outside.

Specifically, the frequency of the external trigger control clock Clk-ctrl must be much higher than the frequency of the input data Din; the frequency of the test clock Clkcal cannot be lower than that of the control clock Clk-ctrl, and the higher the Clkcal frequency, the more accurate the discrimination of the Din frequency.

Specifically, the load determination circuit includes: 2 registers used for storing the load detection code Dtest and the frequency discrimination code Dfin respectively, and a normalization quantization calculation circuit for calculating the load detection code Dtest and the frequency discrimination code Dfin; the data output of the 2 registers is controlled by the same signal and is all output to the normalization quantization calculation circuit; the load evaluation code Dev output by the normalization quantization calculation circuit is calculated by Dtest and Dfin, and the calculation formula is: dev = G × Dtest/Dfin; wherein G is a gain coefficient, and G is greater than 1.

The invention has the advantages that: the low-delay high-side driving circuit suitable for the GaN device reduces the delay of the high-voltage level shifting circuit through a positive feedback current enhanced driving technology, and improves the anti-interference performance of a level shifting signal by adopting a high-reliability error hysteresis filtering circuit, so that the anti-interference performance of the driving circuit is improved while the response speed of the driving circuit is improved; in addition, the driving current can be adaptively adjusted according to the load size and the frequency of the input control pulse, and the power consumption overhead of the output driving circuit is reduced to the maximum extent, so that the output effective power and efficiency of the whole driving circuit are improved, and the gate driving circuit can be widely applied to various gate driving chips.

Drawings

Fig. 1 is a block diagram of a typical half-bridge gate driving circuit and application system.

Fig. 2 is a diagram of a typical high side driver circuit.

Fig. 3 is a block diagram of a low-latency high-side driving circuit suitable for GaN devices according to the present invention.

FIG. 4 is a diagram of a low latency high voltage level shifter circuit according to the present invention.

FIG. 5 is a schematic diagram of the delay reduction principle of the low-delay high-voltage level shift circuit of the present invention.

FIG. 6 is a block diagram of the high reliability error hysteresis filter circuit according to the present invention.

FIG. 7 is a block diagram of an output driving circuit according to the present invention.

Fig. 8 is a flow chart of the adaptive adjustment process of driving capability according to the present invention.

FIG. 9 is a timing diagram of the operation of the output driving circuit according to the present invention.

Fig. 10 is a diagram illustrating the load detection principle of the present invention.

FIG. 11 is a block diagram of a load determination circuit according to the present invention.

FIG. 12 is a block diagram of a controller circuit according to the present invention.

Detailed Description

The present invention is described in further detail below with reference to the attached drawings and examples.

Fig. 3 is a block diagram of the general structure of the high-side driving circuit of the present invention. The circuit of the invention comprises a low-delay high-voltage level shift circuit 1 and an output drive circuit 2; the low-voltage differential input data HIP and HIN firstly enter a low-delay high-voltage level shift circuit 1, the obtained low-potential floating driving data Din enters an output driving circuit 2, and an output control signal HO with large driving capability is obtained through driving amplification; the low-delay high-voltage level shift circuit 1 only needs to use two groups of ground potentials of a low-voltage ground VSS and a floating ground SW, and the output drive circuit 2 only needs to use the floating ground SW; the driving capability of the output driving circuit 2 is controlled by the trigger control clock signal Clk-ctrl and the power-on signal Start-up.

Fig. 4 is a structural diagram of the low-latency high-voltage level shift circuit 1, which is obtained by improving a simple RS flip-flop into a highly reliable error hysteresis filter circuit 101 on the basis of fig. 2, adding enhancement transistors Me1 and Me2 for accelerating the rising speeds of LSP and LSN, and a signal inversion detection circuit 102 for controlling Me1 and Me 2.

Specifically, the low-delay high-voltage level shift circuit 1 includes: the high-voltage LDMOS comprises a high-voltage LDMOS transistor MD1, a high-voltage LDMOS transistor MD2, a protection diode D1, a protection diode D2, a resistor R3, a resistor R4, a resistor R1, a resistor R2, a coupling MOS tube M1, a coupling MOS tube M2, a speed enhancement transistor Me1, a speed enhancement transistor Me2, an error hysteresis filter circuit 101 and a signal overturn detection circuit 102.

The source ends of the high-voltage LDMOS transistor MD1 and the high-voltage LDMOS transistor MD2 are connected with a low-voltage ground VSS; the drain terminal of the high-voltage LDMOS transistor MD1 is simultaneously connected to the source terminal of the coupling MOS transistor M1, the anode of the protection diode D1, the lower terminal of the resistor R3 and the gate terminal of the coupling MOS transistor M2; the drain end of the high-voltage LDMOS transistor MD2 is simultaneously connected to the source end of the coupling MOS transistor M2, the anode of the protection diode D2, the lower end of the resistor R4 and the gate end of the coupling MOS transistor M1; the drain terminal of the coupling MOS transistor M1 is connected to the upper end of the resistor R1, and is also connected to the data input P terminal (P terminal and N terminal are commonly called as differential port) LSP of the error hysteresis filter circuit 101 and the drain terminal of the speed enhancement transistor Me 1; the drain terminal of the coupling MOS transistor M2 is connected to the upper end of the resistor R2, and is also connected to the data input N terminal LSN of the error hysteresis filter circuit 101 and the drain terminal of the speed enhancement transistor Me 2; the lower ends of the resistor R1 and the resistor R2 are connected with a floating ground SW; the output of the error lag filtering circuit 101 is driving data Din, and the Din is also used as an input signal of the signal overturn detecting circuit 102; 2 output ends of the signal turnover detection circuit 102 are respectively connected with the grid ends of the speed enhancement transistor Me1 and the speed enhancement transistor Me 2; the cathode of the protection diode D1, the cathode of the protection diode D2, the upper end of the resistor R3, the upper end of the resistor R4, the source end of the speed enhancement transistor Me1, and the source end of the speed enhancement transistor Me2 are simultaneously connected to a high-voltage power supply voltage.

Fig. 5 is a schematic diagram illustrating the delay reduction of the low-delay high-voltage level shift circuit 1 according to the present invention. Assuming that a pulse is input to HIP, the delay Din will change after a certain time, starting from 0, and the rising delay time of Din is td for the level shift circuit shown in fig. 2. The principle of the delay optimization of the present invention is to detect the change of Din through the signal inversion detection circuit 102, and accelerate the inversion speed of Din when it exceeds a certain threshold. At time t0, the LSP voltage starts to go from low to high from 0, causing Din to go from low to high from SW (in this case, VH voltage); at the time tdet, when the signal inversion detection circuit 102 confirms that Din changes from low to high and the Din voltage exceeds the threshold Vth-det of the signal inversion detection circuit 102, the signal inversion detection circuit 102 turns on the second speed enhancement transistor Me2 to accelerate the voltage rising speed of LSP, thereby accelerating the voltage rising process of Din from Vth-det to the high-voltage power supply VH + VCC; at the time tden, din can complete the inversion from low to high potential. For example, setting Vth-det to 20% of the VCC voltage, the overall flip time tden of Din from low to high can be reduced to 30% of the original td, i.e., the signal transmission delay from HIP to Din is reduced to 30%, and the speed of the corresponding driving circuit can be increased by more than 3 times. Obviously, the Vth-det is set at different threshold values, which has direct influence on the order of tden, and the smaller Vth-det is, the smaller tden is, and the shorter the delay is, but the more sensitive the error fluctuation of the LSP, so that the error hysteresis filter circuit 101 with high anti-interference performance needs to be designed to filter various error interferences on the LSP and the LSN.

Fig. 6 is a block diagram of a highly reliable error lag filtering circuit 101 that can be used in the present invention according to an embodiment. The circuit comprises a P-end circuit and an N-end circuit which are identical in structure, wherein the P-end circuit comprises: the P-side coupling inverter 1P1, the P-side deburring circuit 1P2, the P-side or gate 1P3, the P-side data selector MUXP, the N-side circuit includes the same structure: the N terminal is coupled with an inverter 1N1, an N terminal deburring circuit 1N2, an N terminal OR gate 1N3 and an N terminal data selector MUXN. Namely, the structures of the P-end deburring circuit and the N-end deburring circuit are the same, and the P-end deburring circuit and the N-end deburring circuit respectively comprise 3 2-input NAND gates and a 2-input OR gate.

Only the connection relationship of the P-side circuit is described below: the P-end deburring circuit 1P2 internally comprises 3 two-input nand gates and a two-input or gate, a first input end of a first nand gate is connected with an input signal, a second input end of the first nand gate is connected with an output end of the first or gate, an output end of the first nand gate is connected with a first input end of a third nand gate, a second input end of the third nand gate is connected with an output end of a second nand gate, an output end of the third nand gate is connected with a second input end of the first or gate, a first input end of the second nand gate and a C end (control port) of a P-end data selector MUXP, a second input end of the P-end or gate 1P3 is connected with an S0 end (first data port) of the P-end data selector MUXP, and an output end of the P-end or gate 1P3 is connected with an S1 end (second data port) of the P-end data selector MUXP.

For the P-side circuit, the input signal is a signal HIP, and for the N-side circuit, the input signal is a signal HIN; meanwhile, a signal HIP is connected with a first input end of a P-end OR gate 1P3 through a P-end coupling phase inverter 1P1, and a first input end of a first OR gate and a second input end of a second NAND gate in an N-end circuit; the signal HIN is connected with a first input end of an N-end OR gate 1N3, a first input end of a first OR gate of the P-end circuit and a second input end of a second NAND gate through an N-end coupling phase inverter 1N 1; the D-side (output port) output signal LSP of the P-side data selector MUXP and the D-side output signal LSN of the N-side data selector MUXN.

For the signal inversion detection circuit 102 in fig. 4, it can be implemented by a conventional combinational logic circuit, and the simplest manner is an inverter circuit, or an inverter circuit with a control function, where the inversion threshold of the inverter is Vth-det; the implementation mode with higher precision can be realized by adopting a high-speed comparator, wherein one end of the comparator is Vth-det, and the other end of the comparator is Din.

Figure 7 is a block diagram of an embodiment of the output driver circuit 2 of the present invention, the system comprises an input P-end inverter chain, an N-end inverter chain, N P-end output inverters Invpk _ 1-Invpk _ N, N N-end output inverters Invnk _ 1-Invnk _ N, N P-end output PMOS tubes Mp 1-Mpn, N N-end output NMOS tubes Mn 1-Mnn, N P-end output inverter control switches Kp 1-Kpn, N N-end output inverter control switches Kn 1-Knn, a sampling switch SW, an input data switch Kin, a test data switch Kcal, a high-speed comparator array 201, an error filtering circuit 202, a load judging circuit 203, a driving current selecting circuit 204, an input pulse frequency judging circuit 205 and a controller circuit 206;

the P-end inverter chain comprises k cascaded P-end input buffer inverters Invp 0-Invpk-1, and the driving capability of the k inverters is gradually increased from the front stage to the rear stage; the N-end inverter chain comprises k-1 cascaded N-end input buffer inverters Invn 1-Invn k-1 and a delay unit delay connected before the most front-stage inverter, and the driving capability of the k-1 inverters is gradually increased from the front stage to the rear stage; the delay time of the delay unit delay must be equal to the delay time of the front-end P-end input buffer inverter; the output of the P-end inverter chain is simultaneously connected to the left sides of the N P-end output inverter control switches Kp 1-Kpn, and the output of the N-end inverter chain is simultaneously connected to the left sides of the N N-end output inverter control switches Kn 1-Knn; the P-terminal inverter chain is connected with the input end of the N-terminal inverter chain and also connected to the right side of the input data switch Kin and the test data switch Kcal; the right sides of control switches Kp1 to Kpn of N P-end output inverters are respectively connected with gate ends of N P-end output PMOS tubes Mp1 to Mpn, and the right sides of control switches Kn1 to Knn of N N-end output inverters are respectively connected with gate ends of N N-end output NMOS tubes Mn1 to Mnn; the source ends of the N P-end output PMOS tubes Mp 1-Mpn are simultaneously connected to a power supply voltage, the source ends of the N N-end output NMOS tubes Mn 1-Mnn are simultaneously connected to the ground, and the drain ends of the N P-end output PMOS tubes Mp 1-Mpn are simultaneously connected to the drain ends of the N N-end output NMOS tubes Mn 1-Mnn and the output end of the output drive circuit 2, namely, a port for outputting a control signal HO.

The output HO of the output drive circuit 2 enters the high-speed comparator array 201 after being sampled by the sampling switch SW, is compared with n reference voltages to obtain a quantization code Dout, enters the error filter circuit 202, and outputs a load detection code Dtest after being filtered; the input pulse frequency discrimination circuit 205 compares and quantizes the frequency of the input data Din based on the test clock Clkcal to obtain a Din frequency discrimination code Dfin; the load detection code Dtest and the frequency discrimination code Dfin enter the load discrimination circuit 203 at the same time to calculate to obtain a load evaluation code Dev; the driving current selection circuit 204 selectively outputs the switch control signals Kp1 to Kpn of the N P-side output inverter control switches and the switch control signals Kn1 to Knn of the N-side output inverter control switches according to the size of Dev.

The load test signal Dcal output by the controller circuit 206 is connected to the left side of the test data switch Kcal, the test clock Clkcal output by the controller circuit 206 is connected to the clock input terminal of the input pulse frequency discrimination circuit 205, the load test control signal Ctrl _ test output by the controller circuit 206 is connected to the control signal input terminals of the high-speed comparator array 201 and the error filter circuit 202, respectively, the control signal Ctrl _ ev output by the controller circuit 206 is connected to the control signal input terminal of the load discrimination circuit 203, the Ctrl _ out signal output by the controller circuit 206 is connected to the control signal input terminal of the drive current selection circuit 204, and the Ctrl _ fin signal output by the controller circuit 206 is connected to the control signal input terminal of the input pulse frequency discrimination circuit 205; the controller circuit 206 is controlled by the trigger control clock signal Clk-ctrl and the power-on signal Start-up; the frequency of the trigger control clock signal Clk-ctrl must be R times the frequency of the load test signal Dcal. Wherein n is a natural number, and k and R are natural numbers greater than 1.

The operation state of the output driver circuit 2 shown in fig. 7 includes two modes, i.e., adaptive adjustment of driving capability and normal operation. After the power supply voltage is powered on, the output driving circuit 2 first starts the driving capability adaptive adjustment mode, and then enters the normal operation mode.

The driving capability adaptive adjustment process of the output driving circuit 2 is shown in fig. 8. After the power supply voltage is electrified, the electrifying Start-up signal is started to be effective from low to high; the controller circuit 206 will turn off the input data switch Kin, output the test clock Clkcal, turn on the deep pulse frequency discrimination circuit, and the input pulse frequency discrimination circuit 205 compares and quantizes the frequency of the input data Din based on the test clock Clkcal and obtains the Din frequency discrimination code Dfin; the controller circuit 206 then turns on the test data switches Kcal, kp1 and Kn1, and outputs the load test signal Dcal, and also turns on the high speed comparator array 201, the error filter circuit 202, the load judgment circuit 203 and the driving current selection circuit 204, at this time, the output HO of the driving circuit will generate different dv/dt changes according to the load; at the mth Clk-ctrl clock edge after Dcal output, when the output setup time (the time required for HO voltage to rise) is satisfied, the controller circuit 206 will turn on the sampling switch SW to sample the HO voltage, and obtain the load detection code Dtest through the processing of the high-speed comparator array 201 and the error filtering circuit 202; the load judging circuit 203 calculates to obtain a load evaluation code Dev according to the load detection code Dtest and the Din frequency judging code Dfin; the driving current selection circuit 204 sets the switch control signals Kp2 to Kpn and Kn2 to Knn according to the load evaluation code Dev, and keeps the same; at this time, the output driving capability of the output driving circuit 2 remains unchanged, and the driving capability adaptive adjustment mode is ended; the controller circuit 206 finally turns on the switch Kin, turns off the switch Kal and the load test signal Dcal, and the output driver circuit starts the normal operation mode.

Fig. 9 shows a control sequence of the driving capability adaptive adjustment process. The adaptive adjustment process of the driving capability of the output driving circuit 2 is triggered by a power-on Start-up signal, the power-on Start-up signal is changed from low to high to be effective, and the clock Clk-ctrl enters the controller circuit 206; the controller circuit 206 will output the test clock Clkcal, turn on the deep pulse frequency discrimination circuit, the input pulse frequency discrimination circuit 205 will compare and quantize the frequency of the input data Din based on the test clock Clkcal, and obtain Din frequency discrimination code Dfin through J test clocks Clkcal; the controller circuit 206 then outputs a load test signal Dcal, at which time the output HO of the driver circuit will produce different dv/dt changes depending on the load; at the mth Clk-ctrl clock edge after Dcal output, the controller circuit 206 will turn on the sampling switch SW to sample the HO voltage, and obtain the load detection code Dtest through the processing of the high-speed comparator array 201 and the error filtering circuit 202; the load judging circuit 203 calculates the load evaluation code Dev at the Juge clock edge according to the load detection code Dtest and the Din frequency judging code Dfin, and keeps the same; the driving current selection circuit 204 sets the switch control signals Kp2 to Kpn and Kn2 to Knn according to the load evaluation code Dev, and keeps the same; and finally, the power-on Start-up signal is changed from high to low to Start invalidation, the output driving capability of the output driving circuit 2 is kept unchanged, and the driving capability self-adaptive adjustment mode is ended.

In the adaptive adjustment process of the driving capability, the frequency of the control clock Clk-ctrl must be much higher (e.g. 10-100 times) than the frequency of the input data Din, for example, the Din frequency is 100khz, and the Clk-ctrl frequency is usually set above 10 MHz; the frequency of the test clock Clkcal cannot be lower than the frequency of the control clock Clk-ctrl, and the higher the Clkcal frequency, the more accurate the discrimination of the Din frequency.

In the process of comparing and quantifying the frequency of the input data Din by the input pulse frequency discrimination circuit 205, the time length of J periods of the test clock Clkcal must be longer than one period of Din (2 or more periods of Din are all possible). For example, if Din has a frequency of 100KHz and the test clock Clkcal has a frequency of 10MHz, then Din and Clkcal have corresponding signal periods of 10us and 0.1us, respectively, and J must be greater than 100. If Clkcal has a frequency X times Din (X is greater than 1), then J must be a natural number greater than X, and it is clear that the larger the value of J, the more precise the value of Dfin.

The output setup time consists of M Clk-ctrl clock cycles, and the time span from the output of Dcal to the Mth Clk-ctrl clock edge must be less than 1 cycle time of the load test signal Dcal. M is a natural number smaller than R. For example, if the Dcal frequency is 200khz and the Clk-ctrl frequency is 5MHz, then Dcal and Clk-ctrl have corresponding signal periods of 5us and 0.2us, respectively, then the value of M must be less than 25, and obviously the closer the value of M is to 25, the more accurate the value of Dtest is.

Fig. 10 can illustrate the load detection principle of the present invention. Assuming that after the output driving circuit 2 shown in fig. 7 turns on Kp1 and Kn1, the output current provided by the N-terminal output NMOS transistor Mn1 and the P-terminal output PMOS transistor Mp1 is Iout =0.5a, the frequency of clk-ctrl is 5MHz (corresponding to a signal period of 0.2 us), and M =5 is selected, the sampling switch SW will sample the HO voltage at the beginning of 1us of Dcal high level. For a fixed output Iout, it is obvious that the larger the load capacitance is driven, the lower the rising slope of HO, and the magnitude of HO voltage at 1us is inversely proportional to the load capacitance, i.e. the HO voltage at a load of 0.5nF should be 3 times the HO voltage at a load of 1.5 nF. Therefore, under the condition of a fixed driving current, the magnitude of the output driving load can be determined according to the magnitude of the HO voltage at 1us, and the magnitude of the output driving load can be quantized by comparing the HO voltage with the n reference voltages Vr 1-Vrn to obtain the load quantization code Dout.

In the embodiment of the invention, under the condition of fixed driving current, the work of comparing and quantizing the HO voltage at 1us and n reference voltages Vr 1-Vrn is realized by a high-speed comparator array 201, the function of the comparator array is similar to that of an ADC (analog-to-digital converter) circuit, so that the combination forms of the comparator array are various according to different quantization speeds of load detection. The HO voltage and n reference voltages Vr 1-Vrn can be compared and quantized by adopting n comparators, and the load quantization code Dout can be obtained by comparison in one clock period, the total scheme has the advantage of high speed, but the number of the used comparators is large, and the hardware cost is high; the HO voltage and n reference voltages Vr 1-Vrn can be subjected to successive comparison and quantization by adopting a comparator, so that a load quantization code Dout is obtained. The n reference voltages Vr 1-Vrn are also arranged in a matching way with the comparator combined strategy, and can be arranged at uniform intervals by adopting thermometer codes or arranged at different weights by adopting binary systems. Therefore, in practical implementation, a proper comparator type and combination strategy can be selected according to the requirements of the driver chip application system.

Because the high-speed comparator has certain maladjustment, and the higher the working speed of the comparator is, the more serious the maladjustment is, the load quantization code Dout needs to be subjected to error filtering to obtain the load detection code Dtest, and the realization of the error filtering circuit has great difference according to the combination realization strategy of the type of the Dout code and the front-end high-speed comparator array circuit. If the comparator array circuit adopts n comparators to work in parallel, a digital algorithm for offset calibration of a Flash ADC comparator is required to be adopted for error filtering; if the comparator array circuit adopts 1 comparator for multiplexing work, a digital algorithm for SAR ADC offset calibration needs to be adopted for error filtering.

Fig. 11 shows a block diagram of the load discriminating circuit 203 in the embodiment of the present invention, which includes 2

registers

1 and 2 for storing the load detection code Dtest and the frequency discriminating code Dfin, respectively, and a normalization quantization calculating circuit for performing calculation processing on the load detection code Dtest and the frequency discriminating code Dfin. The data output of register 1 and register 2 is controlled by the Juge signal. The load evaluation code Dev output by the normalization quantization calculation circuit is calculated by Dtest and Dfin, and the calculation formula is: dev = G × Dtest/Dfin. Where G is a gain factor, an empirical value, and is selected according to the application context of the output driver circuit 2, and in practical applications, G is usually greater than 1.

The practical function of the normalization quantization calculation circuit is to further optimize the output driving current of the output driving circuit according to the frequency of the input data Din. Because the load test signal Dcal is a fixed frequency signal, after the output load is tested, if the frequency of the input data Din is far less than that of Dcal, the driving current can be continuously reduced, thereby further improving the efficiency of the driving circuit and saving unnecessary power consumption overhead. For example, if the signal periods of Din and Dcal are 10us and 1us, respectively, then Din will have a frequency 10 times slower than a fixed load, and the charging time for the load capacitor can be extended by 10 times, so that a smaller driving current can be selected to charge and discharge the output load. Therefore, under the condition of meeting the requirements of the application system of the driving circuit, the coefficient G can be set to scale the Dev value, the output driving current is reduced, the efficiency of the driving circuit is further improved, and unnecessary power consumption overhead is saved.

Fig. 12 is a block diagram of the controller circuit 206 according to an embodiment of the present invention, and the function of the controller circuit 206 is to provide control signals required by other circuits according to the external trigger control clock signal and the power-on signal. The controller circuit 206 internally includes: a frequency discrimination control generation circuit 261 for generating a Ctrl _ fin signal to control the input pulse frequency discrimination circuit 205; a switch signal generating circuit 262 for generating switch control signals Kcal, SW, and Kin; a load test control generating circuit 263, configured to generate a load test control signal Ctrl _ test to control the high-speed comparator array 201 and the error filtering circuit 202; a load discrimination control generation circuit 264 for generating Ctrl _ ev signal to control the load discrimination circuit 203; a driving current control generating circuit 265 for generating Ctrl _ out signal to control the driving current selecting circuit 204; a test code generation circuit 266 for generating a load test code Dcal; the output end of the counter circuit 267 is connected to the frequency discrimination control generating circuit 261, the switching signal generating circuit 262, the load test control generating circuit 263, the load discrimination control generating circuit 264, the driving current control generating circuit 265 and the test code generating circuit 266, respectively, and is configured to provide the other control signals according to the sequence to generate the required trigger signals according to the external trigger control clock signal Clk-ctrl and the power-on signal Start-up.

The input pulse frequency discrimination circuit 205 of the present invention has a circuit function of comparing and quantizing the frequency of the input data Din by using the test clock Clkcal, and the function can be realized by using a phase discriminator circuit. The driving current selection circuit 204 may be implemented by using a decoder or a multiplexer to select signal switches. This is a matter of choice for the person skilled in the art in view of the prior art and will not be described in detail.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, which is intended to cover any modifications, equivalents, improvements, etc. within the spirit and scope of the present invention.

Claims

1. Low time delay high side drive circuit suitable for GaN device, characterized by includes: the low-delay high-voltage level shift circuit comprises a low-delay high-voltage level shift circuit (1) and an output drive circuit (2) which are connected in sequence; low-voltage input data enters a low-delay high-voltage level shift circuit (1) to obtain low-potential floating driving data Din, then enters an output driving circuit (2), and is subjected to driving amplification to obtain an output control signal HO with driving capability; the low-delay high-voltage level shift circuit (1) needs to use two groups of ground potentials of a low-voltage ground VSS and a floating ground SW, and the output drive circuit (2) only needs to use the floating ground SW; the input end of the output driving circuit (2) is also connected with a trigger control clock signal Clk-ctrl and a power-on signal Start-up, and the driving capability of the output driving circuit (2) is controlled by the trigger control clock signal Clk-ctrl and the power-on signal Start-up.

2. The low-latency high-side driving circuit suitable for the GaN device according to claim 1, wherein the low-latency high-voltage level shifting circuit (1) comprises: the high-voltage LDMOS transistor comprises a high-voltage LDMOS transistor MD1, a high-voltage LDMOS transistor MD2, a protection diode D1, a protection diode D2, a resistor R3, a resistor R4, a resistor R1, a resistor R2, a coupling MOS transistor M1, a coupling MOS transistor M2, a speed enhancement transistor Me1, a speed enhancement transistor Me2, an error hysteresis filter circuit (101) and a signal overturn detection circuit (102);

the source ends of the high-voltage LDMOS transistor MD1 and the high-voltage LDMOS transistor MD2 are connected with a low-voltage ground VSS; the drain end of the high-voltage LDMOS transistor MD1 is simultaneously connected to the source end of a coupling MOS transistor M1, the anode of a protection diode D1, the lower end of a resistor R3 and the gate end of a coupling MOS transistor M2; the drain end of the high-voltage LDMOS transistor MD2 is simultaneously connected to the source end of the coupling MOS transistor M2, the anode of the protection diode D2, the lower end of the resistor R4 and the gate end of the coupling MOS transistor M1; the drain end of the coupling MOS tube M1 is connected to the upper end of the resistor R1, and is also connected to the data input P end LSP of the error hysteresis filter circuit (101) and the drain end of the speed enhancement transistor Me 1; the drain end of the coupling MOS transistor M2 is connected to the upper end of the resistor R2, and is also connected to the data input N end LSN of the error hysteresis filter circuit (101) and the drain end of the speed enhancement transistor Me 2; the lower ends of the resistor R1 and the resistor R2 are connected with a floating ground SW; the output of the error hysteresis filter circuit (101) is driving data Din which is also connected with the input end of the signal overturn detection circuit (102); 2 output ends of the signal turnover detection circuit (102) are respectively connected with the grid ends of the speed enhancement transistor Me1 and the speed enhancement transistor Me 2; the cathode of the protection diode D1, the cathode of the protection diode D2, the upper end of the resistor R3, the upper end of the resistor R4, the source end of the speed enhancement transistor Me1, and the source end of the speed enhancement transistor Me2 are simultaneously connected to a high-voltage power supply voltage.

3. The low-latency high-side driving circuit for the GaN device as claimed in claim 2, wherein the error hysteresis filtering circuit (101) comprises a P-side circuit and an N-side circuit with the same structure, and the P-side circuit comprises: the P-side coupled inverter (1P 1), the P-side deburring circuit (1P 2), the P-side or gate (1P 3), and the P-side data selector (MUXP), the N-side circuit includes the same structure: the N-terminal coupling inverter (1N 1), the N-terminal deburring circuit (1N 2), the N-terminal OR gate (1N 3) and the N-terminal data selector (MUXN); wherein, the connection relationship of the P-side circuit is as follows: the P-end deburring circuit (1P 2) internally comprises 3 two-input NAND gates and a two-input OR gate, a first input end of a first NAND gate is connected with an input signal, a second input end of the first NAND gate is connected with an output end of the first OR gate, an output end of the first NAND gate is connected with a first input end of a third NAND gate, a second input end of the third NAND gate is connected with an output end of a second NAND gate, an output end of the third NAND gate is connected with a second input end of the first OR gate, a first input end of the second NAND gate and a control port C of a P-end data selector (MUXP), a second input end of the P-end OR gate (1P 3) is connected with a first data port S0 of the P-end data selector (MUXP), and an output end of the P-end OR gate (1P 3) is connected with a second data port S1 of the P-end data selector (MUXP);

for the P-side circuit, the input signal is a signal HIP, and for the N-side circuit, the input signal is a signal HIN; meanwhile, a signal HIP is connected with a first input end of a P-end OR gate (1P 3) through a P-end coupling phase inverter (1P 1), and a first input end of the first OR gate and a second input end of a second NAND gate in an N-end circuit; the signal HIN is connected with a first input end of an N-end OR gate (1N 3) through an N-end coupling phase inverter (1N 1), and a first input end of a first OR gate of the P-end circuit and a second input end of a second NAND gate; the output port D of the P-end data selector (MUXP) outputs a signal LSP, and the output port D of the N-end data selector (MUXN) outputs a signal LSN.

4. The low-latency high-side driving circuit for the GaN device according to claim 1, wherein the output driving circuit (2) comprises: the device comprises an input P-end inverter chain, N P-end output inverters, N P-end output PMOS tubes, N P-end output inverter control switches, an input N-end inverter chain, N N-end output inverters, N N-end output NMOS tubes, N N-end output inverter control switches, a sampling switch SW, an input data switch Kin, a test data switch Kcal, a high-speed comparator array (201), an error filtering circuit (202), a load judging circuit (203), a driving current selecting circuit (204), an input pulse frequency judging circuit (205) and a controller circuit (206);

the P-end inverter chain is k cascaded P-end input buffer inverters, and the driving capability of the k inverters is gradually increased from a front stage to a rear stage; the N-end inverter chain comprises k-1 cascaded N-end input buffer inverters and a delay unit connected in front of the most front-stage inverter, and the driving capability of the k-1 inverters is gradually increased from the front stage to the rear stage; the delay time of the delay unit must be equal to the delay time of the front-end P-end input buffer inverter; the output of the P-end inverter chain is simultaneously connected to the left sides of the N P-end output inverter control switches, and the output of the N-end inverter chain is simultaneously connected to the left sides of the N N-end output inverter control switches; the P-terminal inverter chain is connected to the input end of the N-terminal inverter chain and to the right side of the input data switch Kin and the test data switch Kcal; wherein n is a natural number, and k is a natural number greater than 1;

the output control signal HO enters a high-speed comparator array (201) after being sampled by a sampling switch SW, is compared with n reference voltages, and then enters an error filtering circuit (202) to output a load detection code Dtest; an input pulse frequency discrimination circuit (205) compares and quantizes the frequency of input drive data Din to obtain a Din frequency discrimination code Dfin; the load detection code Dtest and the frequency discrimination code Dfin enter a load discrimination circuit (203) at the same time to calculate to obtain a load evaluation code Dev; the drive current selection circuit (204) selects and outputs the switch control signals of the N P-end output inverter control switches and the switch control signals of the N N-end output inverter control switches according to the magnitude of the load evaluation code Dev;

the load test signal Dcal output by the controller circuit (206) is connected to the left side of a test data switch Kcal, the test clock Clkcal output by the controller circuit (206) is connected to the clock input end of an input pulse frequency discrimination circuit (205), the load test control signal Ctrl _ test output by the controller circuit (206) is respectively connected to the control signal input ends of the high-speed comparator array (201) and the error filter circuit (202), the control signal Ctrl _ ev output by the controller circuit (206) is connected to the control signal input end of the load discrimination circuit (203), the Ctrl _ out signal output by the controller circuit (206) is connected to the control signal input end of the drive current selection circuit (204), and the Ctrl _ fin signal output by the controller circuit (206) is connected to the control signal input end of the input pulse frequency discrimination circuit (205); the input end of the controller circuit (206) is connected with the trigger control clock signal Clk-ctrl and the power-on signal Start-up, and is controlled by the two signals; the frequency of the trigger control clock signal Clk-ctrl must be R times the frequency of the load test signal Dcal, R being a natural number greater than 1.

5. The low-latency high-side driving circuit suitable for the GaN device as claimed in claim 4, wherein the operating state of the output driving circuit (2) comprises a driving capability adaptive adjustment mode and a normal operating mode; when the power supply voltage is powered on, the driving capability adaptive adjustment mode is started first, and then the normal working mode is entered.

6. The low-latency high-side driving circuit suitable for GaN devices as claimed in claim 5, wherein the working procedure in the driving capability adaptive adjustment mode is as follows:

after the power supply voltage is electrified, the controller circuit (206) closes the input data switch Kin, outputs the test clock Clkcal, and opens the input pulse frequency discrimination circuit (205), and the input pulse frequency discrimination circuit (205) compares and quantizes the frequency of the input data Din based on the test clock Clkcal to obtain a Din frequency discrimination code Dfin;

when the output setup time is met, the controller circuit (206) turns on a test data switch Kcal and outputs a load test signal Dcal, and in addition, turns on the high-speed comparator array (201), the error filtering circuit (202), the load judging circuit (203) and the driving current selection circuit (204), and at the moment, the output control signal HO of the driving circuit changes according to different loads;

the controller circuit (206) starts a sampling switch SW to sample the voltage at the output end HO of the driving circuit, and a load detection code Dtest is obtained after the voltage is processed by the high-speed comparator array (201) and the error filtering circuit (202);

the load judging circuit (203) calculates to obtain a load evaluation code Dev according to the load detection code Dtest and the Din frequency judging code Dfin;

the drive current selection circuit (204) sets the switch control signals of the N P-end output inverter control switches and the switch control signals of the N N-end output inverter control switches according to the load evaluation code Dev, and keeps the switch control signals unchanged;

the process of comparing and quantizing the frequency of the input data Din by the input pulse frequency discrimination circuit (205) needs to quantize the frequency of the Din by using J test clock Clkcal periods, the time length of the J test clock Clkcal periods must be greater than one period of the Din, namely the frequency of the test clock Clkcal is X times of the frequency of the input data Din; wherein X is more than 1, J is a natural number more than X.

7. The low-latency high-side driver circuit for GaN devices of claim 4, wherein the controller circuit (206) comprises: a frequency discrimination control generation circuit (261) for generating a Ctrl _ fin signal to control the input pulse frequency discrimination circuit (205); a switch signal generation circuit (262) for generating switch control signals Kcal, SW and Kin; a load test control generation circuit (263) for generating a load test control signal Ctrl _ test to control the high-speed comparator array (201) and the error filtering circuit (202); a load discrimination control generation circuit (264) for generating a Ctrl _ ev signal to control the load discrimination circuit (203); a drive current control generation circuit (265) for generating a Ctrl _ out signal to control the drive current selection circuit (204); a test pattern generation circuit (266) for generating a load test pattern Dcal and a test clock Clkcal; the output end of the counter circuit (267) is respectively connected with the frequency discrimination control generation circuit (261), the switching signal generation circuit (262), the load test control generation circuit (263), the load discrimination control generation circuit (264), the driving current control generation circuit (265) and the test code generation circuit (266) and is used for providing the Ctrl _ fin, kcal, SW, kin, ctrl _ test, ctrl _ ev, ctrl _ out, dcal and Clkcal signals according to the sequence to generate the required trigger signals according to the trigger control clock signal Clk-Ctrl and the power-on signal Start-up which are input from the outside.

8. The low-latency high-side driving circuit for GaN devices of claim 7, wherein the frequency of the external trigger control clock Clk-ctrl must be much higher than the frequency of the input data Din; the frequency of the test clock Clkcal cannot be lower than the frequency of the control clock Clk-ctrl, and the higher the Clkcal frequency, the more accurate the discrimination of the Din frequency.

9. The low-latency high-side driving circuit for the GaN device according to claim 4, wherein the load discrimination circuit (203) comprises: 2 registers used for storing the load detection code Dtest and the frequency discrimination code Dfin respectively, and a normalization quantization calculation circuit for calculating the load detection code Dtest and the frequency discrimination code Dfin; the data output of the 2 registers is controlled by the same signal and is all output to the normalization quantization calculation circuit; the load evaluation code Dev output by the normalization quantization calculation circuit is calculated by Dtest and Dfin, and the calculation formula is: dev = G × Dtest/Dfin; wherein G is a gain coefficient, and G is greater than 1.