CN113193865B - Level shift circuit suitable for GaN half-bridge grid drive - Google Patents
Level shift circuit suitable for GaN half-bridge grid drive Download PDFInfo
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Abstract
The invention belongs to the technical field of power supplies, and particularly relates to a level shift circuit suitable for GaN half-bridge gate drive. The level shift circuit provided by the invention effectively avoids the limitation of a large voltage dynamic range on the LDMOS parasitic capacitor to the speed by a mode of the synergistic action of the active clamping level shift circuit controlled by the PWM signal and the acceleration module controlled by the short pulse, and realizes high-speed level conversion. Meanwhile, a node which is relatively low in the circuit and has large parasitic capacitance is separated from the output through the decoupling accelerating circuit, logic error overturn caused by charging and discharging of the parasitic capacitance relative to the ground is effectively avoided in the dV/dt conversion process, and the dV/dt noise suppression capability is improved.
Description
Technical Field
The invention belongs to the technical field of power supplies, and particularly relates to a level shift circuit suitable for GaN half-bridge gate driving.
Background
GaN power devices, which have smaller on-resistance and parasitic capacitance than Si MOSFET power devices, have been considered as a good solution for miniaturizing power supply systems. As a core module in the GaN half-bridge gate driving circuit, the speed of a level shift circuit and the dV/dt interference resistance of a floating power supply rail directly determine the working frequency and the reliability of the GaN half-bridge gate driving circuit. The GaN gate driving circuit generally has a switching frequency as high as several MHz to several tens MHz, which makes the transmission delay of the GaN gate driving circuit as low as ten and several nanoseconds. Because of the extremely low parasitic capacitance of the GaN power device, the switching speed of the GaN half-bridge switching node reaches 200V/ns or even higher, and the GaN gate driving circuit needs to be capable of reliably working at such a high switching speed of the switching node. Therefore, the extremely low transmission delay and the extremely high floating power rail switching speed of the GaN half-bridge gate driving circuit require the level shift circuit to have high speed and high anti-floating power rail dV/dt capability at the same time.
In the GaN half-bridge gate driving shown in fig. 1, an NLDMOS is usually used as a bridge between a low voltage domain and a high voltage domain in a level shift circuit to implement conversion of a signal from the low voltage domain to the high voltage domain. In the high-voltage BCD process or the high-voltage CMOS process, the parasitic capacitance CP between the NLDMOS drain and the substrate and the large voltage dynamic range on CP are limiting factors for the speed of the level shift circuit. In the switching process of the switching node, the high-side floating power supply VHB can generate charge and discharge current IP to the CP, and the IP can generate undershoot or overshoot at the output after flowing through the output impedance of the level shift circuit. When the dV/dt of the switch node is high, the IP is large, and the undershoot and the overshoot can touch the overturning threshold value of the rear-stage logic circuit, so that the GaN power tube is mistakenly started or mistakenly turned off, and system faults are caused.
Disclosure of Invention
The purpose of the invention is as follows: aiming at the limitation of parasitic capacitance between an NLDMOS tube drain electrode and a substrate in the level shift circuit on the circuit transmission speed and the dV/dt interference resistance, the level shift circuit which is suitable for a GaN half-bridge gate driving circuit and has high speed and high dV/dt interference resistance is provided, low transmission delay and high dV/dt interference resistance can be realized at the same time, and the harsh requirements of high-frequency and high-reliability operation of the GaN half-bridge gate driving circuit on the level shift circuit are met. The circuit structure comprises an active clamping level shift circuit, an acceleration module and a short pulse generation circuit.
The technical scheme of the invention is as follows:
a level shift circuit suitable for GaN half-bridge grid driving comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first NOMS tube, a second NOMS tube, a third NOMS tube, a fourth NOMS tube, a fifth NOMS tube, a sixth NOMS tube, a seventh NOMS tube, an eighth NOMS tube, a ninth NOMS tube, a tenth NOMS tube, an eleventh NOMS tube, a twelfth NOMS tube, a thirteenth NOMS tube, a fourteenth NOMS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a first PLDMOS tube, a second PLDMOS tube, a first NLDMOS tube, a second NLDMOS tube, a third DMOS NLDMOS tube, a fourth NLDMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first short pulse generation circuit and a non-gate generation circuit, as shown in FIG 2; wherein,
the source electrode of the first PMOS tube is connected with the power supply, and the grid electrode of the first PMOS tube is connected with the first input end; the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the first NMOS tube is connected with the first input end, and the source electrode of the first NMOS tube is grounded;
the source electrode of the second PMOS tube is connected with the power supply, and the grid electrode of the second PMOS tube is connected with the second input end; the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the second NMOS tube is connected with the second input end, and the source electrode of the second NMOS tube is grounded;
the connection point of the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube is connected with the input end of the NOT gate, and the output end of the NOT gate is connected with the connection point of the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube;
the source electrode of the third PMOS tube is connected with the high-side floating power supply, and the grid electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube after passing through the fourth resistor; the source electrode of the fourth PMOS tube is connected with the high-side floating power supply, and the grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube after passing through the third resistor;
the drain electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube through a third resistor, the grid electrode of the third NMOS tube is connected with the drain electrode of the fourth PMOS tube through a fourth resistor, and the source electrode of the third NMOS tube is connected with the high-side floating ground; the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube through a fourth resistor, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the third PMOS tube through a third resistor, and the source electrode of the fourth NMOS tube is connected with a high-side floating ground;
the drain electrode of the fifth NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the fifth NMOS tube is connected with the drain electrode of the fourth PMOS tube through a fourth resistor, and the source electrode of the fifth NMOS tube is connected with the high-side floating ground; the drain electrode of the sixth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the sixth NMOS tube is connected with the drain electrode of the third PMOS tube through a third resistor, and the source electrode of the sixth NMOS tube is connected with a high-side floating ground;
the drain electrode of the seventh NMOS tube is connected with the drain electrode of the third PMOS tube through a third resistor, and the grid electrode and the drain electrode of the seventh NMOS tube are both connected with the high-side floating ground; the drain electrode of the eighth NMOS tube is connected with the drain electrode of the fourth PMOS tube through a fourth resistor, and the grid electrode and the drain electrode of the eighth NMOS tube are both connected with a high-side floating ground;
one end of the first resistor is connected with the drain electrode of the seventh NMOS tube, and the other end of the first resistor is connected with the high-side floating ground; the source electrode of the first PLDMOS tube is connected with one end of a first resistor, and the grid electrode of the first PLDMOS tube is connected with the high-side floating ground; the drain electrode of the first NLDMOS tube is connected with the drain electrode of the first PLDMOS tube, the grid electrode of the first NLDMOS tube is connected with the power supply, and the source electrode of the first NLDMOS tube and the source electrode of the ninth NMOS tube are connected with the drain electrode of the first NMOS tube; the drain electrode of the ninth NMOS tube is connected with the power supply, and the grid electrode and the source electrode of the ninth NMOS tube are interconnected;
one end of the second resistor is connected with the high-side floating power supply, and the other end of the second resistor is connected with the drain electrode of the eighth NMOS tube;
the source electrode of the second PLDMOS tube is connected with the drain electrode of the eighth NMOS tube, and the grid electrode of the second PLDMOS tube is connected with the high-side floating ground; the drain electrode of the second NLDMOS tube is connected with the drain electrode of the second PLDMOS tube, the grid electrode of the second NLDMOS tube is connected with the power supply, and the source electrode of the second NLDMOS tube and the source electrode of the tenth NMOS tube are connected with the drain electrode of the second NMOS tube; the drain electrode of the tenth NMOS tube is connected with the power supply, and the grid electrode and the source electrode of the tenth NMOS tube are interconnected;
the source electrode of the fifth PMOS tube is connected with the high-side floating power supply, and the grid electrode of the fifth PMOS tube is interconnected with the drain electrode of the fifth PMOS tube; the source electrode of the sixth PMOS tube is connected with the high-side floating power supply, the grid electrode of the sixth PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the source electrode of the first PLDMOS tube; the source electrode of the seventh PMOS tube is connected with the high-side floating power supply, the grid electrode of the seventh PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the third PMOS tube;
the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the fifth PMOS tube, and the grid electrode and the source electrode of the eleventh NMOS tube are both connected with the high-side floating ground;
the drain electrode of the third NLDMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the third NLDMOS tube is connected with the power supply, and the source electrode of the third NLDMOS tube and the source electrode of the twelfth NMOS tube are connected with the drain electrode of the thirteenth NMOS tube; the drain electrode of the twelfth NMOS tube is connected with the power supply, and the grid electrode and the source electrode of the twelfth NMOS tube are interconnected; the grid electrode of the thirteenth NMOS tube is connected with the output of the first short pulse generating circuit, and the source electrode of the thirteenth NMOS tube is grounded;
the source electrode of the eighth PMOS tube is connected with the high-side floating power supply, and the grid electrode of the eighth PMOS tube is interconnected with the drain electrode of the eighth PMOS tube; the source electrode of the ninth PMOS tube is connected with the high-side floating power supply, the grid electrode of the ninth PMOS tube is connected with the drain electrode of the eighth PMOS tube, and the drain electrode of the ninth PMOS tube is connected with the source electrode of the second PLDMOS tube; the source electrode of the tenth PMOS tube is connected with the high-side floating power supply, the grid electrode of the tenth PMOS tube is connected with the drain electrode of the eighth PMOS tube, and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the fourth PMOS tube;
the drain electrode of the fourteenth NMOS tube is connected with the drain electrode of the eighth PMOS tube, and the grid electrode and the source electrode of the fourteenth NMOS tube are both connected with the high-side floating ground;
the drain electrode of the fourth NLDMOS tube is connected with the drain electrode of the eighth PMOS tube, the grid electrode of the fourth NLDMOS tube is connected with the power supply, and the source electrode of the fourth NLDMOS tube and the source electrode of the fifteenth NMOS tube are connected with the drain electrode of the sixteenth NMOS tube; the drain electrode of the fifteenth NMOS tube is connected with the power supply, and the grid electrode and the source electrode of the fifteenth NMOS tube are interconnected; the grid electrode of the sixteenth NMOS tube is connected with the output of the second short pulse generating circuit, and the source electrode of the sixteenth NMOS tube is grounded;
the connection point of the drain electrode of the third PMOS tube, the drain electrode of the fifth NMOS tube and the drain electrode of the seventh PMOS tube is a first output end; and the connection point of the drain electrode of the fourth PMOS tube, the drain electrode of the tenth PMOS tube and the sixth NMOS tube is a second output end.
Furthermore, the first short pulse generating circuit comprises a first inverter, a second inverter, a third inverter, an AND gate and a capacitor, wherein the first inverter, the second inverter and the third inverter are sequentially connected in series, the input end of the first inverter is connected with the second input end, the connection point of the second inverter and the third inverter is grounded through the capacitor, one input end of the AND gate is connected with the second input end, the other input end of the AND gate is connected with the output end of the third inverter, and the output end of the AND gate is the output end of the first short pulse generating circuit; the second short pulse generating circuit has the same structure as the first short pulse generating circuit, except that the input of the second short pulse generating circuit is the first input terminal.
The invention has the beneficial effects that: in the dV/dt conversion process, a node with large parasitic capacitance relative to a substrate is separated from an output node by a resistance decoupling latch, and the output logic state is kept unchanged by a decoupling acceleration circuit. The influence of parasitic current caused by dV/dt on output is completely blocked, the dV/dt resistance of the level shift circuit is not limited by parasitic capacitance of a relative substrate in the LDMOS and the on-resistance of a charging and discharging path of the parasitic capacitance, and the dV/dt resistance is remarkably improved. The accelerating module and the active clamping level shift circuit work cooperatively, so that the limitation of a large voltage dynamic range on a parasitic capacitor between the drain terminal of the LDMOS and the substrate on the circuit speed is eliminated, and high-speed signal transmission is realized.
Drawings
The parasitic capacitance of the NLDMOS relative to the substrate in the level shift circuit in the figure 1 limits the GaN gate drive delay and the dV/dt resistance.
FIG. 2 is a circuit diagram of a high speed high dV/dt suppression capability level shift circuit suitable for GaN gate drive.
FIG. 3 is a waveform diagram of the operation of a high speed high dV/dt suppression capability level shift circuit suitable for GaN gate driving according to the present invention.
Fig. 4 is a schematic diagram of the operation of the high-speed high dV/dt suppression capability level shift circuit for GaN gate driving during dV/dt conversion of the floating power rail according to the present invention, wherein (a) is a schematic diagram and (b) is a waveform diagram during the conversion.
FIG. 5 is a simulation diagram of a high speed high dV/dt suppression capability level shift circuit suitable for GaN gate drive during dV/dt conversion of a floating power rail.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings:
fig. 2 shows a circuit structure of the level shift circuit of the present invention. The circuit consists of an active clamping level shift circuit, an acceleration module and a short pulse generation circuit. The active clamp level shift circuit includes a resistor decoupling latch. The resistor decoupling latch and the acceleration module form a decoupling acceleration circuit.
In the resistor decoupling latch, a resistor is adopted to separate a PLDMOS source end and an output end which are relatively provided with large parasitic capacitance, and a high-side floating power supply ground V is blocked SW The effect of parasitic currents on the output logic state caused when a dV/dt transition occurs. The acceleration module charges and discharges a parasitic capacitance of the active clamp level shift circuit relative to ground in the process of dV/dt conversion of the floating power rail.
The accelerating module is also used for improving the transmission speed of the active clamping level shift circuit. The low-speed active clamping level shift circuit is controlled by an input PWM signal, the high-speed acceleration module is controlled by a short pulse, and when signal transmission between power rails occurs, the output state is rapidly changed under the synergistic effect of the input PWM signal and the short pulse, so that high-speed signal transmission is realized. The active clamp level shifting circuit is used for establishing and maintaining an output state, and the accelerating module is used for establishing the output state.
FIG. 2 shows a circuit diagram of a high speed high dV/dt suppression capability level shift circuit suitable for GaN gate drive according to the present invention. The NLDMOS tubes M5, M6, M17 and M18 and the PLDMOS tubes M7 and M8 are used for bearing high pressure. The input tubes M1, M2, M3, M4, M15 and M16 are low-voltage non-isolated MOSFETs. The M3 pipe and the M4 pipe are used for rapidly switching off the M5 pipe and the M6 pipe, so that the rising speed of the nodes N5 and N6 is increased. The MD1, MD2, MD3 and MD4 are low-voltage isolation type NMOS tubes with short-circuited gates and sources, and body diodes of the low-voltage isolation type NMOS tubes are used for clamping drain nodes of input tubes to avoid gate oxide breakdown of the input tubes. The devices in the shaded portion are low voltage isolated transistors and resistors, which are placed in the isolated deep N-well. The body diodes of transistors MD5, MD6, MD7, and MD8 are used to charge the parasitic capacitances at nodes N1, N2, N3, and N4 with respect to ground and protect the gate oxide of the low voltage isolation transistors. The resistor decoupling latch is composed of resistors R3 and R4 and transistors M9, M10, M11 and M12, M13, M14, R3 and R4 respectively connect nodes N1, N2 and V OUT 、V OUT- Separately, the effects of the floating supply rail dV/dt noise on the output can be effectively masked. Transistors M13 and M14 are used for fast pulldown V OUT And V OUT- . Resistors R1 and R2 are initialization resistors for the resistive decoupling latch.
The specific operation waveform of the circuit is shown in fig. 3. The active clamping circuit is controlled by a gate drive input PWM signal, and the acceleration module is controlled by a short pulse generated by the PWM signal through the short pulse generating circuit. The circuit operation is divided into two stages of output state establishment and output state maintenance. In the process of establishing the output state, when V IN When the voltage is turned from low to high, the transistor M is turned from low to high 1 ，M 5 And M 7 The pull-down path is configured to generate a pull-down current I applied to node N1 down 。V IN After passing through a short pulse generating circuit, V P1 From low to high, the acceleration module is started and acts on V through the current mirror OUT- And pull-up current I of node N2 up1 And I up . In I up1 、I up And I down The output state of the resistive decoupling latch can be rapidly flipped under the combined action of (a) and (b). When the short pulse signal V P1 At the end of the high level duration, the acceleration module is switched off, I up1 And I up The voltage is reduced to zero, the circuit enters an output state maintaining stage, the output state is kept unchanged only by the active clamping level shifting circuit in the stage, and no static current is generated. In the same way, V IN- Controlling output generation and V of level shift circuit IN The resulting logic states are controlled to the opposite state.
When the acceleration module is turned off, it needs to be ensured that the active clamp level shift circuit can be turned over to its equilibrium state under the action of the input PWM signal. When the active clamp level shift circuit is in the equilibrium state, as shown in fig. 2, the potentials of the nodes N1 and N2 are equal, V OUT And V OUT- The potentials are equal, and the potential at the node N5 or N6 rises slowly. R 3 And R 4 So that the active clamp level shift circuit can use a smaller pull-down current I down Will output V OUT Or V OUT- Is turned over to connectNear V HB . When V is OUT -V SW And V N1 -V SW Is logic high, V OUT- -V SW And V N2 -V SW Is logic low, I down Pull-down N1 nodes and V OUT When, assume M 7 The gate-source voltage of the tube is V and is increased by M 12 Pipe, R 4 And M 10 The inverter has a switching threshold of V T1 From M 12 ，M 14 The inverter is formed with a flip threshold of V T2 ，V HB And V SW Differential pressure of V DDH ，R 3 And R 4 Has a value of R dec . To ensure the pull-down current I down The latch state of the resistive decoupling inverter can be broken, and the following holds:
V<V T1 <V T2 (1)
wherein V thn And V thpd Respectively represent the threshold voltages of the low-voltage NMOS transistor and the PLDMOS transistor according to (1) - (3), R dec The requirements are satisfied:
as shown in FIG. 3, let T 0 For transmission delay of the short pulse generating circuit, T 1 For starting up from the acceleration module to generating a pull-up current I up1 And I up Time delay of (D), T 2 Generating a voltage V to node N2 for pull-up current N2 Time delay of the turn-up, T 3 Is a V N2 Is turned up to V OUT -V SW A reduced latency. Level shift circuit output falling edge transmission delay T DF Expressed as:
T DF ＝T 0 +T 1 +T 2 +T 3 (5)
let the transmission delay of the input inverter be T 5 Due to V OUT Relative V SW Is smaller than the parasitic capacitance of the node N1 or N2 from V P2 Is turned up to V OUT -V SW The transmission delay of the turn-up is less than T 1 +T 2 . Level shift circuit output rising edge transmission delay T DR Expressed as:
T DR <T 5 +T 0 +T 1 +T 2 (6)
T 3 determined by the positive feedback capability of the resistive decoupling latch, and T 3 ≈T 5 . Therefore, the rising edge propagation delay of the level shift circuit is smaller than the falling edge propagation delay.
As shown in fig. 3, the output V OUT -V SW In the process of turning down, when V N2 Quilt I up Is pulled up to near V HB And then, the output state of the level shift circuit is established. M in the saturation region at this time 8 Parasitic capacitance C of the transistor-to-node N6 N6 Charging when the potential V of the node N6 N6 Close to V HB When M is in contact with 8 The tube enters a deep linear area, and the active clamping level shift circuit completes state conversion. V N6 Rise from GND to V HB Time T of 4 Comprises the following steps:
wherein L is pd Is the fixed channel length, W, of the PLDMOS in the high voltage CMOS process nd And W pd Respectively NLDMOS tube M 6 、M 5 And a PLDMOS tube M 8 、M 7 Channel width of (1), K 1 ，K 2 And K 3 Is a process dependent constant. V p1 And V p2 Pulse width T of p ≧T 1 +T 2 +T 4 Due to T 1 And T 2 Much less than T 4 The minimum short pulse width is T 4 Determine according to the formula(7)，M 6 And M 5 The tube adopts minimum channel width and increases M 8 Pipe and M 7 The channel width of the tube is beneficial to reducing the short pulse width, and further reduces the power consumption of the circuit. Thus, PLDMOS tube M 7 And M 8 The choice of channel width presents a tradeoff between power consumption and layout area.
FIGS. 4(a) and 4(b) are waveform diagrams illustrating the operation of the decoupling acceleration circuit during positive and negative dV/dt transitions of the floating power rail. Before positive dV/dt conversion, V OUT -V SW And V N1 -V SW Is a logic high level, V OUT- -V SW And V N2 -V SW Is a logic low level. When the positive dV/dt slew rate of the floating supply rail is high, at node N3, M D5 And M 19 Parasitic capacitance C to node N3 with respect to the substrate N3 Charging, at node N4, M D6 Body diode and M of a tube 20 Parasitic capacitance C to node N4 with respect to the substrate N4 And (6) charging. At node N1, by M 21 Parasitic charging current I generated by tube P1 Is not sufficient to fully provide the parasitic capacitance C of N1 with respect to the substrate N1 At this time M D7 Body diode of tube and transistor M 21 、M 11 、M 23 Common pair C N1 Charging, V N1 -V SW Becomes a logic low level. Symmetrically, at node N2, M D8 Body diode of tube and transistor M 22 、M 12 、M 24 Common pair C N2 Charging, V N2 -V SW Remains at logic low. R dec And M 11 (M 12 )、M 23 (M 24 ) On-resistance of (a) determines V OUT And V OUT- The potential of (2). To ensure V OUT -V SW Remains at logic high level, R dec The requirements are satisfied:
wherein R is 11 And R 23 Each represents M 11 (M 12 ) And M 23 (M 24 ) On-resistance of V T Is a flip threshold, V, of the subsequent logic circuit D Is the body diode forward voltage drop. Due to circuit symmetry, when V OUT -V SW While maintaining a logic high level, V OUT- -V SW Also becomes a logic high level. When the dV/dt conversion process is over, transistor M is shown in FIG. 4(b) due to current mirror bandwidth limitations 21 -M 24 Will not turn off immediately, M 21 And M 22 Are respectively to C N1 And C N2 Charging, V N1 -V SW And V N2 -V SW Will be higher than V T2 ，M 23 And M 24 Avoid V OUT -V SW And V OUT- -V SW Changing to a logic low. When M is 21 -M 24 When the gate-source voltage of (1) is gradually decreased, V N1 -V SW And V N2 -V SW Gradually falls below V T2 When the active clamping level shift circuit enters an equilibrium state, V OUT -V SW And V OUT- -V SW Still remains logic high, M 7 Parasitic capacitance C of the tube-to-tube node N5 with respect to the substrate N5 Charging when M is 7 When entering the deep linear region, V N1 -V SW Rising above V T2 ，V OUT- -V SW Reverting to a logic high level.
Before negative dV/dt conversion, V OUT -V SW And V N1 -V SW Becomes a logic low level, V OUT- -V SW And V N2 -V SW Becomes a logic high level. When the floating supply rail negative dV/dt slew rate is high, C is at nodes N3 and N4 N3 And C N4 Respectively pass through M 19 Pipe and M 20 Body diode direction V of tube HB And (4) discharging. At node N1, C N1 Discharge current I of P3 Very large, C N3 By M 21 Body diode of (1), M 9 Tube and resistor R 3 、M 13 Discharge of the series path formed by the tubes, V N1 -V SW Becomes a logic high level. At node N2, C N2 By M 22 Body diode of, M 10 Tube and resistor R 4 、M 14 Discharge of the series path formed by the tubes, V N2 -V SW Remains at a logic high level. To ensure V OUT -V SW Remains at a logic low level, R dec The requirements are satisfied:
wherein R is 13 Is a transistor M 13 、M 14 The on-resistance of (1). When V is OUT -V SW When held at logic low, V OUT- -V SW Also becomes a logic low. After the negative dV/dt conversion is over, at M 7 And under the action of a resistive decoupling latch, V N1 -V SW Reverting to logic low level, V OUT- -V SW Reverting to a logic high level. The combination of the three formulas (4), (8) and (9) and the decoupling resistance value R dec The requirements are satisfied:
R dec(min) >max[R dec1 ,R dec2 ,R dec3 ] (10)
when the floating supply rail positive dV/dt slew rate is low, M is at node N1 21 The pipe can be paired with C N1 And C N5 Providing a sufficiently large charging current, V N1 -V SW Higher than V T2 . At node N2, M 22 dV/dt parasitic current pairs C in the tube N2 Charging, residual current flowing through M 10 The on-resistance of the tube. M 24 The dV/dt parasitic current in the tube flows through M 14 The on-resistance of the tube. M due to the smaller dV/dt 22 And M 24 Medium dV/dt parasitic currents are small, V OUT- -V SW Remains at logic low level, V N2 -V SW Below V T2 ，V OUT -V SW Remains at a logic high level. When the floating supply rail negative dV/dt slew rate is low, at node N2, C N2 Mainly by M 22 Is discharged by the body diode, V N2 -V SW Higher than V DDH . At node N1, C N1 Discharge current I of P3 Flows through M 9 On-resistance of the tube, resistance R 3 And M 13 The on-resistance of the tube. Because of the small negative dV/dt switching speed, I P3 Smaller, V OUT -V SW Remains at a logic low level, V N1 -V SW Below V T2 ，V OUT- -V SW Remains at a logic high level.
As discussed above, when the floating power rail is switched dV/dt, if the level is fixed for the input signal to the circuit and the decoupling resistor resistance R is fixed dec Satisfies the formula (10), V OUT -V SW The logic high level can be kept in any positive dV/dt conversion process, the logic low level can be kept in any negative dV/dt conversion process, and the dV/dt resistance of the level shift circuit can reach infinity theoretically. However, the dV/dt resistance of practical circuits is limited by the current capability of the transistor body diode, i.e. by the area of the body diode.
FIG. 5 is a diagram of simulation results of the level shift circuit of the present invention when the floating power rail switching speed is 300V/ns. When the floating power rail rises at a switching speed of 300V/ns, the undershoot of the output voltage is 0.69V, and no logic state false inversion occurs. When the floating power rail is lowered at a switching speed of 300V/ns, the overshoot of the output voltage is 0.38V, and no false logic state flip occurs.
In summary, the level shift circuit provided by the invention effectively avoids the limitation of a large voltage dynamic range on the LDMOS parasitic capacitor to the speed by the way of the synergistic action of the active clamping level shift circuit controlled by the PWM signal and the acceleration module controlled by the short pulse, and realizes high-speed level conversion. Meanwhile, a node which is relatively low in the circuit and has large parasitic capacitance is separated from the output through the decoupling accelerating circuit, logic error overturn caused by charging and discharging of the parasitic capacitance relative to the ground is effectively avoided in the dV/dt conversion process, and the dV/dt noise suppression capability is improved.
Claims (2)
1. A level shift circuit suitable for GaN half-bridge grid driving is characterized by comprising a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first NOMS tube, a second NOMS tube, a third NOMS tube, a fourth NOMS tube, a fifth NOMS tube, a sixth NOMS tube, a seventh NOMS tube, an eighth NOMS tube, a ninth NOMS tube, a tenth NOMS tube, an eleventh NOMS tube, a twelfth NOMS tube, a thirteenth NOMS tube, a fourteenth NOMS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a first PLDMOS tube, a second PLDMOS tube, a first NLDMOS tube, a second NLDMOS tube, a third DMOS NLDMOS tube, a fourth NLDMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first short pulse generation circuit and a non-gate generation circuit; wherein,
the source electrode of the first PMOS tube is connected with a power supply, and the grid electrode of the first PMOS tube is connected with the first input end; the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the first NMOS tube is connected with the first input end, and the source electrode of the first NMOS tube is grounded;
the source electrode of the second PMOS tube is connected with the power supply, and the grid electrode of the second PMOS tube is connected with the second input end; the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the second NMOS tube is connected with the second input end, and the source electrode of the second NMOS tube is grounded;
the connection point of the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube is connected with the input end of the NOT gate, and the output end of the NOT gate is connected with the connection point of the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube;
the source electrode of the third PMOS tube is connected with the high-side floating power supply, and the grid electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube after passing through the fourth resistor; the source electrode of the fourth PMOS tube is connected with the high-side floating power supply, and the grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube after passing through the third resistor;
the drain electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube through a third resistor, the grid electrode of the third NMOS tube is connected with the drain electrode of the fourth PMOS tube through a fourth resistor, and the source electrode of the third NMOS tube is connected with the high-side floating ground; the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube through a fourth resistor, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the third PMOS tube through a third resistor, and the source electrode of the fourth NMOS tube is connected with a high-side floating ground;
the drain electrode of the fifth NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the fifth NMOS tube is connected with the drain electrode of the fourth PMOS tube through a fourth resistor, and the source electrode of the fifth NMOS tube is connected with the high-side floating ground; the drain electrode of the sixth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the sixth NMOS tube is connected with the drain electrode of the third PMOS tube through a third resistor, and the source electrode of the sixth NMOS tube is connected with a high-side floating ground;
the drain electrode of the seventh NMOS tube is connected with the drain electrode of the third PMOS tube through a third resistor, and the grid electrode and the drain electrode of the seventh NMOS tube are both connected with the high-side floating ground; the drain electrode of the eighth NMOS tube is connected with the drain electrode of the fourth PMOS tube through a fourth resistor, and the grid electrode and the drain electrode of the eighth NMOS tube are both connected with a high-side floating ground;
one end of the first resistor is connected with the drain electrode of the seventh NMOS tube, and the other end of the first resistor is connected with the high-side floating ground; the source of the first PLDMOS tube is connected with one end of the first resistor, and the grid of the first PLDMOS tube is connected with the high-side floating ground; the drain electrode of the first NLDMOS tube is connected with the drain electrode of the first PLDMOS tube, the grid electrode of the first NLDMOS tube is connected with the power supply, and the source electrode of the first NLDMOS tube and the source electrode of the ninth NMOS tube are connected with the drain electrode of the first NMOS tube; the drain electrode of the ninth NMOS tube is connected with the power supply, and the grid electrode and the source electrode of the ninth NMOS tube are interconnected;
one end of the second resistor is connected with the high-side floating power supply, and the other end of the second resistor is connected with the drain electrode of the eighth NMOS tube;
the source electrode of the second PLDMOS tube is connected with the drain electrode of the eighth NMOS tube, and the grid electrode of the second PLDMOS tube is connected with the high-side floating ground; the drain electrode of the second NLDMOS tube is connected with the drain electrode of the second PLDMOS tube, the grid electrode of the second NLDMOS tube is connected with the power supply, and the source electrode of the second NLDMOS tube and the source electrode of the tenth NMOS tube are connected with the drain electrode of the second NMOS tube; the drain electrode of the tenth NMOS tube is connected with the power supply, and the grid electrode and the source electrode of the tenth NMOS tube are interconnected;
the source electrode of the fifth PMOS tube is connected with the high-side floating power supply, and the grid electrode of the fifth PMOS tube is interconnected with the drain electrode of the fifth PMOS tube; the source electrode of the sixth PMOS tube is connected with the high-side floating power supply, the grid electrode of the sixth PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the source electrode of the first PLDMOS tube; the source electrode of the seventh PMOS tube is connected with the high-side floating power supply, the grid electrode of the seventh PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the third PMOS tube;
the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the fifth PMOS tube, and the grid electrode and the source electrode of the eleventh NMOS tube are both connected with the high-side floating ground;
the drain electrode of the third NLDMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the third NLDMOS tube is connected with the power supply, and the source electrode of the third NLDMOS tube and the source electrode of the twelfth NMOS tube are connected with the drain electrode of the thirteenth NMOS tube; the drain electrode of the twelfth NMOS tube is connected with the power supply, and the grid electrode of the twelfth NMOS tube is interconnected with the source electrode of the twelfth NMOS tube; the grid electrode of the thirteenth NMOS tube is connected with the output of the first short pulse generating circuit, and the source electrode of the thirteenth NMOS tube is grounded;
the source electrode of the eighth PMOS tube is connected with the high-side floating power supply, and the grid electrode of the eighth PMOS tube is interconnected with the drain electrode of the eighth PMOS tube; the source electrode of the ninth PMOS tube is connected with the high-side floating power supply, the grid electrode of the ninth PMOS tube is connected with the drain electrode of the eighth PMOS tube, and the drain electrode of the ninth PMOS tube is connected with the source electrode of the second PLDMOS tube; a source electrode of the tenth PMOS tube is connected with the high-side floating power supply, a grid electrode of the tenth PMOS tube is connected with a drain electrode of the eighth PMOS tube, and a drain electrode of the tenth PMOS tube is connected with a drain electrode of the fourth PMOS tube;
the drain electrode of the fourteenth NMOS tube is connected with the drain electrode of the eighth PMOS tube, and the grid electrode and the source electrode of the fourteenth NMOS tube are both connected with the high-side floating ground;
the drain electrode of the fourth NLDMOS tube is connected with the drain electrode of the eighth PMOS tube, the grid electrode of the fourth NLDMOS tube is connected with the power supply, and the source electrode of the fourth NLDMOS tube and the source electrode of the fifteenth NMOS tube are connected with the drain electrode of the sixteenth NMOS tube; the drain electrode of the fifteenth NMOS tube is connected with the power supply, and the grid electrode and the source electrode of the fifteenth NMOS tube are interconnected; the grid electrode of the sixteenth NMOS tube is connected with the output of the second short pulse generating circuit, and the source electrode of the sixteenth NMOS tube is grounded;
the connection point of the drain electrode of the third PMOS tube, the drain electrode of the fifth NMOS tube and the drain electrode of the seventh PMOS tube is a first output end; and the connection point of the drain electrode of the fourth PMOS tube, the drain electrode of the tenth PMOS tube and the drain electrode of the sixth NMOS tube is a second output end.
2. The level shift circuit suitable for GaN half-bridge gate driving of claim 1, wherein the first short pulse generation circuit comprises a first inverter, a second inverter, a third inverter, an AND gate and a capacitor, wherein the first inverter, the second inverter and the third inverter are connected in series in sequence, an input end of the first inverter is connected with the second input end, a connection point of the second inverter and the third inverter is grounded through the capacitor, one input end of the AND gate is connected with the second input end, the other input end of the AND gate is connected with an output end of the third inverter, and an output end of the AND gate is an output end of the first short pulse generation circuit; the second short pulse generating circuit has the same structure as the first short pulse generating circuit, except that the input of the second short pulse generating circuit is the first input terminal.
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| US11942942B1 (en) * | 2022-11-21 | 2024-03-26 | Hong Kong Applied Science and Technology Research Institute Company Limited | High-speed level-shifter for power-conversion applications |
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