CN113193865B - Level shift circuit suitable for GaN half-bridge grid drive - Google Patents

Abstract

The invention belongs to the technical field of power supplies, and particularly relates to a level shift circuit suitable for GaN half-bridge gate drive. The level shift circuit provided by the invention effectively avoids the limitation of a large voltage dynamic range on the LDMOS parasitic capacitor to the speed by a mode of the synergistic action of the active clamping level shift circuit controlled by the PWM signal and the acceleration module controlled by the short pulse, and realizes high-speed level conversion. Meanwhile, a node which is relatively low in the circuit and has large parasitic capacitance is separated from the output through the decoupling accelerating circuit, logic error overturn caused by charging and discharging of the parasitic capacitance relative to the ground is effectively avoided in the dV/dt conversion process, and the dV/dt noise suppression capability is improved.

Description

A level shift circuit suitable for GaN half-bridge gate drive

technical field

The invention belongs to the technical field of power supplies, and in particular relates to a level shift circuit suitable for driving a GaN half-bridge gate.

Background technique

Compared with Si MOSFET power devices, GaN power devices have smaller on-resistance and parasitic capacitance, and have been considered as a good solution for miniaturizing power systems. As the core module in the GaN half-bridge gate driver circuit, the speed of the level shift circuit and the ability to resist the dV/dt interference of the floating power rail directly determine the operating frequency and reliability of the GaN half-bridge gate driver circuit. GaN gate driver circuits usually have switching frequencies as high as several MHz to several tens of MHz, which makes the propagation delay of GaN gate driver circuits as low as tens of nanoseconds. Due to the extremely low parasitic capacitance of GaN power devices, the switching speed of GaN half-bridge switching nodes can reach 200V/ns or even higher, and GaN gate drive circuits need to be able to operate reliably at such high switching node switching speeds. Therefore, the extremely low propagation delay and extremely high switching speed of floating power rails of GaN half-bridge gate driver circuits require a level-shift circuit with both high speed and high dV/dt immunity to floating power rails.

In the GaN half-bridge gate driver shown in Figure 1, the level shift circuit usually uses NLDMOS as the bridge between the low-voltage domain and the high-voltage domain to realize the conversion of the signal from the low-voltage domain to the high-voltage domain. In the high-voltage BCD process or the high-voltage CMOS process, the parasitic capacitance CP between the NLDMOS drain and the substrate and the large voltage dynamic range on CP are the limiting factors for the speed of the level-shift circuit. During the switching process of the switch node, the high-side floating power supply VHB will generate the charge and discharge current IP to the CP, and IP will generate undershoot or overshoot at the output after flowing through the output impedance of the level shift circuit. When the dV/dt of the switch node is high, the IP is large, and the undershoot and overshoot will touch the inversion threshold of the logic circuit of the later stage, causing the GaN power tube to be turned on or turned off by mistake, causing system failure.

SUMMARY OF THE INVENTION

The purpose of the present invention: in view of the limitation of the parasitic capacitance between the drain of the NLDMOS transistor and the substrate on the circuit transmission speed and the ability to resist dV/dt interference in the above-mentioned level shift circuit, to propose a GaN half-bridge gate drive circuit that is suitable for The level shift circuit with high speed and high resistance to dV/dt interference can achieve low transmission delay and high resistance to dV/dt interference at the same time. harsh requirements. Its circuit structure includes an active clamp level shift circuit, an acceleration module and a short pulse generating circuit.

The technical scheme of the present invention is:

A level shift circuit suitable for GaN half-bridge gate drive, as shown in Figure 2, includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, and a sixth PMOS tube tube, seventh PMOS tube, eighth PMOS tube, ninth PMOS tube, tenth PMOS tube, first NOMS tube, second NOMS tube, third NOMS tube, fourth NOMS tube, fifth NOMS tube, sixth NOMS tube tube, seventh NOMS tube, eighth NOMS tube, ninth NOMS tube, tenth NOMS tube, eleventh NOMS tube, twelfth NOMS tube, thirteenth NOMS tube, fourteenth NOMS tube, fifteenth NMOS tube tube, sixteenth NMOS tube, first PLDMOS tube, second PLDMOS tube, first NLDMOS tube, second NLDMOS tube, third NLDMOS tube, fourth NLDMOS tube, first resistor, second resistor, third resistor, a fourth resistor, a first short-pulse generating circuit, a second short-pulse generating circuit and a NOT gate; wherein,

The source of the first PMOS transistor is connected to the power supply, and the gate thereof is connected to the first input terminal; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, the gate of the first NMOS transistor is connected to the first input terminal, and the first NMOS transistor is connected to the first input terminal. The source of the NMOS tube is grounded;

The source of the second PMOS transistor is connected to the power supply, and the gate is connected to the second input terminal; the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, the gate of the second NMOS transistor is connected to the second input terminal, and the second NMOS transistor is connected to the second input terminal. The source of the NMOS tube is grounded;

The connection point of the gate of the first PMOS tube and the gate of the first NMOS tube is connected to the input end of the NOT gate, and the output end of the NOT gate is connected to the connection point of the gate of the second PMOS tube and the gate of the second NMOS tube;

The source of the third PMOS transistor is connected to the high-side floating power supply, and its gate is connected to the drain of the fourth PMOS transistor through the fourth resistor; the source of the fourth PMOS transistor is connected to the high-side floating power supply, and its gate is connected to the third resistor followed by the drain of the third PMOS transistor;

The drain of the third NMOS transistor is connected to the drain of the third PMOS transistor through the third resistor, the gate of the third NMOS transistor is connected to the drain of the fourth PMOS transistor through the fourth resistor, and the source of the third NMOS transistor is connected to High-side floating ground; the drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor through the fourth resistor, the gate of the fourth NMOS transistor is connected to the drain of the third PMOS transistor through the third resistor, and the fourth NMOS transistor is connected to the drain of the third PMOS transistor through the third resistor. The source of the tube is connected to the high-side floating ground;

The drain of the fifth NMOS tube is connected to the drain of the third PMOS tube, the gate of the fifth NMOS tube is connected to the drain of the fourth PMOS tube through the fourth resistor, and the source of the fifth NMOS tube is connected to the high-side floating ground; The drain of the sixth NMOS tube is connected to the drain of the fourth PMOS tube, the gate of the sixth NMOS tube is connected to the drain of the third PMOS tube through the third resistor, and the source of the sixth NMOS tube is connected to the high-side floating ground;

The drain of the seventh NMOS transistor is connected to the drain of the third PMOS transistor through the third resistor, and the gate and drain of the seventh NMOS transistor are both connected to the high-side floating ground; the drain of the eighth NMOS transistor passes through the fourth resistor. The drain of the fourth PMOS transistor is connected, and the gate and drain of the eighth NMOS transistor are both connected to the high-side floating ground;

One end of the first resistor is connected to the drain of the seventh NMOS transistor, and the other end of the first resistor is connected to the high-side floating ground; the source of the first PLDMOS transistor is connected to one end of the first resistor, and the gate of the first PLDMOS transistor is connected to the high side Floating ground; the drain of the first NLDMOS transistor is connected to the drain of the first PLDMOS transistor, the gate of the first NLDMOS transistor is connected to the power supply, the source of the first NLDMOS transistor and the source of the ninth NMOS transistor are connected to the first NMOS transistor Drain; the drain of the ninth NMOS transistor is connected to the power supply, and its gate and source are interconnected;

One end of the second resistor is connected to the high-side floating power supply, and the other end of the second resistor is connected to the drain of the eighth NMOS transistor;

The source of the second PLDMOS transistor is connected to the drain of the eighth NMOS transistor, the gate of the second PLDMOS transistor is connected to the high-side floating ground; the drain of the second NLDMOS transistor is connected to the drain of the second PLDMOS transistor, and the drain of the second NLDMOS transistor is connected to the drain of the second PLDMOS transistor. The gate is connected to the power supply, the source of the second NLDMOS tube and the source of the tenth NMOS tube are connected to the drain of the second NMOS tube; the drain of the tenth NMOS tube is connected to the power supply, and the gate and the source are interconnected;

The source of the fifth PMOS tube is connected to the high-side floating power supply, and its gate is interconnected with the drain; the source of the sixth PMOS tube is connected to the high-side floating power supply, and its gate is connected to the drain of the fifth PMOS tube, and the sixth PMOS tube is connected to the drain of the fifth PMOS tube. The drain of the tube is connected to the source of the first PLDMOS tube; the source of the seventh PMOS tube is connected to the high-side floating power supply, its gate is connected to the drain of the fifth PMOS tube, and the drain of the seventh PMOS tube is connected to the third PMOS tube the drain;

The drain of the eleventh NMOS transistor is connected to the drain of the fifth PMOS transistor, and the gate and source of the eleventh NMOS transistor are both connected to the high-side floating ground;

The drain of the third NLDMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the third NLDMOS transistor is connected to the power supply, the source of the third NLDMOS transistor and the source of the twelfth NMOS transistor are connected to the drain of the thirteenth NMOS transistor ; The drain of the twelfth NMOS tube is connected to the power supply, and its gate and source are interconnected; the gate of the thirteenth NMOS tube is connected to the output of the first short-pulse generating circuit, and the source of the thirteenth NMOS tube is grounded;

The source of the eighth PMOS tube is connected to the high-side floating power supply, and its gate is interconnected with the drain; the source of the ninth PMOS tube is connected to the high-side floating power supply, and its gate is connected to the drain of the eighth PMOS tube, and the ninth PMOS tube is connected to the drain of the eighth PMOS tube. The drain of the tube is connected to the source of the second PLDMOS tube; the source of the tenth PMOS tube is connected to the high-side floating power supply, its gate is connected to the drain of the eighth PMOS tube, and the drain of the tenth PMOS tube is connected to the fourth PMOS tube the drain;

The drain of the fourteenth NMOS transistor is connected to the drain of the eighth PMOS transistor, and the gate and source of the fourteenth NMOS transistor are both connected to the high-side floating ground;

The drain of the fourth NLDMOS transistor is connected to the drain of the eighth PMOS transistor, the gate of the fourth NLDMOS transistor is connected to the power supply, the source of the fourth NLDMOS transistor and the source of the fifteenth NMOS transistor are connected to the drain of the sixteenth NMOS transistor ; The drain of the fifteenth NMOS tube is connected to the power supply, and its gate and source are interconnected; the gate of the sixteenth NMOS tube is connected to the output of the second short pulse generating circuit, and the source of the sixteenth NMOS tube is grounded;

The connection point of the drain of the third PMOS transistor, the drain of the fifth NMOS transistor and the drain of the seventh PMOS transistor is the first output end; the connection point of the drain of the fourth PMOS transistor, the drain of the tenth PMOS transistor and the sixth NMOS transistor for the second output.

Further, the first short pulse generating circuit includes a first inverter, a second inverter, a third inverter, an AND gate and a capacitor, wherein the first inverter, the second inverter and the first inverter The three inverters are connected in series in sequence, the input terminal of the first inverter is connected to the second input terminal, the connection point between the second inverter and the third inverter is grounded through a capacitor, and one input terminal of the AND gate is connected to the second input terminal The input end, the other input end of the AND gate is connected to the output end of the third inverter, and the output end of the AND gate is the output end of the first short pulse generating circuit; the structure of the second short pulse generating circuit is the same as that of the first short pulse generating circuit. The structure of the circuit is the same, the difference is that the input of the second short pulse generating circuit is the first input terminal.

The beneficial effects of the present invention are: in the dV/dt conversion process, the resistance decoupling latch is used to separate the node with large parasitic capacitance relative to the substrate and the output node, and the decoupling acceleration circuit maintains the output logic state unchanged. The influence of the parasitic current caused by dV/dt on the output is completely blocked, and the anti-dV/dt capability of the level shift circuit is no longer limited by the parasitic capacitance relative to the substrate in the LDMOS and the on-resistance of the charging and discharging path of the parasitic capacitance , the resistance to dV/dt has been significantly improved. The acceleration module and the active clamp level shift circuit work together to eliminate the limitation of the circuit speed due to the large voltage dynamic range on the parasitic capacitance between the LDMOS drain terminal and the substrate, and realize high-speed signal transmission.

Description of drawings

Figure 1 Schematic diagram of the parasitic capacitance of the NLDMOS relative to the substrate limiting the GaN gate drive delay and the ability to resist dV/dt in the level shift circuit.

FIG. 2 is a circuit structure diagram of a level shift circuit with high speed and high dV/dt suppression capability proposed by the present invention, which is suitable for GaN gate driving.

FIG. 3 is a working waveform diagram of a high-speed and high-dV/dt suppression level shift circuit proposed by the present invention, which is suitable for GaN gate driving.

FIG. 4 is a working principle diagram of a high-speed and high dV/dt suppression capability level shift circuit suitable for GaN gate drive proposed by the present invention in the dV/dt conversion process of the floating power rail, wherein (a) is the working principle diagram, (b) is the working waveform diagram during the conversion process.

FIG. 5 is a simulation schematic diagram of a high-speed and high-dV/dt-rejection level-shift circuit suitable for GaN gate drive proposed by the present invention during the dV/dt conversion process of the floating power rail.

Detailed ways

Below in conjunction with accompanying drawing, the technical scheme of the present invention is described in detail:

FIG. 2 shows the circuit structure of the level shift circuit of the present invention. The circuit is composed of active clamp level shift circuit, acceleration module and short pulse generation circuit. Resistive decoupling latches are included in the active-clamp level-shift circuit. The resistive decoupling latch and the acceleration module constitute a decoupling acceleration circuit.

In the resistive decoupling latch, a resistor is used to separate the _PLDMOS source terminal and output terminal with relatively large parasitic capacitance, and block the parasitic current caused by the dV/dt conversion of the high-side floating power supply ground VSW to the output logic. status effect. The acceleration module charges and discharges the parasitic capacitance relative to the ground in the active clamp level shift circuit during the dV/dt conversion of the floating power rail.

The acceleration module is also used to increase the transmission speed of the active clamp level shift circuit. The low-speed active clamp level shift circuit is controlled by the input PWM signal, and the high-speed acceleration module is controlled by short pulses. When the signal transmission between the power rails occurs, the two work together to quickly change the output state to achieve high-speed signal transmission. . The active clamp level shift circuit is used to establish and maintain the output state, and the acceleration module is used to establish the output state.

FIG. 2 shows a circuit structure diagram of a level shift circuit with high speed and high dV/dt suppression capability proposed by the present invention, which is suitable for GaN gate driving. NLDMOS transistors M5, M6, M17, M18 and PLDMOS transistors M7, M8 are used to withstand high voltage. The input tubes M1, M2, M3, M4, M15, and M16 are low-voltage non-isolated MOSFETs. The M3 and M4 tubes are used to quickly turn off the M5 and M6 tubes, thereby increasing the rising speed of the nodes N5 and N6. MD1, MD2, MD3 and MD4 are low-voltage isolated NMOS transistors with gate-source short-circuiting, and their body diodes are used to clamp the drain node of the input transistor to avoid breakdown of the gate oxide of the input transistor. The shaded devices are low-voltage isolated transistors and resistors placed in isolated deep N-wells. The body diodes of transistors MD5, MD6, MD7 and MD8 are used to charge the parasitic capacitances at nodes N1, N2, N3 and N4 with respect to ground and to protect the gate oxides of the low voltage isolated transistors. The resistive decoupling latch consists of resistors R3, R4 and transistors M9, M10, M11, M12, M13, M14, R3 and R4 separate nodes N1, N2 from V _OUT , V _OUT- , respectively, floating power rail dV/dt The effect of noise on the output can be effectively shielded. Transistors M13 and M14 are used to quickly pull down V _OUT and V _OUT- . Resistors R1 and R2 are initialization resistors for the resistive decoupling latch.

The specific working waveform of the circuit is shown in Figure 3. The active clamp circuit is controlled by the gate drive input PWM signal, and the acceleration module is controlled by the short pulse generated by the PWM signal through the short pulse generation circuit. The circuit work is divided into two stages: output state establishment and output state maintenance. In the process of establishing the output state, when V _IN turns from low to high, the pull-down path formed by the transistors M ₁ , M ₅ and M ₇ generates a pull-down current I _down acting on the node N1 . After V _IN passes through the short-pulse generating circuit, V _P1 turns from low to high. At this time, the acceleration module is turned on, and the current mirror generates pull-up currents I _up1 and I _up acting on V _OUT- and node N2 respectively. Under the combined action of I _up1 , I _up and I _down , the output state of the resistive decoupling latch can be quickly flipped. When the high level duration of the short pulse signal V _P1 ends, the acceleration module is turned off, I _up1 and I _up are reduced to zero, and the circuit enters the output state maintenance stage, which is only maintained by the active clamp level shift circuit. The output state remains unchanged, and no quiescent current is generated. In the same way, the V _IN - control level shift circuit output produces a state that is the opposite of the logic state produced by the V _IN control.

When the acceleration module is turned off, it is necessary to ensure that the active clamp level shift circuit can be turned over to its equilibrium state under the action of the input PWM signal. When the active clamp level shift circuit is in a balanced state, as shown in Figure 2, the potentials of nodes N1 and N2 are equal, the potentials of V _OUT and V _OUT- are equal, and the potential of nodes N5 or N6 rises slowly. R ₃ and R ₄ enable the active clamp level shift circuit to flip the output V _OUT or V _OUT- close to V _HB with a small pull-down current I _down . When V _OUT - V _SW and V _N1 - V _SW are logic high, V _OUT - - V _SW and V _N2 - V _SW are logic low, and I _down pulls down the N1 node and V _OUT , it is assumed that the gate-source voltage of the _M7 transistor is V, the inversion threshold of the inverter composed of M ₁₂ tube, R ₄ and M ₁₀ is V _T1 , the inversion threshold of the inverter composed of M ₁₂ and M ₁₄ is V _T2 , V _HB and V _SW voltage difference is V _DDH , the value of R ₃ and R ₄ is R _dec . In order to ensure that the pull-down current I _down can break the latched state of the resistive decoupling inverter, the following formula holds:

V<V _T1 <V _T2 (1)

Among them, V _{thn and V thpd represent} the threshold voltages of low-voltage NMOS transistors and PLDMOS transistors, respectively. According to (1)-(3), R _dec needs to satisfy:

As shown in Fig. 3, let T ₀ be the transmission delay of the short pulse generating circuit, T ₁ be the delay from the startup of the acceleration module to the generation of the pull-up currents I _up1 and I _up , and T ₂ is the pull-up current generated to the node N2 The delay time for the voltage V _N2 to turn high, T3 is the time delay for V _N2 to turn high to V _{OUT -} V _SW to turn low. The transmission delay _TDF of the output falling edge of the level shift circuit is expressed as:

T _DF =T ₀ +T ₁ +T ₂ +T ₃ (5)

Let the propagation delay of the input inverter be T ₅ , since the parasitic capacitance of V _OUT relative to V _SW is smaller than the parasitic capacitance of node N1 or N2, the propagation delay from _VP2 high to V _OUT - V _SW high is less than T ₁ +T ₂ . The transmission delay T _DR of the output rising edge of the level shift circuit is expressed as:

T _DR < T ₅ +T ₀ +T ₁ +T ₂ (6)

T ₃ is determined by the positive feedback capability of the resistive decoupling latch, and T ₃ ≈ T ₅ . Therefore, the rising edge propagation delay of the level shift circuit is smaller than the falling edge propagation delay.

As shown in Figure 3, in the process of output V _OUT - V _SW turning low, when V _N2 is pulled up to close to V _HB by I _up , the output state of the level shift circuit is established. At this time, the M ₈ tube in the saturation region charges the parasitic capacitance C _N6 of the node N6. When the potential V _N6 of the node N6 is close to V _HB , the M ₈ tube enters the deep linear region, and the active clamp level shift circuit completes the state transition . _The time T4 for _VN6 to rise from GND to _VHB is:

Wherein L _pd is the fixed channel length of PLDMOS in the high voltage CMOS process, W _nd and W _pd are the channel widths of NLDMOS transistors M ₆ , M ₅ and PLDMOS transistors M ₈ , M ₇ respectively, K ₁ , K ₂ and K ₃ is a process-dependent constant. The pulse widths of V _p1 and V _p2 T _p ≧ T ₁ +T ₂ +T ₄ , because T ₁ and T ₂ are much smaller than T ₄ , the minimum short pulse width is determined by T ₄ , according to equation (7), M ₆ and M The ₅ -tube adopts the minimum channel width and increases the channel width of the _M8 tube and the _M7 tube, which is beneficial to reduce the short pulse width, thereby reducing the power consumption of the circuit. Therefore, the selection of the channel widths of the PLDMOS transistors M ₇ and M ₈ has a trade-off between power consumption and layout area.

Figures 4(a) and 4(b) show the operation principle and waveform diagrams of the decoupling acceleration circuit during positive and negative dV/dt transitions of the floating power rail. Before a positive dV/dt transition, V _OUT - V _SW and V _N1 - V _SW are logic high and V _OUT - - V _SW and V _N2 - V _SW are logic low. When the positive dV/dt slew rate of the floating power rail is high, at node N3, the body diode of _MD5 and _M19 charge the parasitic capacitance C _N3 of node N3 relative to the substrate, and at node N4, the parasitic capacitance of _MD6 tube The body diode and M ₂₀ charge the parasitic capacitance CN4 of node _N4 with respect to the substrate. At the node N1, the parasitic charging current I _P1 generated by the M ₂₁ tube is not enough to fully provide the charging current of the parasitic capacitance C _N1 of the N1 relative to the substrate. At this time, the body diode of the _MD7 tube and the transistors M ₂₁ , M ₁₁ , M ₂₃ collectively charges C _N1 and V _N1 - V _SW goes to a logic low level. Symmetrically, at node N2, the body diode of _MD8 and transistors M ₂₂ , M ₁₂ , and M ₂₄ jointly charge _{CN2, and V N2 -V SW} remains logic low. The on-resistances of R _dec and M ₁₁ (M ₁₂ ) and M ₂₃ (M ₂₄ ) determine the potentials of V _OUT and V _OUT- . To ensure that V _OUT - V _SW remains at a logic high level, R _dec needs to satisfy:

Wherein R ₁₁ and R ₂₃ represent the on-resistance of M ₁₁ (M ₁₂ ) and M ₂₃ (M ₂₄ ) respectively, VT is the switching threshold of the logic circuit of the subsequent stage, and _{V D is} the forward voltage drop of the body diode. Due to circuit symmetry, while _VOUT - _VSW remains logic high, _VOUT -- _VSW also goes logic high. When the dV/dt conversion process is over, as shown in Figure 4(b), due to the current mirror bandwidth limitation, transistors _M21 - _M24 will not be turned off immediately, _M21 and _M22 charge _CN1 and _CN2 , respectively, V _N1 -V _SW and V _N2 - V _SW will be higher than V _T2 , M ₂₃ and M ₂₄ prevent V _OUT - V _SW and V _OUT- - V _SW from changing to logic low. When the gate-source voltage of M ₂₁ -M ₂₄ gradually decreases, V _N1 -V _SW and V _N2 -V _SW gradually drop below V _T2 , at this time the active clamp level shift circuit enters into a balanced state, V _OUT - V _SW and V _OUT- -V _SW remain logic high, _M7 tube charges the parasitic capacitance C _N5 of node N5 relative to the substrate, when _M7 enters the deep linear region, V _N1 -V _SW rises above V _T2 , V _OUT- -V _SW returns to logic high.

Before a negative dV/dt transition, V _OUT - V _SW and V _N1 - V _SW go logic low, and V _OUT - - V _SW and V _N2 - V _SW go logic high. When the negative dV/dt slew rate of the floating rail is high, at nodes _N3 and _N4 , CN3 and CN4 discharge to V _HB through _the body diodes of M19 and _M20 transistors, respectively. At node _N1 , the discharge current I _P3 of CN1 is very large, _CN3 discharges through the body diode of _M21 , the series path formed by _M9 tube and resistor _R3 , _M13 tube, _VN1 - _VSW becomes logic high level. At node _N2 , _CN2 discharges through the body diode of _M22 , the series path formed by _M10 tube and resistors R4 and _M14 tubes, and _VN2 - _VSW remains at a logic high level. To ensure that V _OUT - V _SW remains at a logic low level, R _dec needs to satisfy:

Wherein R ₁₃ is the on-resistance of the transistors M ₁₃ and M ₁₄ . While _VOUT - _VSW remains logic low, _VOUT -- _VSW also goes logic low. After the negative dV/dt transition, V _N1 - V _SW returns to logic low and V _OUT - - V _SW returns to logic high under the action of M ₇ and the resistive decoupling latch. Combining the three equations (4), (8) and (9), the decoupling resistance value R _dec needs to meet:

R _dec(min) >max[R _dec1 ,R _dec2 ,R _dec3 ] (10)

When the positive dV/dt switching speed of the floating power rail is low, at node N1, M ₂₁ can provide sufficient charging current for _CN1 and _CN5 , and V _N1 - V _SW is higher than V _T2 . At node N2, the dV/dt parasitic current in the _M22 tube charges C _N2 , and the residual current flows through the on-resistance of the _M10 tube. The dV/dt parasitic current in the _M24 tube flows through the on-resistance of the _M14 tube. Due to the small dV/dt, the dV/dt parasitic currents in M ₂₂ and M ₂₄ are small, V _OUT- -V _SW remains logic low, V _N2 -V _SW is lower than V _T2 , V _OUT - V _SW held at a logic high level. When the negative dV/dt switching speed of the floating rail is low, at node _N2 , CN2 discharges primarily through the body diode of M ₂₂ , and V _N2 - V _SW is higher than V _DDH . At the node _N1 , the discharge current _IP3 of CN1 flows through the on-resistance of the _M9 tube, the on-resistance of the resistor _R3 and the _M13 tube. Because the negative dV/dt slew rate is lower and I _P3 is smaller, V _OUT - V _SW remains logic low, V _N1 - V _SW is lower than V _T2 , and V _OUT - - V _SW remains logic high.

According to the above discussion, when dV/dt switching occurs on the floating power rail, if the level of the input signal of the circuit is fixed and the decoupling resistor value R _dec satisfies Equation (10), V _OUT - V _SW can be at any positive dV/dt Maintaining a logic high level during the conversion process and maintaining a logic low level during any negative dV/dt conversion process, the dV/dt resistance of the level shift circuit can theoretically reach infinity. However, the dV/dt resistance of a practical circuit is limited by the current capability of the transistor body diode, that is, by the area of the body diode.

FIG. 5 is a simulation result diagram of the level shift circuit proposed by the present invention when the switching speed of the floating power rail is 300V/ns. When the floating power rail ramps up at a switching speed of 300V/ns, the undershoot of the output voltage is 0.69V, and no logical state false inversion occurs. When the floating power rail drops at a switching speed of 300V/ns, the overshoot of the output voltage is 0.38V, and there is also no false logic state inversion.

To sum up, the level shift circuit proposed by the present invention effectively avoids the large voltage dynamic range on the parasitic capacitance of LDMOS by the synergistic effect of the active clamp level shift circuit controlled by the PWM signal and the acceleration module controlled by the short pulse. The speed limit realizes high-speed level translation. At the same time, the relatively low node with large parasitic capacitance in the circuit is separated from the output through the decoupling acceleration circuit, which effectively avoids the false logic inversion caused by the charging and discharging of the parasitic capacitance relative to the ground during the dV/dt conversion process, and improves the dV/dt conversion process. dt noise rejection capability.

Claims (2)

1. A level shift circuit suitable for GaN half-bridge gate drive, characterized in that it comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube tube, seventh PMOS tube, eighth PMOS tube, ninth PMOS tube, tenth PMOS tube, first NOMS tube, second NOMS tube, third NOMS tube, fourth NOMS tube, fifth NOMS tube, sixth NOMS tube tube, seventh NOMS tube, eighth NOMS tube, ninth NOMS tube, tenth NOMS tube, eleventh NOMS tube, twelfth NOMS tube, thirteenth NOMS tube, fourteenth NOMS tube, fifteenth NMOS tube tube, sixteenth NMOS tube, first PLDMOS tube, second PLDMOS tube, first NLDMOS tube, second NLDMOS tube, third NLDMOS tube, fourth NLDMOS tube, first resistor, second resistor, third resistor, a fourth resistor, a first short-pulse generating circuit, a second short-pulse generating circuit and a NOT gate; wherein, The source of the first PMOS transistor is connected to the power supply, and the gate thereof is connected to the first input terminal; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, the gate of the first NMOS transistor is connected to the first input terminal, and the first NMOS transistor is connected to the first input terminal. The source of the NMOS tube is grounded; The source of the second PMOS transistor is connected to the power supply, and the gate is connected to the second input terminal; the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, the gate of the second NMOS transistor is connected to the second input terminal, and the second NMOS transistor is connected to the second input terminal. The source of the NMOS tube is grounded; The connection point of the gate of the first PMOS tube and the gate of the first NMOS tube is connected to the input end of the NOT gate, and the output end of the NOT gate is connected to the connection point of the gate of the second PMOS tube and the gate of the second NMOS tube; The source of the third PMOS transistor is connected to the high-side floating power supply, and its gate is connected to the drain of the fourth PMOS transistor through the fourth resistor; the source of the fourth PMOS transistor is connected to the high-side floating power supply, and its gate is connected to the third resistor followed by the drain of the third PMOS transistor; The drain of the third NMOS transistor is connected to the drain of the third PMOS transistor through the third resistor, the gate of the third NMOS transistor is connected to the drain of the fourth PMOS transistor through the fourth resistor, and the source of the third NMOS transistor is connected to High-side floating ground; the drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor through the fourth resistor, the gate of the fourth NMOS transistor is connected to the drain of the third PMOS transistor through the third resistor, and the fourth NMOS transistor is connected to the drain of the third PMOS transistor through the third resistor. The source of the tube is connected to the high-side floating ground; The drain of the fifth NMOS tube is connected to the drain of the third PMOS tube, the gate of the fifth NMOS tube is connected to the drain of the fourth PMOS tube through the fourth resistor, and the source of the fifth NMOS tube is connected to the high-side floating ground; The drain of the sixth NMOS tube is connected to the drain of the fourth PMOS tube, the gate of the sixth NMOS tube is connected to the drain of the third PMOS tube through the third resistor, and the source of the sixth NMOS tube is connected to the high-side floating ground; The drain of the seventh NMOS transistor is connected to the drain of the third PMOS transistor through the third resistor, and the gate and drain of the seventh NMOS transistor are both connected to the high-side floating ground; the drain of the eighth NMOS transistor passes through the fourth resistor. The drain of the fourth PMOS transistor is connected, and the gate and drain of the eighth NMOS transistor are both connected to the high-side floating ground; One end of the first resistor is connected to the drain of the seventh NMOS transistor, and the other end of the first resistor is connected to the high-side floating ground; the source of the first PLDMOS transistor is connected to one end of the first resistor, and the gate of the first PLDMOS transistor is connected to the high side Floating ground; the drain of the first NLDMOS transistor is connected to the drain of the first PLDMOS transistor, the gate of the first NLDMOS transistor is connected to the power supply, the source of the first NLDMOS transistor and the source of the ninth NMOS transistor are connected to the first NMOS transistor Drain; the drain of the ninth NMOS transistor is connected to the power supply, and its gate and source are interconnected; One end of the second resistor is connected to the high-side floating power supply, and the other end of the second resistor is connected to the drain of the eighth NMOS transistor; The source of the second PLDMOS transistor is connected to the drain of the eighth NMOS transistor, the gate of the second PLDMOS transistor is connected to the high-side floating ground; the drain of the second NLDMOS transistor is connected to the drain of the second PLDMOS transistor, and the drain of the second NLDMOS transistor is connected to the drain of the second PLDMOS transistor. The gate is connected to the power supply, the source of the second NLDMOS tube and the source of the tenth NMOS tube are connected to the drain of the second NMOS tube; the drain of the tenth NMOS tube is connected to the power supply, and the gate and the source are interconnected; The source of the fifth PMOS tube is connected to the high-side floating power supply, and its gate is interconnected with the drain; the source of the sixth PMOS tube is connected to the high-side floating power supply, and its gate is connected to the drain of the fifth PMOS tube, and the sixth PMOS tube is connected to the drain of the fifth PMOS tube. The drain of the tube is connected to the source of the first PLDMOS tube; the source of the seventh PMOS tube is connected to the high-side floating power supply, its gate is connected to the drain of the fifth PMOS tube, and the drain of the seventh PMOS tube is connected to the third PMOS tube the drain; The drain of the eleventh NMOS transistor is connected to the drain of the fifth PMOS transistor, and the gate and source of the eleventh NMOS transistor are both connected to the high-side floating ground; The drain of the third NLDMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the third NLDMOS transistor is connected to the power supply, the source of the third NLDMOS transistor and the source of the twelfth NMOS transistor are connected to the drain of the thirteenth NMOS transistor ; The drain of the twelfth NMOS tube is connected to the power supply, and its gate and source are interconnected; the gate of the thirteenth NMOS tube is connected to the output of the first short-pulse generating circuit, and the source of the thirteenth NMOS tube is grounded; The source of the eighth PMOS tube is connected to the high-side floating power supply, and its gate is interconnected with the drain; the source of the ninth PMOS tube is connected to the high-side floating power supply, and its gate is connected to the drain of the eighth PMOS tube, and the ninth PMOS tube is connected to the drain of the eighth PMOS tube. The drain of the tube is connected to the source of the second PLDMOS tube; the source of the tenth PMOS tube is connected to the high-side floating power supply, its gate is connected to the drain of the eighth PMOS tube, and the drain of the tenth PMOS tube is connected to the fourth PMOS tube the drain; The drain of the fourteenth NMOS transistor is connected to the drain of the eighth PMOS transistor, and the gate and source of the fourteenth NMOS transistor are both connected to the high-side floating ground; The drain of the fourth NLDMOS transistor is connected to the drain of the eighth PMOS transistor, the gate of the fourth NLDMOS transistor is connected to the power supply, the source of the fourth NLDMOS transistor and the source of the fifteenth NMOS transistor are connected to the drain of the sixteenth NMOS transistor ; The drain of the fifteenth NMOS tube is connected to the power supply, and its gate and source are interconnected; the gate of the sixteenth NMOS tube is connected to the output of the second short pulse generating circuit, and the source of the sixteenth NMOS tube is grounded; The connection point of the drain of the third PMOS transistor, the drain of the fifth NMOS transistor and the drain of the seventh PMOS transistor is the first output end; the drain of the fourth PMOS transistor, the drain of the tenth PMOS transistor and the drain of the sixth NMOS transistor The connection point is the second output. 2 . A level shift circuit suitable for driving GaN half-bridge gates according to claim 1 , wherein the first short pulse generating circuit comprises a first inverter, a second inverter, a first Three inverters, AND gates and capacitors, wherein the first inverter, the second inverter and the third inverter are connected in series in sequence, the input end of the first inverter is connected to the second input end, the second inverter The connection point between the inverter and the third inverter is grounded through a capacitor, one input of the AND gate is connected to the second input, the other input of the AND gate is connected to the output of the third inverter, and the output of the AND gate is connected to the ground. is the output terminal of the first short pulse generating circuit; the structure of the second short pulse generating circuit is the same as that of the first short pulse generating circuit, except that the input of the second short pulse generating circuit is the first input terminal.

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