JPH06109780A - Comparator circuit - Google Patents

Abstract

PURPOSE:To maintain sufficient hysteresis even for the time of a collector voltage rise delayed due to capacity incident to the collector of a transistor, regarding a comparator circuit having hysteresis. CONSTITUTION:A transistor Q6 having the same phase as an output transistor Q5, and another transistor Q7 having a phase opposite to the phase of the transistor Q5, are connected for positive feedback to both input terminals of differential amplification circuits Ql, Q2, Q3 and Q4. As a result, one of the transistors Q6 and Q7 is sure to change from interrupted state to continuous state under threshold voltage, and sufficient hysteresis can be thereby maintained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator circuit having hysteresis.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a conventional comparison circuit. Q
11, Q12, Q13, Q14, Q15, Q16 are transistors, R11, R12, R13, R14, R15,
R16 is a resistor, I11 is a current source, V11 is a voltage source, IN
11 is an inverting input terminal, IN12 is a non-inverting input terminal, OU
T11 is an output terminal, and GND11 is a ground terminal.

The operation of the circuit shown in FIG. 2 will be briefly described. Assuming that the transistors Q11 and Q12 and the transistors Q13, Q14, Q15 and Q16 have the same element characteristics, the transistors Q11, Q12, Q13, Q
A differential amplifier circuit is configured by 14. Therefore, the base potential VB11 of the transistor Q11 is
12 becomes lower than the base potential VB12, the transistors Q15 and Q16 are cut off and the output terminal OUT1
1 goes high.

On the other hand, the base potential V of the transistor Q11
When B11 becomes higher than the base potential VB12 of the transistor Q12, the transistors Q15 and Q16 become conductive and the output terminal OUT11 becomes low.

Base potential VB11 of transistor Q11
Is lower than the base potential VB12 of the transistor Q12, the threshold voltage condition is that the voltage of the inverting input terminal IN11 is VIN11 and the non-inverting input terminal IN1 is
When the voltage of 2 is represented by VIN12, the following equation (1) is obtained.

VIN11 × R16 / (R15 + R16) = VIN12 × R12 / (R11 + R12) Equation (1) The threshold voltage condition when the base potential VB11 of the transistor Q11 is higher than the base potential VB12 of the transistor Q12 is as follows: It is represented by 2).

VIN11 × R16 / (R15 + R16) = (VIN12−IC16 × R11) × R12 / (R11 + R12) Equation (2) (where IC16: collector current of the transistor Q16) From Equation (1) and Equation (2) Threshold voltage difference V
H11 is represented by the following equation (3).

VH11 = IC16 × R11 × R12 / (R11 + R12) Equation (3) From the equation (1), the equation (2), and the equation (3), the output terminal OUT1
The threshold voltage condition that 1 is in the low state from the high state is determined by the equation (1), the threshold voltage condition that the output terminal OUT11 is in the high state from the low state is determined by the equation (2), and the hysteresis width is expressed by the equation (3). ), It is possible to configure a comparison circuit determined by the threshold voltage difference VH11.

[0009]

However, in this conventional comparison circuit, parasitic capacitance C is generated in the collector of the transistor when the circuit is formed of an integrated circuit, and the rise time of the collector potential VC16 of the transistor Q16 is
When the collector potential VC16 of the transistor Q16 does not rise immediately after the output terminal OUT11 changes from the low state to the high state, the hysteresis is sufficient because the time constant of the resistors R11, R12, R13 and the parasitic capacitance C limits the hysteresis. There was a problem that the width could not be obtained.

Therefore, in view of the above-mentioned drawbacks, a technical object of the present invention is to provide a comparison circuit capable of ensuring a sufficient hysteresis even with respect to a delay in collector voltage rise time due to a collector parasitic capacitance of a transistor.

[0011]

According to the present invention, in a comparator circuit which produces a hysteresis by applying positive feedback to either one of an inverting input and a non-inverting input, the other input is also positive in phase opposite to the output. A comparison circuit is obtained which is characterized by applying feedback to create hysteresis. That is, the comparison circuit of the present invention is characterized in that a feedback circuit of opposite phase is provided for both the inverting input terminal and the non-inverting input terminal.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. As shown in FIG. 1, the emitter of the transistor Q1 is connected to the emitter of the transistor Q2. The collector of the transistor Q1 is connected to the collector of the transistor Q3, and also the transistors Q3, Q4, Q7.
Connected to the base of. The collector of the transistor Q2 is connected to the collector of the transistor Q4 and the bases of the transistors Q5 and Q6. The emitters of the transistors Q3, Q4, Q5, Q6, Q7 are connected to the ground terminal GND1.

An inverting input terminal IN1 is connected to the base of the transistor Q1 via a resistor R5. The base of the transistor Q1 is connected to the ground terminal GND1 via the resistor R6 and is also connected to the collector of the transistor Q7 via the resistor R7. The base of the transistor Q2 has a non-inverting input terminal IN1.
Are connected via a resistor R1. The base of the transistor Q2 is connected to the ground terminal GND1 via the resistor R2.
Is also connected to the collector of the transistor Q6 via the resistor R3.

A current source I1 and a voltage source V1 are connected in series between the bases of the transistors Q1 and Q2 and the ground terminal GND1. The current source I1 and the voltage source V1
The connection point between and is connected to the collector of the transistor Q5 via the resistor R5. The connection point between the resistor R4 and the collector of the transistor Q5 is connected to the output terminal OUT1.

Next, the operation of the embodiment shown in FIG. 1 will be described. Transistors Q1 and Q2 and transistors Q3 and Q4
And Q5, Q6 and Q7 have the same element characteristics,
Since the differential amplifier circuit is composed of the transistors Q1, Q2, Q3 and Q4, the base potential V of the transistor Q1 is
When B1 becomes lower than the base potential VB2 of the transistor Q2, the transistors Q5 and Q6 are cut off, the transistor Q7 becomes conductive, and the output terminal OUT1 becomes high.

When the base potential VB1 of the transistor Q1 becomes higher than the base potential VB2 of the transistor Q2, the transistors Q5 and Q6 become conductive and the transistor Q7.
The output is cut off and the output terminal OUT1 becomes low.

The threshold voltage condition when the base potential VB1 of the transistor Q1 is lower than the base potential VB2 of the transistor Q2 is expressed by the following equation (4) when the voltage VIN1 of the inverting input terminal IN1 and the voltage VIN2 of the non-inverting input terminal IN2 are used. Becomes

(VIN1-IC7 × R5) × R6 / (R5 + R6) = VIN2 × R2 / (R1 + R2) Equation (4) However, IC7: collector current of transistor Q7 base potential VB1 of transistor Q1 is transistor Q1
The threshold voltage condition when the potential is higher than the base potential VB2 of 2 is represented by the following equation (5).

VI N1 × R6 / (R5 + R6) = (VIN2-IC6 × R1) × R2 / (R1 + R2) Equation (5) where IC6 is the threshold current from the collector current equation (4) and equation (5) of the transistor Q6. Voltage difference VH1
Is expressed by the following equation (6).

VH1 = IC6 × R1 × R2 / (R1 + R2) + IC7 × R5 × R6 / (R5 + R6) Expression (6) From the expression (4), the expression (5), and the expression (6), the output terminal OUT1 is higher than the high state. The threshold voltage condition for the low state is determined by the equation (4), the threshold voltage condition for the output terminal OUT1 to be in the high state from the low state is determined by the equation (5), and the hysteresis width is the threshold voltage of the equation (6). A comparison circuit determined by the difference VH1 can be configured.

[0022]

As described above, in the comparison circuit of the present invention, the parasitic capacitance C is generated in the collector of the transistor, such as in the case of an integrated circuit, and the rise time of the collector potential VC6 of the transistor Q6 is set to the resistances R1 and R2. , R3
Even when limited by the time constant of the parasitic capacitance C, the transistor Q7 is turned on at the same time as the transistor Q6 is cut off, and the fall time of the base potential VB1 of the transistor Q1 is not limited. Therefore, the output terminal OUT1 is in a high state rather than a low state. Even if the collector potential VC6 of the transistor Q6 does not rise immediately after the change to, the transistor Q7 has an effect that a sufficient hysteresis width can be obtained.

Further, the NPN transistor of FIG.
Even in a circuit in which the transistors are used, the PNP transistors are used as NPN transistors, and the polarities of the current source and the voltage source are inverted, the same effect as described above can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional comparison circuit.

[Explanation of symbols]

Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q11,
Q12, Q13, Q14, Q15, Q16 Transistors R1, R2, R3, R4, R5, R6, R7, R11,
R12, R13, R14, R15, R16 Resistors I1, I11 Current sources V1, V11 Voltage sources IN1, IN11 Inversion input terminals IN2, IN12 Non-inversion input terminals OUT1, OUT11 Output terminals GND1, GND11 Ground terminals

Claims (1)

[Claims] 1. A comparator circuit for generating positive hysteresis by applying positive feedback to one of an inverting input and a non-inverting input, and generating positive hysteresis in the opposite phase to the output also for the other input. Characteristic comparison circuit.