JPS641785Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gain control amplifier circuit used in television receivers and the like.

In television receivers, monitor receivers, video tape recorders, etc., small signal amplification stages, such as AGC (automatic gain control) circuits and ACC (automatic chroma control) circuits, use a gain control amplifier circuit 1 as shown in Figure 1. , a level detector 2, and an integrator 3 are used. As the amplifier circuit 1, a cascode type amplifier with good high frequency characteristics is often used in order to obtain good control characteristics, and is generally configured as an integrated circuit as shown in FIG. That is, 20 and 21 are control input terminals to which a DC control voltage is applied from the outside (for example, the level detector 2), and 22 is a capacitor to which an input signal to be amplified is applied.
It is a signal input terminal led through _C1 . _Q1 , _Q2
are transistors forming a first differential pair, and Q ₃ and Q ₄ are transistors forming a second differential pair. The bases of the transistors Q ₁ and Q ₄ are connected to the control input terminal 20, and the bases of the transistors Q ₂ and Q ₃ are connected to the control input terminal 21. The collectors of transistors Q ₁ and Q ₃ are connected together and then connected to the power supply V _CC , and the collectors of transistors Q 2 and Q ₃ are connected to the power supply V CC .
The collectors of _Q4 are connected together and then connected to the power supply V _CC via a resistor R1. Further, the emitter connection point of the differential pair transistors Q ₁ and Q ₂ is connected to the collector of the transistor Q ₅ , the emitter of this transistor Q ₅ is grounded via the resistor R ₂ , and the base is connected to the signal input terminal 22. has been done. Furthermore, the emitter connection point of the differential pair transistors Q ₃ and Q ₄ is connected to the collector of a transistor Q ₆ , and the emitter of this transistor Q ₆ is grounded via a resistor _RA .

On the other hand, the collector common connection point of the transistors Q ₂ and Q ₄ is an emitter follower connection transistor.
The collector of this transistor Q ₇ is connected to the power supply V _CC , and the emitter is connected to the signal output terminal 24 and grounded via resistors R ₃ and R ₄ in _sequence . And this resistance R ₃ ,
The connection point of R ₄ is connected via a resistor R ₅ to the base of an emitter follower-connected transistor Q ₈ . The collector of this transistor _Q8 is the power supply
It is connected to V _CC and its emitter is grounded through resistor _R6 . Further, this emitter is connected to the base of the transistor _Q5 via a resistor R7 and to the base of the transistor _Q6 via a resistor R8. and the transistor
The base of _Q8 is grounded via an external terminal 25 and an external bypass capacitor _C2 .

In the above configuration, the input signal guided to the signal input terminal 22 is amplified by the transistor _Q5 ,
The collector outputs of transistors Q ₂ and Q ₄ are buffered and amplified by transistor Q ₇ and then output from output terminal 24 . Then, the voltage at the resistor connection point of the emitter circuit of transistor _Q7 is taken out and applied to the base of transistor _Q8 . in this case,
Since the bypass capacitor C2 is connected to this base, a DC voltage is applied to the base. The emitter voltage of the transistor Q ₈ is supplied to the bases of the transistors Q ₅ and Q ₆ , so that the signal input terminal 22 is subjected to DC feedback.

Also, differential pair transistors Q ₁ , Q ₂ , and Q ₃ ,
In Q ₄ , the respective currents I ₁ , I ₂ , I ₃ , and I ₄ change as shown in FIG. 3 in response to changes in the control input voltage V _C . In this case, the differential pair transistor Q ₁ ,
The values of the resistors R _{2 and} R _A are made equal in order to flow an equal current to the current source transistor Q ₅ of Q ₂ and the current source transistor Q ₆ of the differential pair transistors Q 3 and Q ₄ .

Therefore, in the circuit of FIG. 2, the DC voltage V _A at the signal input terminal 22 is derived as follows.

The base-emitter voltage of each transistor is
Assuming V _F , the emitter current of transistor _Q5 is
(V _A − V _F )/R ₂ . This emitter current is
Since the current flowing through the resistor R ₁ is equal to I ₂ + I ₄ , the base voltage of the transistor Q ₇ is given by V _CC −R ₁ ·(V _A −V _F )/R ₂ . Therefore, the current flowing through resistors R ₃ and R ₄ is V _CC −R ₁・(V _A −V _F )/R ₂ −V _F /R ₃ +R ₄ , so the base voltage of transistor Q ₈ is V _CC −R ₁・(V _A −V _F )/R ₂ −V _F /R ₃ +R ₄・R ₄ . Since the value obtained by subtracting the base-emitter voltage of transistor _Q8 from this voltage is equal to V _A , V _A =V _CC −R ₁・(V _A −V _F )/R ₂ −V _F /R ₃ +R ₄・R ₄ −V _F holds true.

Solving this equation for V _A , V _A = R ₄ / R ₃ + R ₄ V _CC - (1 + R ₄ / R ₃ + R ₄ - R ₁ / R ₂
×R ₄ /R ₃ +R ₄ )V _F /1+R ₁ /R ₂・R ₄ /R ₃ +R ₄ ...(1) holds true.

Furthermore, the maximum AC gain G is when all the signal current of the transistor _Q5 flows to _R1 via the transistor _Q2 , so G= _R1 / _R2 ...(2). As can be seen from the above equations (1) and (2), in order to increase the gain G, R1/ _R2 must be increased, and therefore the signal input end DC voltage V _A becomes small.

On the other hand, since the peak-to-peak value of the undistorted maximum permissible voltage Vinmax of the input signal is twice the level at which transistor _Q5 is cut off, it is given by the following equation.

Vinmax=2・(V _A −V _F ) …(3) As is clear from the above equations (1) to (3), the setting of R ₁ /R ₂ in order to increase V _A and increase Vinmax. , is contrary to the setting of R ₁ /R ₂ to increase G. Therefore, conventionally, gain G characteristics, maximum allowable input
One of the Vinmax characteristics (dynamic range) was sacrificed.

This idea was made in view of the above circumstances.
By making the resistances of the current sources of the two sets of differential pair transistors different from each other so as to have a predetermined relationship, the control input terminal DC voltage V _A at the maximum input signal can be made larger than before. The purpose of the present invention is to provide a gain control amplifier circuit in which both the gain G and the dynamic range can be set large.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In the present invention, the value of the resistor R _A is set to be two to three times the value of the resistor R ₂ (for example, R _A =2R ₂ ) in the circuit described above with reference to FIG. The reason for this is that in the circuit shown in Figure 2, the input signal level is small and the control input voltage
When V _C is the minimum (for example, -200mV), there is no problem even if the signal input terminal DC voltage V _A is small, but when the input signal becomes large and the control input voltage V _C is near the maximum, the signal input terminal DC voltage This is to increase the voltage V _A and deepen the bias of the transistor _Q5 . Since the base voltages of transistors Q ₅ and Q ₆ are the same, if the value of resistor R _A is made larger than R ₂ (e.g. R _A = 2R ₂ ), the voltage across resistor R _A increases as the voltage across resistor R ₂ increases. The voltage across it also increases. In this way, the value of V _A becomes large,
It is possible to increase the input amplitude until transistor _Q5 is cut off.

That is, when R _A =2R ₂ is set as described above in the circuit of FIG. 2, the signal input terminal DC voltage V _A ' at that time is derived as follows.

The emitter current of transistor _Q6 is (V _A ′−
V _F )/2R ₂ , where V _C is the maximum (for example,
+200mV), the emitter current is resistor R
It is almost equal to the current flowing through 1. Therefore,
V _A ′ is obtained by replacing R ₂ in equation (1) with 2R ₂ . In other words, V _A ′=R ₄ /R ₃ +R ₄ V _CC −(1+R ₄ /R ₃ +R ₄ −R ₁ /2
R ₂ ×R ₄ /R ₃ +R ₄ )V _F /1 + R ₁ /2R ₂ ×R ₄ /R ₃ +R ₄ ……(4)
As can be seen by comparing the above equation (4) with the previous equation (1), V _A ′>V _A because of the constant R1/2R ₂ in the denominator on the right side. Therefore, the maximum allowable input amplitude when the control input voltage V _C is near the maximum is Vinmax' = 2 (V _A '−V _F )...(5), so from Vinmax in the previous equation (3), grow bigger,
You can see that Dynamite Cleanse is big.

Here, the signal input vs. signal output of the circuit in FIG.
An example of the characteristics of the signal input terminal DC voltage V _A is shown in FIG. In the figure, the dotted line shows the conventional example (R _A =R ₂ ), and the solid line shows an example of the present invention (R _A =2R ₂ ). In the case of a small input, waveform distortion occurs in both the circuits of the present invention and the conventional example, resulting in deterioration of the characteristics, but as the input becomes large, V _A ′ decreases as shown in the figure.
Since it is larger than V _A , in the present invention, waveform distortion can be suppressed up to a larger input than in the conventional example, and good input/output characteristics can be obtained.

Note that even when R _A =2R ₂ is set in this manner, the maximum gain G is determined by G = R ₁ /R ₂ , so the same gain as the conventional one can be obtained.

That is, according to the present invention, as described above, 2
By making the resistances of the current sources of the differential pair transistors different from each other so as to have a predetermined relationship, it is possible to provide a gain control amplifier circuit in which both the gain G and the dynamic range can be set large. .

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of an automatic gain control circuit, Figure 2 is a circuit diagram showing an example of the gain control amplifier circuit in Figure 1, and Figure 3 is for explaining the operation of Figure 2. FIG. 4 is a characteristic diagram showing the conventional example and the present invention example of the characteristics shown in FIG. V _CC ...Power supply, V _C ...Control input voltage, Q ₁ to _{Q 8}
...Transistor, R ₁ to R ₈ , R _A ... Resistor, C ₁ ,
C ₂ ... Capacitor.

Claims (1)

[Scope of utility model registration request] The collector of the first transistor Q ₁ is connected to the power supply, and the collector of the second transistor Q ₂ is connected to the resistor.
A first differential pair transistor is connected to the power supply through _R1 and has its emitters connected to each other, and a third transistor _Q3 has its collector connected to the power supply and a fourth transistor _Q4 has its collector connected to the resistor.
a second differential pair of transistors connected to _the power supply via R ₁ and whose emitters are connected to each _other ; a circuit that commonly applies a control input voltage V _C between the base of the transistor Q ₄ and the base of the third transistor Q ₃ ; and a fifth circuit that is connected as an emitter current source of the first differential pair transistor. a transistor _Q5 , a circuit for applying a signal input to the base of the transistor _Q5 via a capacitor _C1 , and a sixth transistor _Q6 connected as an emitter current source of the second differential pair transistor; a circuit that buffers and amplifies the signal outputs obtained at the collectors of the second transistor Q ₂ and the fourth transistor Q ₄ ; A circuit that applies negative feedback to the bases of the transistor _Q5 and the sixth transistor _Q6 , a bias resistor R2 inserted between the emitter of the fifth transistor _Q5 and the ground terminal, and a circuit that applies negative feedback to the bases of the transistor _Q5 and the sixth transistor Q6; A gain control amplifier circuit comprising a bias resistor _RA inserted between the emitter of the transistor _Q6 and the ground terminal and having a value larger than the bias resistor _R2 .