JPS61263305A - Hysteresis comparator - Google Patents

Hysteresis comparator

Info

Publication number
JPS61263305A
JPS61263305A JP60105135A JP10513585A JPS61263305A JP S61263305 A JPS61263305 A JP S61263305A JP 60105135 A JP60105135 A JP 60105135A JP 10513585 A JP10513585 A JP 10513585A JP S61263305 A JPS61263305 A JP S61263305A
Authority
JP
Japan
Prior art keywords
current
transistor
hysteresis
resistor
iphi3
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60105135A
Other languages
Japanese (ja)
Other versions
JPH0666648B2 (en
Inventor
Shinji Tanaka
慎二 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60105135A priority Critical patent/JPH0666648B2/en
Publication of JPS61263305A publication Critical patent/JPS61263305A/en
Publication of JPH0666648B2 publication Critical patent/JPH0666648B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233Bistable circuits
    • H03K3/02337Bistables with hysteresis, e.g. Schmitt trigger

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To set optionally the temperature coefficient of hysteresis width by switching a current source current of each emitter so as to change the potential difference of the resistor between both emitter terminals of a transistor (TR) pair constituting a differential amplifier. CONSTITUTION:In a hysteresis comparator, when differential input voltages V1, V2 have a relation of V1>V2, TRs Q13, Q14, Q15 are turned off and a current source Iphi3 is set. When the voltage V1 is small and collector currents (Ic) of TRs Q11, Q12 are nearly equal, the circuit is inverted and the current is nearly equal to (Iphi1+Iphi2+Iphi3)/2. A current of (Iphi1+Iphi3-Iphi2)/2 flows to a resistor R1 and an offset by said current is given. When the voltage V1 is large and the output is switched conversely, an offset of (Iphi1-Iphi2)/2.R1 is given. The potential difference of the offset gives a hysteresis width. In this case, since the current source Iphi3 is decided by a voltage drop of the resistor R1, the temperature coefficient of the hysteresis width is set optionally.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、差動入力の波形整形機能を有するヒステリシ
スコンパレータに関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a hysteresis comparator having a differential input waveform shaping function.

従来の技術 普通例えば、モータ制御系のように、ホール素子等によ
る位置信号処理手段に使われる差動入力のヒステリシス
付きコンパレータは、差動入力電圧レベルが100 m
V前後の値であるため、ヒステリシス電圧幅も、10〜
somVと小さい。
Conventional Technology For example, a differential input comparator with hysteresis used in a position signal processing means using a Hall element, such as in a motor control system, has a differential input voltage level of 100 m.
Since the value is around V, the hysteresis voltage width is also 10~
It is as small as somV.

このような小さいヒステリシス電圧幅を設定するには、
差動対トランジスタのエミツタ面積比、電流密度比によ
る差動増幅段のベースエミッタ間電圧の差をヒステリシ
ス電圧幅として設定する場合が多い。
To set such a small hysteresis voltage width,
The difference in base-emitter voltage of a differential amplifier stage based on the emitter area ratio and current density ratio of differential pair transistors is often set as the hysteresis voltage width.

第2図は従来の代表的なヒステリシスコンパレータの回
路図であり、その回路動作の概略を以下説明する。トラ
ンジスタQ1.Q2.Q3のエミツタ面積比をSEl 
i SE2 iS)、3”1 i 1 inとする。差
動入力の各電圧v1.■2がv2〉vlの場合、トラ、
ジスタQ がオン、トランジスタQ2.Q3がオフとな
るので、電流ミラ一対トランジスタQ4.Q6を介し、
トランジスタQ6はオフ、ダイオードDはオン状態とな
り、v2が小さくなる場合には、コレラ°り電流IC3
+Ic2=IC1の時、トランジスタQ6がオンに変化
する。逆に電圧v2〈vlの場合、トランジスタQ6は
オン、ダイオードDはオフ状態で、v2が大きくなる場
合、コレクタ電流エC2=工C1の時に、トランジスタ
Q6 がオフとなり、出力が切換わる。
FIG. 2 is a circuit diagram of a typical conventional hysteresis comparator, and an outline of the circuit operation will be explained below. Transistor Q1. Q2. The emitter area ratio of Q3 is SEl
i SE2 iS), 3”1 i 1 in. If each differential input voltage v1.■2 is v2>vl, then
transistor Q is on, transistor Q2. Since Q3 is turned off, the current mirror pair of transistors Q4. Through Q6,
Transistor Q6 is off, diode D is on, and when v2 becomes small, cholera current IC3
When +Ic2=IC1, transistor Q6 turns on. Conversely, when the voltage v2<vl, the transistor Q6 is on and the diode D is off, and when v2 becomes large, when the collector current C2=C1, the transistor Q6 turns off and the output is switched.

したがって、ヒステリシス電圧幅VHは、トランジスタ
Q2  とトランジスタQ3.Q2(ただし、Q3+Q
2)とのエミツタ面積比で決定され、(1)式の通りに
表わされる。
Therefore, the hysteresis voltage width VH varies between transistors Q2 and Q3. Q2 (however, Q3+Q
2) and is determined by the emitter area ratio, and is expressed as in equation (1).

T VH=−1n(n−H)      −−−−−・−(
1)(ただし、q;電子電荷 k;ボルッマル定数T;
温度) 例えば n=1とすると、(1)式から、室温時に、約
18mVのヒステリシス電圧幅を設定することができる
T VH=-1n(n-H) -------・-(
1) (where q; electronic charge k; Bolmar constant T;
Temperature) For example, if n=1, from equation (1), a hysteresis voltage width of about 18 mV can be set at room temperature.

発明が解決しようとする問題点 ところが、第2図に示される様なヒステリシスコンパレ
ータの場合、ヒステリシス電圧幅が、(1)式でも明ら
かな通り、温度係数を持っている。特にモータ制御装置
等に応用する場合、パワートランジスタと同チップ上に
このヒステリシスコンパレータを集積することもあり、
保証すべき温度範囲も広く、ホール素子入力信号が微少
であると、そのヒステリシス電圧幅の設定が雛しくなる
Problems to be Solved by the Invention However, in the case of a hysteresis comparator as shown in FIG. 2, the hysteresis voltage width has a temperature coefficient, as is clear from equation (1). Particularly when applied to motor control devices, this hysteresis comparator may be integrated on the same chip as the power transistor.
The temperature range to be guaranteed is wide, and if the Hall element input signal is minute, the setting of the hysteresis voltage width becomes difficult.

また、第2図に示される様なヒステリシスコンパレータ
の場合、差動入力条件がvl(v2の場合とvl〉v2
の場合とで、同じ電圧差におけるトランジスタQつ 側
と同Q2.Q3側とのベース電流値が(n+1)倍違う
ため、差動入力の信号源インピーダンスが充分低くない
場合、元来、全く対称であった差動入力が、非対称にな
ってし1う。これは、例えばモータ制御装置等に応用し
た場合で、且つ、ヒステリシスコンパレータ以外の集積
回路に差動入力信号を利用する時に、問題となることが
ある。
In addition, in the case of a hysteresis comparator as shown in Fig. 2, the differential input condition is vl (v2 and vl>v2
In the case of the transistor Q side and the same Q2 side at the same voltage difference. Since the base current value on the Q3 side differs by a factor of (n+1), if the signal source impedance of the differential input is not low enough, the differential input, which was originally completely symmetrical, becomes asymmetrical. This may become a problem when applied to a motor control device, for example, and when a differential input signal is used in an integrated circuit other than a hysteresis comparator.

本発明はこのような問題点を除くことの可能な回路構成
を提供するものである。
The present invention provides a circuit configuration that can eliminate such problems.

問題点を解決するための手段 本発明は、要約するに、差動増幅器を構成するトランジ
スタ対と同トランジスタ対の両エミッタ端子間に接続さ
れた抵抗と、同トランジスタ対の各エミッタ端子に各々
電流源が接続さ扛、前記電流源の一方に、前記差動増幅
器の出力によって制御されるトランジスタで電流源電流
を切換えて、前記抵抗に生じる電位差によるヒステリシ
ス幅を設定する構成のヒステリシスコンパレータである
Means for Solving the Problems In summary, the present invention consists of a pair of transistors constituting a differential amplifier, a resistor connected between both emitter terminals of the pair of transistors, and a current flowing through each emitter terminal of the pair of transistors. The hysteresis comparator is configured such that a current source is connected to one of the current sources, the current source current is switched by a transistor controlled by the output of the differential amplifier, and a hysteresis width is set by a potential difference generated in the resistor.

作   用 本発明によると、差動増幅段を構成するトランジスタ対
と同トランジスタ対のエミッタ端子間に接続された抵抗
と、同トランジスタ対のエミッタ端子に接続された一対
の電流源とその一方の電流源に対して、オン、オフ可能
な第2の電流ミラ一対構成を並列に結合したため、ヒス
テリシス特性は、切換可能な第2の電流ミラ一対電流と
前記抵抗で生じる降下電圧によってそのヒステリシス幅
が決められるので、温度係数の設定が容易である。
According to the present invention, a pair of transistors constituting a differential amplification stage, a resistor connected between the emitter terminals of the pair of transistors, a pair of current sources connected to the emitter terminals of the pair of transistors, and a current flowing through one of them. Since the second pair of current mirrors that can be turned on and off are connected in parallel to the source, the hysteresis width is determined by the current of the second pair of switchable current mirrors and the voltage drop generated in the resistor. Therefore, it is easy to set the temperature coefficient.

また、差動増幅段を構成するトランジスタ対のベース電
流の対称性も、電流変化が小さいために。
In addition, the base currents of the transistor pairs that make up the differential amplifier stage are symmetrical because current changes are small.

影響は小さい。The impact is small.

実施例 第1図に本発明の一実施例によるヒステリシスコンパレ
ータの回路構成を示す。
Embodiment FIG. 1 shows a circuit configuration of a hysteresis comparator according to an embodiment of the present invention.

回路動作を以下説明する。差動入力条件が、vl〉■2
の時、トランジスタQ13.Q14.Q1.はオフで、
トランジスタQ16.Q1□で構成される電流ミラ一対
による電流源Iφ3 はオンである。
The circuit operation will be explained below. The differential input condition is vl〉■2
When transistor Q13. Q14. Q1. is off,
Transistor Q16. A current source Iφ3 formed by a pair of current mirrors made up of Q1□ is on.

したがって、vl  が小さくなって、トランジスタQ
13.Q14.Q1.がオンするのは、差動対トランジ
スタQ11.Q12 のコレクタ電流が、はぼ等しくな
った時なので、その電流値は(工φ1 + 工φ2 +
 Iφ3)/2にほぼ等しい。
Therefore, vl becomes smaller and transistor Q
13. Q14. Q1. is turned on because the differential pair transistor Q11. This is when the collector currents of Q12 are approximately equal, so the current value is
It is approximately equal to Iφ3)/2.

したがって、抵抗R1には、(Iφ1+工φ3−Iφ2
)/2の電流が流れており、両エミッタ間に (Iφ1+工φ3−Iφ2)/2・R4に等しいオフセ
ット(電位差座ついたことになる。逆に、差動入力条件
が、v2〉vlの時、トランジスタQ13.Q14.Q
1゜はオンで、電流源Iφ3はオフである。しだがって
、vl  が大きくなって出力が切換わるのは、トラン
ジメタ対Q11.Q1□ のコレクタ電流が、はぼ等し
くなった時、つまり(Iφ1+工φ2)/2にほぼ等し
く、抵抗R1に(工φ1−Iい。)/2の電流が流れて
いる時である。このとき、トランジスタQ11.Q12
の両工ミッタ間に、(工φ1−Iφ2)/2・R1のオ
フセットがついた状態になり、この電位差がヒステリシ
ス幅となる。なお、トランジスタQ18.Q19  は
電流源用の電流ミラ一対である。
Therefore, the resistance R1 has (Iφ1 + engineeringφ3−Iφ2
)/2 current is flowing, and an offset (potential difference) equal to (Iφ1 + engineeringφ3−Iφ2)/2・R4 is flowing between both emitters.Conversely, if the differential input condition is v2>vl, When, transistor Q13.Q14.Q
1° is on and current source Iφ3 is off. Therefore, the reason why vl increases and the output switches is due to the transistor pair Q11. This is when the collector current of Q1□ is approximately equal, that is, approximately equal to (Iφ1+φ2)/2, and a current of (φ1−I)/2 is flowing through the resistor R1. At this time, transistor Q11. Q12
An offset of (Iφ1-Iφ2)/2·R1 is created between the two transmitters, and this potential difference becomes the hysteresis width. Note that the transistor Q18. Q19 is a pair of current mirrors for the current source.

以上より、トータルのヒステリシス幅は、上記2つの状
態のオフセットの和、つまり(功弐〇通シ(噂式でも明
らかな通り、電流源Iφ3が抵抗R1での降下電圧で決
定されるために、ヒステリシス幅の温度係数を任意に設
定できる利点がある。
From the above, the total hysteresis width is the sum of the offsets of the above two states, that is, as the current source Iφ3 is determined by the voltage drop across the resistor R1, There is an advantage that the temperature coefficient of the hysteresis width can be set arbitrarily.

また、ペース電流の変化は従来に比べ小さいため、信号
源インピーダンスが高くても、信号が歪まない。
Furthermore, since the change in pace current is smaller than in the past, the signal will not be distorted even if the signal source impedance is high.

発明の効果 以上で明らかな通り、本発明によれば次の2つの効果が
ある。
Effects of the Invention As is clear from the above, the present invention has the following two effects.

第1の効果は、ヒステリシス巾の温度係数を任2意に設
定できる。
The first effect is that the temperature coefficient of the hysteresis width can be set arbitrarily.

第2の効果は、信号源インピーダンスの高い入力信号で
も歪まない。
The second effect is that even input signals with high signal source impedance are not distorted.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例によるヒステリシスコンパレ
ータの回路構成図、第2図は、従来例によるヒステリシ
スコンパレータの回路構成図である。 Q11〜Q19・・・・・・トランジスタ、R1・・・
・・・抵抗。
FIG. 1 is a circuit diagram of a hysteresis comparator according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional hysteresis comparator. Q11-Q19...Transistor, R1...
···resistance.

Claims (1)

【特許請求の範囲】[Claims] 差動増巾器を構成するトランジスタ対と同トランジスタ
対の両エミッタ端子間に接続された抵抗と、同トランジ
スタ対の各エミッタ端子に各々電流源が接続され、前記
電流源の一方に、前記差動増幅器の出力で制御されるト
ランジスタで電流源電流を切換えて、前記抵抗に生じる
電圧差によるヒステリシス幅を設定する構成のヒステリ
シスコンパレータ。
A transistor pair constituting a differential amplifier, a resistor connected between both emitter terminals of the transistor pair, and a current source connected to each emitter terminal of the transistor pair, and one of the current sources is connected to the differential amplifier. A hysteresis comparator configured to switch a current source current using a transistor controlled by an output of a dynamic amplifier to set a hysteresis width based on a voltage difference generated across the resistor.
JP60105135A 1985-05-17 1985-05-17 Hysteresis comparator Expired - Lifetime JPH0666648B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60105135A JPH0666648B2 (en) 1985-05-17 1985-05-17 Hysteresis comparator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60105135A JPH0666648B2 (en) 1985-05-17 1985-05-17 Hysteresis comparator

Publications (2)

Publication Number Publication Date
JPS61263305A true JPS61263305A (en) 1986-11-21
JPH0666648B2 JPH0666648B2 (en) 1994-08-24

Family

ID=14399306

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60105135A Expired - Lifetime JPH0666648B2 (en) 1985-05-17 1985-05-17 Hysteresis comparator

Country Status (1)

Country Link
JP (1) JPH0666648B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63136712A (en) * 1986-11-28 1988-06-08 Toshiba Corp Differential comparator
JPS63263910A (en) * 1987-04-22 1988-10-31 Nec Corp Voltage comparator
JPS63296514A (en) * 1987-05-28 1988-12-02 Matsushita Electric Ind Co Ltd Hysteresis comparator
US7126419B2 (en) 2002-03-12 2006-10-24 Oki Electric Industry Co., Ltd. Analog summing and differencing circuit, optical receiving circuit, optical transmitting circuit, automatic gain control amplifier, automatic frequency compensation amplifier, and limiting amplifier

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5335465A (en) * 1976-09-14 1978-04-01 Sony Corp Differential input type trigger circuit
JPS57170621A (en) * 1981-04-10 1982-10-20 Mitsubishi Electric Corp Comparing circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5335465A (en) * 1976-09-14 1978-04-01 Sony Corp Differential input type trigger circuit
JPS57170621A (en) * 1981-04-10 1982-10-20 Mitsubishi Electric Corp Comparing circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63136712A (en) * 1986-11-28 1988-06-08 Toshiba Corp Differential comparator
JPS63263910A (en) * 1987-04-22 1988-10-31 Nec Corp Voltage comparator
JPS63296514A (en) * 1987-05-28 1988-12-02 Matsushita Electric Ind Co Ltd Hysteresis comparator
US7126419B2 (en) 2002-03-12 2006-10-24 Oki Electric Industry Co., Ltd. Analog summing and differencing circuit, optical receiving circuit, optical transmitting circuit, automatic gain control amplifier, automatic frequency compensation amplifier, and limiting amplifier

Also Published As

Publication number Publication date
JPH0666648B2 (en) 1994-08-24

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