JPH062349Y2 - ECL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an ECL circuit having means for level shifting or amplifying its output.

[Prior Art] ECL (Emitter Coupled Logic) circuit is TTL or C-MOS
It has a feature that its operating speed is faster than that of the Logic circuit, and is widely used as a digital circuit element.

In such an ECL circuit, when the output is level-shifted or amplified, a circuit as shown in FIG. 2 (a) or (b) has been used. That is, in FIG. 2A, U1 is an ECL circuit and IN is a terminal to which the input signal Vi is applied. When the output of the ECL circuit is level-shifted or amplified in the circuit of FIG. 9A, a differential amplifier circuit including grounded emitter transistors Q1 and Q2 is used as the means. In addition, in (a) figure, R
1, R2 is the load resistance of the output Q of the ECL circuit U1, V
CC is a positive voltage source, and VEE and VDD are negative voltage sources, respectively. Such a circuit shown in FIG.
It is often used when level shifting or amplifying the output of a circuit. However, in this circuit, when high speed is required, delay in switching characteristics due to the mirror effect of Cob (capacitance between collector and base) of the transistors Q1 and Q2 becomes a problem, and it becomes expensive to use a circuit with less Cob. . On the other hand, the circuit shown in FIG. 2B uses the grounded transistors Q1 and Q2 to level shift or amplify the output of the ECL circuit U1. In this circuit, the influence of Cob of the transistors Q1 and Q2 is reduced and the speed can be increased.
Bias power supply BBB is required for each base.

[Purpose of device]

The present invention has been made to solve such a drawback, and the purpose thereof is an ECL circuit in which a means for level shifting or amplifying is speeded up with an extremely simple structure without requiring a bias power source or the like. Is to realize.

[Constitution of device]

In order to achieve the above-mentioned object, the present invention connects the emitter electrodes of a pair of grounded-base type transistors whose base electrodes are commonly connected to both output terminals of an ECL circuit,
The output is taken out from the collector electrodes of these transistors. Examples will be described below.

〔Example〕

FIG. 1 is a connection diagram of an embodiment of the circuit according to the present invention.
In the figure, U1 indicates an ECL circuit, and Q indicates its output. R1 and R2 are load resistors, one end of which is E
It is connected to the output Q of the CL circuit and the other end is the negative power supply VEE.
It is connected to the. Q1 and Q2 are transistors, R3 to
R5 is a resistor, and C1 is a capacitor. The emitter electrodes of the transistors Q1 and Q2 are connected to the output Q of the ECL circuit U1, the collector electrode C is connected to the voltage source Vcc through the load resistors R4 and R5 of this transistor,
The base electrode is commonly connected to the ground point via a parallel circuit of a resistor R3 and a capacitor C1. The resistor R3 is for supplying a bias current, and is a transistor Q.
The potential at the connection point of the base electrodes of 1 and Q2 is (ECL circuit U
1 output low level) + (transistor Q1 or Q2
Is clamped to the base-emitter voltage Vbe). With such a connection, the transistors Q1 and Q2 form a grounded base amplifier.
The level shift output or amplified output is the transistor Q1,
It is extracted from the collector current C of Q2.

In the circuit of FIG. 1 having such a configuration, the common base potential of the transistors Q1 and Q2 forming the base-grounded amplifier is (low level of output of ECL circuit U1) +
Since it is clamped (to Vbe), the transistor Q1 or Q2 on the side of the output Q of the ECL circuit U1 which has become high level is cut off. Since the level of the output Q of the ECL circuit U1 is alternately set to high or low, the transistors Q1 and Q2 are alternately turned on and off in response to the level of the output Q, of the transistors Q1 and Q2 with an amplification factor peculiar to the base-grounded type. The shifted or amplified digital signal is taken out.

In the ECL circuit according to the present invention having such a configuration,
Since the level shift or amplification of the output signal of the ECL circuit is performed using the grounded base type transistors Q1 and Q2, the influence of Cob of the transistors Q1 and Q2 is reduced,
High-speed switching operation is possible as compared with the circuit (a) of FIG. 2 which uses a grounded-emitter transistor.
Also, the grounded base circuit is used as a differential circuit, and the transistor Q
Since the bases of 1 and Q2 are common, the base potentials of both transistors are automatically determined, only the resistor R3 is required as the base bias means, and the bias power supply VBB is unnecessary as shown in Fig. 2 (b). Next, the configuration is simplified.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an embodiment of an ECL circuit according to the present invention, and FIGS. 2 (a) and 2 (b) are connection diagrams of a conventional ECL circuit. U1 ... ECL circuit, Q1, Q2 ... Transistor, R1,
R2 ... load resistance, R3 ... bias resistor.

Claims (1)

[Scope of utility model registration request] 1. A pair of grounded base transistors each having a base electrode connected in common and an emitter electrode respectively connected to both output terminals of complementary outputs of an ECL circuit. It is connected to a negative power source via a parallel circuit of a resistor and a capacitor, and both base electrodes are grounded. Both collector electrodes are connected to a positive power source via a resistor and output from each of these collector electrodes. An ECL circuit characterized by being configured to take out.