JPH0595276A - Or circuit - Google Patents

Abstract

PURPOSE:To quicken the operating speed by forming a differential pair with 2nd and 3rd transistors(TRs), forming a common base amplifier circuit with 1st, 4th and 5th TRs and using the common base amplifier circuit so as to converts a selected current. CONSTITUTION:TRs 3,4,5 are used to select a current depending on the polarity of a difference between the voltage of an input signal and a reference voltage inputted to input terminals 102,103. A selected current is received by the low input impedance of a common base circuit and its output is used for current voltage conversion. The input impedance of the common base circuit is a reciprocal of a mutual conductance gm of a common emitter amplifier circuit by assuming a common base current amplification factor a of the TR to be nearly equal to 1. That is, an input capacitance Cin of the common emitter amplifier circuit is expressed as Cin=Cin (1+gm/gm), no mirror effect is caused, the charge/discharge time of the input capacitance by the input signal is reduced. Thus, the operating speed is quickened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of an OR circuit, and more particularly to an OR circuit for logically processing high speed data signals.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 2, an OR circuit of this type has a transistor 3 having a base connected to a voltage source 31 serving as a reference voltage, and a transistor having an emitter connected to the collector. 4 and the emitter of the transistor 5 are connected together, and the resistor 12 is connected between the collector of the transistor 3 and the positive side of the voltage source 32,
A resistor 11 is connected between the common collector of the transistors 4 and 5 and the positive side of the voltage source 32, and the common emitters of the transistors 3, transistors 4 and 5 and the negative positive side of the voltage source 31 and the voltage source 32 are connected. Between the current value setting element (for example, a current mirror type constant current source) 2
The current is switched by the current switching circuit based on the differential pair circuit in which 1 is inserted, and the switched current is changed to the resistor 1
It is composed of a circuit for converting a voltage by means of 1 and a resistor 12.

[0003]

This conventional OR circuit is basically the same as the differential amplifier circuit, and as shown in FIG. 2, the voltage input to the input terminals 102 and 103 and the input voltage. If the potential difference from the reference voltage applied to the terminal 101 is within three times the thermal voltage VT (≉26 mV), it operates as an amplifier circuit. That is, the amplifier operates immediately before and after the signal input to the input terminal 102 or the input terminal 103 exceeds the reference voltage. This differential amplifier circuit can be considered as a grounded-emitter amplifier circuit in which the common emitter section is virtually grounded. The grounded-emitter amplifier circuit has a transistor transconductance of gm, a load resistance of R, and a collector-base capacitance of C _jc . At this time, the input capacitance C _in seen from the input terminal is C _in = C _jc (1 + g
m × R), the input capacitance increases due to the Miller effect, a change in the input signal takes time to charge and discharge the input capacitance, and there is a problem that the operation speed is limited.

[0004]

The logical sum circuit of the present invention is
The positive electrode side of the first voltage source is connected to the base of the first transistor as a reference voltage, the collectors are connected together, and the bases are connected to the first input terminal and the second input terminal, respectively. The respective emitters of the transistors and the third transistor and the emitter of the first transistor are connected together, and the emitter connection points of the first, second, and third transistors and the first transistor are connected.
In a current switching logical sum circuit in which a current value setting element is connected between the negative voltage side of the second voltage source and the second voltage source, the emitter is connected to the collector of the first transistor, and the base is the second voltage. A fourth transistor connected to the positive side of the source, a collector to which the second transistor and the third transistor are connected together, and an emitter connected to the positive side of the second voltage source. A fifth transistor connected to the fourth transistor; a first resistor connected between the choresta of the fourth transistor and the positive electrode side of the third voltage source; a collector of the fifth transistor; and a third power supply. A second resistor connected between the positive electrodes.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In FIG. 1, in this embodiment, the transistor 3 has a base connected to the positive electrode side of a voltage source 31 as a reference voltage, a collector connected together, and a base connected to an input terminal 102 and an input terminal 103, respectively. 4 and the emitters of the transistor 5 and the emitter of the transistor 3 are connected together to form the transistors 3, 4
And 5 emitter connection points and voltage source 31, voltage source 32
In the current switching circuit in which the current value setting element 21 is connected to each negative electrode side of the voltage source 33, the transistor 2 whose emitter is connected to the collector of the transistor 3 and whose base is connected to the positive electrode side of the voltage source 33; Four
And a transistor 1 having an emitter connected to the collector of the transistor 5 and a base connected to the positive side of the voltage source 33, and a resistor 11 connected between the collector of the transistor 1 and the positive side of the voltage source 32. , A resistor 12 connected between the collector of the transistor 2 and the positive side of the power supply 32.

Next, the operation of this embodiment will be described.

Transistors 3, 4 and 5 have currents depending on the polarity of the potential difference between the voltage value of the input signal input to input terminals 102 and 103 and the reference voltage, as in the conventional OR circuit shown in FIG. It is a current switching circuit for switching.

In the conventional OR circuit shown in FIG. 2, the switched current is converted from current to voltage by the load resistance, but in the OR circuit of this embodiment, the switched current is converted into the low voltage of the grounded base circuit. The input impedance is received, and current-voltage conversion is performed with the output of the base ground circuit type.

For the input impedance of the grounded base circuit, the grounded base current amplification factor α of the transistor is "≈1".
Assuming that, it is the reciprocal of the mutual conductance gm of the grounded-emitter amplifier circuit. That is, the input capacitance C _in of the grounded-emitter amplifier is C _in = C _jc (1 + gm / gm) when the capacitance between _corktor bases is C _jc , the Miller effect disappears, and the charging / discharging time of the input capacitance by the input signal is reduced. Is shortened.

[0012]

As described above, in the logical sum circuit of the present invention, the second transistor and the third transistor forming the differential pair are connected in common to the collector and the collector of the first transistor, respectively. The emitter is connected,
A fourth transistor and a fifth transistor that form a base-grounded amplifier circuit are provided, and the fourth transistor and the fifth transistor are provided.
Current is converted by the base-mounted circuit into the current switched by the current switching circuit by connecting the first resistor and the second resistor to the respective collectors of the transistor and the current. By using a base-mounted circuit having a low input impedance as the load of the switching unit, it is possible to prevent an increase in the input capacitance due to the Miller effect and to increase the operation speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional OR circuit.

[Explanation of symbols]

 1-5 Transistor 11,12 Resistor 21 Current value setting device 31-33 Voltage source 101-103 Input terminal 201,203 Output terminal

Claims (1)

[Claims] 1. The base of the first transistor is connected to the positive electrode side of a first voltage source as a reference voltage, the collectors are connected together, and the base is a first input terminal, respectively.
The respective emitters of the second transistor and the third transistor connected to the second input terminal and the emitter of the first transistor are connected together,
In a current switching logical sum circuit in which a current value setting element is connected between the emitter connection point of each of the second and third transistors and the negative electrode side of the first voltage source and the second voltage source, A collector in which the emitter is connected to the collector of the first transistor and the base is connected to the positive electrode side of the second voltage source, and the collector in which the second transistor and the third transistor are connected together. A fifth transistor having an emitter connected to the base and a base connected to the positive electrode side of the second voltage source;
A first resistor connected between the Choresta of the transistor and the positive electrode side of the third voltage source, and a second resistor connected between the collector of the fifth transistor and the positive electrode side of the third power supply. An OR circuit characterized by comprising: