JP3073619B2 - Sample hold circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample-and-hold circuit, and more particularly to a sample-and-hold circuit composed of an IC.

[0002]

2. Description of the Related Art An example of a conventional sample and hold circuit is shown in FIG. In the figure, reference numeral 21 denotes a differential circuit constituting a switch unit, 25 is an input terminal, 26 is a sampling output terminal, and the output terminal 26 is connected to a holding capacitor C1. The differential circuit 21 includes a differential pair transistors Q22 and Q23 and a current mirror type transistor Q2 connected to their collectors.
4, Q25 and resistors R2, R3. 22 is a switching circuit, and 23 is a constant current source. The switching circuit 22 comprises a differential pair of transistors Q26 and Q27, while the constant current source 23 comprises a transistor Q21 and a resistor R1.

[0003] Next, the operation of the sample and hold circuit will be described. FIG. 6 shows a signal (a) from a CCD sensor (not shown) and a sampling pulse (b) input to this circuit. When the signal (a) is applied to the input terminal 25 and the sampling pulse (b) is applied to the terminal 27 (provided that the constant voltage E is applied to the terminal 28), while the sampling pulse (b) is at a high potential, the transistor Q
26 conducts, the differential circuit 21 operates, and the input signal is directly output to the output terminal 26. During the period when the sampling pulse (b) is at a low potential, the transistor Q26 is shut off, so that the differential circuit 21 does not operate and the signal charge is held by the capacitor C1 connected to the output terminal 26. This operation is repeated to extract only the signal component (c) from the input signal (a) and hold the charge.

[0004]

However, in the above configuration, the differential circuit 21 and the switching circuit 22 forming the switch section are connected in cascade between the power supply line 20 and the ground. There is a disadvantage that operation becomes difficult when the power supply voltage Vcc is lowered.

An object of the present invention is to provide a sample and hold circuit which can operate even at a low power supply voltage by eliminating the above-mentioned drawbacks.

[0006]

In order to achieve the above object, a sample and hold circuit according to the present invention comprises: a constant current source; a first differential circuit forming a switch connected to the constant current source; A holding capacitor connected to the output terminal of the first differential circuit, and a current having the same value as the output current of the constant current source is output to a connection point between the differential circuit and the constant current source except during the sampling period; In the sampling period, a switching means for outputting a small current for turning on the differential circuit or for outputting no current to the connection point is provided. So
The switching means comprises a second differential circuit and a second differential circuit.
And a constant current circuit driven by the second differential circuit.
The path is controlled by the sampling pulse
I have.

[0007]

According to this structure, the switching circuit, which is inserted in cascade between the differential circuit and the constant current source in the above-mentioned conventional example, is in the form of an outside. The number of transistors cascaded between grounds is reduced, and operation is possible even when the power supply voltage is reduced.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 6 denotes a pair of differential pair transistors Q
2, Q3, a transistor Q4, Q5 connected to the collector side thereof and forming a current mirror type load, and a differential circuit forming a switch unit including resistors R2, R3. The input terminal 2 to which the signal shown in a) is applied is an output terminal. The output terminal 2 is connected to a hold capacitor C1. The emitters of the differential pair transistors Q2 and Q3 are commonly connected to a constant current source 3. The constant current source 3 includes a transistor Q1 and a resistor R1, and its output current is set to 2I.

Reference numeral 7 denotes a switching circuit comprising a pair of differential pair transistors Q11 and Q12. The input terminal 4 is supplied with a sampling pulse, and the input terminal 5 is supplied with a constant voltage E1. . The switching circuit 7 is connected to the constant current source transistor Q10. This constant current source transistor Q10 allows a current I to flow. The collector of the transistor Q11 is connected to the point (e), and the collector of the transistor Q12 is connected to the emitter of the transistor Q5.

The resistors R4 to R7 and the transistor Q7 supply a base potential to the transistors Q1 and Q10. The collector of the transistor Q8 forming a current mirror circuit together with the transistor Q7 is connected to the point (e), and the point (e) is further connected to the emitter of the transistor Q9. The base of transistor Q9 is connected to resistors R5 and R6,
The collector is connected to a point (f), that is, a connection point between the differential circuit 6 and the constant current source 3. The transistor Q8 is 2I
Is set to output a current of Note that the dotted line 10
The part surrounded by is a constant current circuit.

Next, the operation of the sample and hold circuit will be described. First, the signal of FIG. 6 (a) is given to the input terminal 1 and the sampling pulse {terminal of FIG.
(B) In the state where｝ is given, during the period when the sampling pulse (b) is at a high potential, the transistor Q1
1 is conducting, and the transistor Q11 has a constant current I
Flow. Further, since the transistor Q8 flows the constant current 2I, the transistor Q9 outputs the current of the subtraction I (that is, half the current I of the constant current source 3). Therefore, a predetermined operation is performed because the constant current I flows through the differential circuit 6, an input signal is derived to the output terminal 2, and the electric charge is charged to the capacitor C1.

Next, while the sampling pulse (b) is at a low potential, the transistor Q11 is turned off,
Since the constant current 2I of the transistor Q8 flows into the transistor Q1 as it is via the transistor Q9, no current is supplied to the differential circuit 6, and the differential circuit 6 is turned off. At the same time, the transistor Q12 is turned on, so that the transistor Q5 is immediately cut off and the capacitor C1 is turned off.
Is in a high impedance state, and the charge is held.
This circuit is suitable for operation at a low power supply voltage because the number of cascaded stages of transistors between the power supply line 20 and the ground is smaller than that of the conventional example of FIG.

Next, in the embodiment of FIG. 2, the transistor Q1 forming the constant current source 3 is set so that the current I flows.
Further, a constant voltage E1 is applied to a terminal 4 of a switching circuit 7 including the differential pair transistors Q14 and Q15, and a sampling pulse shown in FIG.
The collector of the transistor Q14 is connected as shown to a transistor Q16 forming a current mirror circuit.
The current value of the transistor Q17 which forms a current mirror circuit together with the transistor Q16 is set so as to output the current I. The collector of the transistor Q17 is connected to the connection point (f) between the differential circuit 6 and the constant current source 3. The resistors R4 and R5 divide the power supply voltage Vcc of the power supply line 20 to generate transistors Q1 and Q5.
Thirteen bases are biased.

In this sample and hold circuit, first, the transistor Q14 is turned on during the high potential period of the sampling pulse.
FF and the transistor Q15 are turned on, and the transistors Q16 and Q17 are turned off.
No current flows from point 17 to point (f), so the constant current source 3
Flows to the differential circuit 6. The differential circuit 6 derives the input signal applied to the input terminal 1 to the output terminal 2, and stores the signal charge in the capacitor C1. Next, during the low potential period of the sampling pulse (b), the transistor Q14 is turned off.
N, the transistor Q15 is turned off, the transistors Q16 and Q17 operate, and the current I is supplied from the transistor Q17 to the point (f). Since this current I becomes the current I flowing through the low current source 3, no current flows through the differential circuit 6, and the differential circuit 6 is turned off. During this OFF state, the capacitor C1 has a high impedance and holds the accumulated charge.

Each of the embodiments shown in FIGS. 3 and 4 is obtained by replacing each transistor in FIGS. 1 and 2 with a transistor of the opposite conductivity type, and is substantially the same as FIGS. 1 and 2.

[0016]

As described above, according to the present invention, only a differential circuit and a constant current source are connected in cascade, and a circuit for supplying a current to those connection points is provided outside the cascade connection circuit. Therefore, the number of transistors cascaded between the power supply line and the ground is reduced, and a sample-and-hold circuit that operates even at a low power supply voltage is realized. In addition, sampling period and other than sampling period
Is controlled by a first differential circuit (for sampling).
Switch section) and a second differential circuit separate from the switch section).
Switch off regardless of the voltage of the input signal being sampled.
Change control can be performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a sample and hold circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a sample and hold circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a sample and hold circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a sample and hold circuit according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional example.

FIG. 6 is a circuit diagram showing signal waveforms applied to a sample and hold circuit.

[Explanation of symbols]

 1 input terminal 2 output terminal 3 constant current source 6 differential circuit C1 capacitor

Claims (1)

(57) [Claims] A constant current source; a first differential circuit forming a switch connected to the constant current source; a hold capacitor connected to an output terminal of the first differential circuit; A current equal to the output current of the constant current source is output to the connection point between the first differential circuit and the constant current source during a period other than the sampling period, and a small current for turning on the differential circuit is output during the sampling period. or a switching means does not output a current to the connection point, Ri consists, said switching means second difference
And a constant current circuit driven by the second differential circuit
And the second differential circuit is based on the sampling pulse.
Controlled sample and hold circuit.