JPH07111098A - Sample-hold circuit - Google Patents

Abstract

PURPOSE:To decrease the number of stages of transistors connected in cascade between a power supply line and ground by outputting a current having the same value as an output current of a constant current source to a connecting point of the constant current source of a differential circuit except a sampling period. CONSTITUTION:A transistor Q11 is made a cut off state in a period when a sampling pulse is in a low potential, since a current flows directly to a transistor Q1 through a transistor Q9, a differential circuit 6 is turned off. At the same time, since a transistor Q12 is made a continuity state, a transistor Q5 is immediately cut off, a capacitor C1 is made a high impedance state, and electric charges are held. Since the number of stages of transistors connected in cascade between a power supply line 20 and ground is less comparing with a conventional circuit in this circuit, this circuit is suitable for operation with a low power supply voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit composed of an IC.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a conventional sample and hold circuit. In the figure, reference numeral 21 is a differential circuit forming a switch portion, 25 is an input terminal, 26 is a sampling output terminal, and a hold capacitor C1 is connected to the output terminal 26. The differential circuit 21 includes a differential pair of transistors Q22 and Q23 and a transistor Q2 which is connected to the collectors of the differential pair transistors and forms a current mirror type load.
4, Q25 and resistors R2 and R3. Further, 22 is a switching circuit, and 23 is a constant current source. The switching circuit 22 includes a differential pair transistor Q26 and Q27, while the constant current source 23 includes a transistor Q21 and a resistor R1.

Next, the operation of this sample hold circuit will be described. FIG. 6 shows a signal (a) and a sampling pulse (b) from a CCD sensor (not shown) input to this circuit. When the signal (a) is applied to the input terminal 25 and the sampling pulse (b) is applied to the terminal 27 (provided that the terminal 28 is applied with a constant voltage E), the transistor Q is supplied while the sampling pulse (b) is at a high potential.
26 becomes conductive, the differential circuit 21 operates, and the input signal is directly output to the output terminal 26. Since the transistor Q26 is cut off while the sampling pulse (b) is at a low potential, the differential circuit 21 does not operate, and the signal charge is held by the capacitor C1 connected to the output terminal 26. By repeating this operation, it is possible to extract only the signal component (C) from the input signal (a) and hold the charge.

[0004]

However, in the above configuration, since the differential circuit 21 forming the switch section and the switching circuit 22 are connected in series between the power supply line 20 and the ground, There is a drawback that it becomes difficult to operate when the power supply voltage Vcc decreases.

An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a sample hold circuit which can operate even at a low power supply voltage.

[0006]

In order to achieve the above object, a sample hold circuit of the present invention comprises a constant current source, a differential circuit comprising a switch section connected to the constant current source, and the differential circuit. Output a current having the same value as the output current of the constant current source except the sampling period at the connection point between the hold capacitor connected to the output terminal of the differential circuit and the constant current source, and the differential circuit during the sampling period. And a circuit that outputs a small current that turns on or does not output a current to the connection point.

[0007]

According to this structure, the switching circuit, which is inserted in a cascade form between the differential circuit and the constant current source in the above-mentioned conventional example, is provided outside, so that the power supply line and The number of transistors connected in cascade between the grounds is reduced, and operation is possible even when the power supply voltage is low.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, 6 is a pair of differential pair transistors Q
2 and Q3, transistors Q4 and Q5 forming a current mirror type load connected to their collectors, and resistors R2 and R3. The input terminal 2 to which the signal shown in a) is given and 2 are output terminals. A holding capacitor C1 is connected to the output terminal 2. The emitters of the differential pair transistors Q2 and Q3 are commonly connected to the constant current source 3. The constant current source 3 is composed of a transistor Q1 and a resistor R1, and its output current is set to 2I.

A switching circuit 7 is composed of a pair of differential pair transistors Q11 and Q12. A sampling pulse is applied to its input terminal 4 and a constant voltage E1 is applied to its input terminal 5. . The switching circuit 7 is connected to the constant current source transistor Q10. The constant current source transistor Q10 passes a current I. The collector of the transistor Q11 is connected to the point (e), and the collector of the transistor Q12 is connected to the emitter of the transistor Q5.

The resistors R4 to R7 and the transistor Q7 supply the base potential to the transistors Q1 and Q10. The collector of the transistor Q8 that forms a current mirror circuit together with the transistor Q7 is connected to the point (e), and the point (e) is further connected to the emitter of the transistor Q9. The base of transistor Q9 is connected to resistors R5 and R6,
The collector is connected to point (f), that is, the midpoint of connection between the differential circuit 6 and the constant current source 3. The transistor Q8 is 2I
Is set to output the current. The dotted line 10
The part surrounded by indicates a constant current circuit.

Next, the operation of this sample hold circuit will be described. First, the signal of FIG. 6A is given to the input terminal 1, and the sampling pulse is applied to the terminal 4 {FIG.
(B)} is applied to the transistor Q1 during the period when the sampling pulse (b) is at a high potential.
1 is conducting, and this transistor Q11 has a constant current I
Shed. Further, since the transistor Q8 supplies the constant current 2I, the transistor Q9 outputs the current of the subtraction I (that is, the current I which is half the current 2I of the constant current source 3). Therefore, since the constant current I flows through the differential circuit 6, a predetermined operation is performed, an input signal is derived from the output terminal 2, and the electric charge is stored in the capacitor C1.

Next, during the period when the sampling pulse (b) is at a low potential, the transistor Q11 is cut off,
The constant current 2I of the transistor Q8 flows into the transistor Q1 as it is through the transistor Q9, so that no current is supplied to the differential circuit 6 and the differential circuit 6 is turned off. At the same time, since the transistor Q12 becomes conductive, the transistor Q5 immediately cuts off and the capacitor C1
Becomes a high impedance state, and the electric charge is retained.
This circuit is suitable for low power supply voltage operation because the number of cascaded transistors between the power supply line 20 and the ground is smaller than that of the conventional example shown in FIG.

Next, in the embodiment of FIG. 2, the transistor Q1 forming the constant current source 3 is set so as to flow the current I,
A constant voltage E1 is applied to the terminal 4 of the switching circuit 7 including the differential pair transistors Q14 and Q15, and the sampling pulse shown in FIG. 6 (b) is applied to the terminal 5.
The collector of the transistor Q14 is connected to the transistor Q16 forming a current mirror circuit as shown.
The current value of the transistor Q17, which forms a current mirror circuit together with the transistor Q16, is set so as to output the current I. The collector of the transistor Q17 is connected to the (f) point, which is the midpoint of connection between the differential circuit 6 and the constant current source 3. Resistors R4 and R5 divide the power supply voltage Vcc of the power supply line 20 to form transistors Q1 and Q5.
A bias voltage is applied to the base of No. 13.

In this sample hold circuit, first, the transistor Q14 is turned on during the high potential period of the sampling pulse.
Since the FF and the transistor Q15 are turned on and the transistors Q16 and Q17 are turned off, the transistor Q
No current flows from point 17 to point (f), so the constant current source 3
Current I flows to the differential circuit 6. The differential circuit 6 derives the input signal applied to the input terminal 1 to the output terminal 2 and stores the signal charge in the capacitor C1. Next, during the low potential period of the sampling pulse (b), the transistor Q14 is turned on.
Since N and the transistor Q15 are turned off, the transistors Q16 and Q17 operate and the current I is supplied from the transistor Q17 to the point (f). Since this current I becomes the current I flowing through the low current source 3, no current flows in the differential circuit 6 and the differential circuit 6 is turned off. During this OFF state, the capacitor C1 has a high impedance and holds the accumulated charge.

The embodiments of FIGS. 3 and 4 are obtained by replacing the transistors of FIGS. 1 and 2 with transistors of the opposite conductivity type, and are substantially the same as those of FIGS.

[0016]

As described above, according to the present invention, the differential circuit and the constant current source are only connected in cascade, and the circuit supplying the current to these connection points is connected to the outside of the cascade connection circuit. Therefore, the number of stages of transistors cascade-connected between the power supply line and the ground is reduced, and a sample-and-hold circuit that operates even when the power supply voltage is low is realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a sample hold circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a sample hold circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a sample hold circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a sample and hold circuit according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional example.

FIG. 6 is a circuit diagram showing a signal waveform given to a sample hold circuit.

[Explanation of symbols]

 1 Input Terminal 2 Output Terminal 3 Constant Current Source 6 Differential Circuit C1 Capacitor

Claims (1)

[Claims] 1. A constant current source, a differential circuit forming a switch unit connected to the constant current source, a holding capacitor connected to an output terminal of the differential circuit, and a constant circuit connected to the differential circuit. A current having the same value as the output current of the constant current source is output to the connection point of the current source except during the sampling period, and a small current for turning on the differential circuit is output during the sampling period or no current is output to the connection point. A sample and hold circuit consisting of a circuit and.