JPH05205495A - Amplifying circuit - Google Patents

Abstract

PURPOSE:To prevent occurrence of input and output offsets at the time of on/off transient response by turning off a single end circuit simultaneously with an amplifying differential pair by employing a bypass current when a current switch is off. CONSTITUTION:An amplifier 1 current-amplifies input signals, differential-outputs and single-ends the differential output current through a single end circuit 2. At that time, a bias current of the amplifier 1 is turned on/off with a current path switch circuit SW and the circuit 2 is simultaneously turned off with the amplifying differential pair by using the current at the time of off. By this, the output current is cut earlier than that the circuit 2 discharges accumulated charges through its internal discharge path, prevents an excess output current from flowing in the next stage elements such as a holding capacitance and prevents the occurrence of input/output offset currents at the time of transient response.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit that performs current amplification and single-ended output, and has improved transient response during on / off.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional amplifier circuit having a sample and hold circuit. Transistors Q3 and Q
4 constitutes a differential pair, and the input voltage Vi inputted from the input Vin to the base of the transistor Q3 is converted into a current by the differential pair transistors Q3 and Q4. Of the converted current, the collector current of the transistor Q3 is converted into the transistor Q5,
Current mirror circuit CM consisting of Q6 and resistors R1 and R2
, And is single-ended with the collector current of the transistor Q4 to flow to the holding capacitor C1. By feeding back the voltage of the capacitor C1 to the base of the transistor Q4, an output voltage Vo equal to the input voltage Vi is output V
Occurs on out.

Switching between the sample operation and the hold operation is performed in the current switch circuit SW of the transistors Q1 and Q2. Transistor Q1 turns on during sample operation,
The transistors Q3 to Q6 are activated. During hold operation, transistor Q2 turns on and transistor Q3
The circuit of Q6 is cut off to maintain the capacitance voltage of the capacitor C1.

In the transition from the sample operation to the hold operation, the current of the transistor Q1 is cut off and the collector currents of the transistors Q3 and Q4 are simultaneously turned off. Since accumulated charges remain in the bases of the transistors Q5 and Q6, they are not turned off at the same time as the transistor Q4. Since the accumulated current is discharged by the base currents of the transistors Q5 and Q6, the transistor Q5 is turned off for the first time. Therefore, after the transistor Q4 is turned off, a slight current flows from the transistor Q6. Then, a charging current flows through the capacitor C1 and holds a voltage slightly higher than the sampled voltage, which causes a problem that an input / output offset occurs.

[0005]

In the conventional amplifier circuit for current amplification and single-ended output described above, when the sample operation is shifted to the hold operation, the transistor Q
1, Q3 and Q4 are cut off at the same time. However, since the accumulated electric charge remains in the bases of the transistors Q5 and Q6, the transistors Q5 and Q6 do not turn off at the same time as the transistor Q4, and a slight current flows from the transistor Q6 to the capacitor C1 to hold a voltage higher than the sampled voltage. Will be done. This caused an I / O offset. An object of the present invention is to provide an amplifier circuit that does not generate input / output offset during transient response.

[0006]

According to the present invention, a single-ended circuit is turned off at the same time as an amplification differential pair by using a bypass current when the current switch is turned off.

[0007]

By means of the above means, the single-ended circuit is controlled by the bypass current when the current switch is off, so the output current can be cut earlier than the single-ended circuit discharges the accumulated charge in the internal discharge path, and the holding current can be maintained. It is possible to prevent excess output current from flowing to the next stage element such as a capacitor.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows one embodiment of the present invention. A current path switch circuit SW is provided in the path through which the bias current I0 flows. One of the output of the switch circuit SW is the second input of the amplifier 1 which has supplied the input signal to the first input, and the other is the single end circuit 2. Connect each. In the single-ended circuit 2, the output of the switch SWa is input as a control signal, the differential output from the amplifier 1 is input as a signal, and the single-ended signal from the output is output as an amplified output.

FIG. 2 is a circuit diagram specifically showing FIG. The differential pair composed of transistors Q3 and Q4 has an input V
The input voltage Vi supplied to in is converted into a current and output in the differential mode. Transistors Q5, Q6, resistors R1 and R
In the current mirror circuit CMa consisting of 2, the transistor Q
The collector current of 3 is turned back and added to the collector current of the transistor Q4 to make a single end. The transistors Q3 to Q6 form the amplifier 1.

The single-ended current is passed through the holding capacitor C1 and the charging voltage of the capacitor C1 is fed back to the base of the transistor Q4, whereby the sample-hold circuit 2 is constructed. Switching between the sample operation and the hold operation is performed by a differential pair of transistors Q1 and Q2. During the sample operation, the transistor Q1 is on, and the bias current Io flows through the amplifier circuit 1. At the time of hold operation, the bias current Io is bypassed and is flown to the emitter of the transistor Q6. The emitter of the transistor Q6 corresponds to the control input terminal of the single end circuit.

At the time when the transistor Q1 of the current path switch circuit SW is off and the transistor Q2 is on, the transition from the sample operation to the hold operation occurs.
And Q4 turns off. At this time, the bias current Io is flowing in the transistor Q2, and all of this current flows through the resistor R
Flow to 2. Even if there are accumulated charges in the bases of the transistors Q5 and Q6, the emitter potential of the transistor Q6 decreases, so that the transistor Q6 is cut off and the output current becomes zero.

Therefore, the transistor Q4 is turned off and the transistor Q6 is turned off at the same time, and the transient current that gives an offset to the capacitor C1 does not flow. Therefore, the occurrence of input / output offset can be prevented.

FIG. 3 shows a second embodiment of the present invention. In this embodiment, the single-ended circuit of the transistors Q5 and Q6 of the circuit shown in FIG. 2 is replaced with a circuit of transistors Q7 to Q12, and the basic operation is the same as that of FIG.

The collector currents of the transistors Q3 and Q4 are supplied to the current mirror circuit CM of the transistors Q7 and Q10.
Then, the collector current of the transistor Q4 is returned by the rent mirror circuits CMc and CMd of the transistors Q8 and Q9 and the transistors Q11 and Q12. The collectors of the transistors Q10 and Q12 are connected and the collector currents of these transistors Q10 and Q12 are added to make a single end. The current path switch circuit SWb for the bias current Io is composed of transistors Q1, Q2 and Q13. The collectors of the transistors Q2 and Q13 are connected to the transistor Q9,
Connect to the emitter of Q10.

In such a case, there are two sets of current mirror circuits CMb and CMc in which accumulated charges remain, and it is necessary to cut them off at the same time. Further, since the NPN transistor is generally faster than the PNP transistor, this is an example in which the PNP current mirror circuits CMb and CMc are mainly controlled. In this case, the control input terminal of the single-ended circuit becomes the emitters of the transistors Q9 and Q10.

At the time of transition from the sample operation to the hold operation, the outputs of the current mirror circuits CMb and CMc composed of PNP transistors all serve as an offset current generating source, so that the bypass current is divided into two and the transistor Q is divided.
The bypass current of 2 cuts off the transistor Q9, and the collector current of the transistor Q13 cuts off the transistor Q10.

Also in this embodiment, like the above-mentioned embodiment, no current for giving an offset flows after the end of the sampling operation. The single-ended circuit shown in this embodiment is more useful than a sample-hold circuit because it has a wide output dynamic range and can be used as a normal amplifier circuit.

FIG. 4 shows a third embodiment of the present invention. In this embodiment, instead of the transistor Q13 of the current path switch circuit SWb of FIG.
A current mirror circuit CMe composed of 14 and Q15 and a resistor R9 is provided.

With this arrangement, when a current flows through the transistor Q2, a bypass current is first supplied to the emitter of the transistor Q10 via the transistor Q14, so that the transistor Q10 can be cut off. Since the transistors Q14 and Q15 are the current mirror circuit CMe, the output current of the transistor Q15 increases the emitter potential of the output transistor Q12 of the NPN current mirror circuit, and the transistor Q12 is cut off. Even in this case, the output currents of the transistors Q10 and Q12 can be cut off quickly, and the generation of offset current can be prevented.

The present invention is not limited to the above-described embodiments, but for example, in the circuits of the respective embodiments shown in FIGS. 2 to 4, the bias current switch circuits are described as independent, but the emitters of the differential pair transistors Q3 and Q4 are described. Alternatively, a switch may be provided. In this case, there is an effect of reducing the number of elements. Specifically, the transistor Q1 in FIG. 2 may be deleted and the emitter of the transistor Q2 may be connected to the common emitter of the transistors Q3 and Q4. However, it is necessary to consider that the input level of the switch voltage can be switched with respect to the input voltage Vi.

[0021]

As described above, according to the amplifier circuit of the present invention, at the time of shifting from the sample operation to the hold operation, the transient current that gives the offset to the holding capacitor does not flow, so that the transient response is not generated. It is possible to prevent the occurrence of input / output offset.

[Brief description of drawings]

FIG. 1 is a system diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram specifically showing FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a conventional amplifier circuit.

[Explanation of symbols]

1 ... Amplifier, 2 ... Single end circuit, Io ... Bias current, SWa ... Current path switch circuit.

Claims (2)

[Claims] 1. An amplifier that current-amplifies an input signal and differentially outputs it, a unit that single-ends a differential output current of the amplifier, a unit that turns on / off a bias current of the amplifier, and an on-off unit. An amplifier circuit comprising: a means for using a current at the time of off as a control signal of the single end means. 2. The single-ended means comprises at least one current mirror circuit, and has means for cutting off the output current of the current mirror circuit by the off current of the on / off means. The amplifier circuit according to claim 1, wherein: