JPH01278108A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To increase both maximum output voltage and current amplitudes by using a specific transistor as an output stage. CONSTITUTION:A current mirror circuit consisting of transistors TRQ3-Q6 is connected to a differential connection circuit consisting of a pair of TRQ1 and Q2 and a TRQ12 for constant current source as an active load. While an output stage contains the TRQ14-Q23 and a resistance R1. As a result, the maximum output voltage amplitude is increased by about double as much as the base-emitter voltage. While the output current performs the B-class amplification, i.e., flows to both TRQ21 and Q19 every half cycle. Thus it is possible to obtain a differential amplifier circuit that has large maximum output voltage and current amplitudes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential amplifier circuit, and more particularly to a differential amplifier circuit constituted by transistor circuits.

[Conventional technology]

Differential amplifier circuits that amplify the difference between two input voltages are widely used in input stages of amplifier devices and the like.

FIG. 3 is a typical conventional circuit diagram of a differential amplifier circuit.

In the conventional example shown in FIG. 3, a current mirror circuit made up of transistors Q3 to Q6 is connected as an active load to a differential connection circuit made up of a pair of transistors Ql and Q2 and a constant current source transistor Q12. The output stage includes transistors Q7 to Qll. The base of the transistor Q1 is connected to the signal input terminal VINI, the collector is connected to the base and collector of the transistor Q3, and the emitter is connected to the emitter of the transistor Q2 and the collector of the transistor Q12. The base of transistor Q2 is connected to signal input terminal VIN2, and the base of transistor Q3
The emitter of is connected to the collector of transistor Q4,
The base of the transistor Q4 is connected to the base and collector of the transistor Q6, and the emitter of the transistor Q4 is connected to the emitter of the transistor Q6 and the positive power supply terminal V. Further, the base of Q5 is connected to the base of transistor Q3, the collector to the collector of transistor Q2, and the emitter to the base and collector of transistor Q6.

On the other hand, the base of the transistor Q7 is connected to the collector of the transistor Q5 and the collector of the transistor Qll, the collector is connected to the emitter of the transistor Q8, and the emitter is connected to the collector signal output terminal V□g7 of the transistor Q13. The base of the transistor Q8 is connected to the collector of the transistor QIO and the base of the transistor Qll, and the collector is connected to the positive power supply terminal 2. The base of transistor Q9 is connected to the base of transistor QIO and the collector of transistor Q9, the collector is connected to the emitter of transistor Qll, and the emitter is connected to transistor QIO.
and the positive power supply terminal V+. Further, the base of the transistor Q12 is connected to the base of the transistor Q1B and the reference power supply terminal V ref, and the emitter is connected to the emitter of the transistor Q13 and the negative power supply terminal V-.

In FIG. 3, currents IL flowing through transistors Q7 and Q8 are approximately equal, and transistors Q7. Q8
The base current and the collector current of transistors QIO and Q41 are approximately equal, and a current of IL/β flows. However, β is the current amplification factor. Therefore, transistor Q9. Q
I.O.

Almost equal current IL/β is passed through the input and output terminals of the current mirror circuit composed of transistor Qll to transistor Q7.
．． Since it is supplied to the base of Q8, the transistor Ql
, the currents flowing into the collectors of Q2 are almost equal, and the current offset is well controlled due to the influence of the load connected to the output terminal.

[Problem to be solved by the invention]

The conventional differential amplifier circuit described above has transistors Q3. Q
4. Q5. A current mirror circuit consisting of transistor Q6 and transistor Q7. Q13 limits the maximum output amplitude.

The maximum output voltage amplitude range is the signal output terminal ■. V + (V !IEQ6+ V
5atQ5+ V agQj ) to signal output terminal v
V −+ V matQ1 which is the low side voltage of oUτ
Up to 3. However, VBBQ6 is the transistor Q6
VmaLQ5 is the collector-emitter saturation voltage of transistor Q5, VBEQ7 is the base-emitter voltage of transistor Q7, Vmat
Q13 is the collector-emitter saturation voltage of transistor Q13. Furthermore, since the output current is class-A amplified and flows over the entire cycle, the maximum output current amplitude is small.

An object of the present invention is to provide the above-mentioned conventional differential amplifier circuit with
It is an object of the present invention to provide a differential amplifier circuit in which the current offset of a pair of differentially connected transistors can be reduced and the maximum output voltage amplitude and maximum output current amplitude can be increased.

[Means to solve the problem]

The differential amplifier circuit of the present invention connects the emitters of the first and second transistors (Ql and Q2) to the first constant current source (Q
12), the base of the first transistor is connected to a first signal input terminal, the base of the second transistor is connected to a second signal input terminal, and a pair of transistors is formed of a plurality of transistors. In a differential amplifier circuit, an input terminal of a current mirror circuit having an input and an output terminal is connected to the collector of the first transistor, and an output terminal is connected to the collector of the second transistor. A third transistor (Q1) is connected to the output terminal of the circuit, has its collector connected to the common connection point between the collector and base of the first reverse conductive transistor (Q18), and has its emitter connected to the voltage drop element (R1).
7) and a second reverse conductive transistor (Q19) whose base is connected to the collector of this third transistor and whose collector is connected to the negative power supply terminal, whose collector and base are commonly connected and whose emitter is connected to the third transistor. A fourth transistor (Q20) is connected to the emitter of the first reverse conductive transistor, the base is connected to the collector of this fourth transistor, the collector is connected to the positive power supply terminal, and the emitter is connected to the second reverse conductive transistor.
a fifth transistor (Q21) connected to the emitter of the reverse conductive transistor; and a third reverse conductive transistor (Q23) whose emitter is connected to the positive power supply terminal and whose collector is connected to the base of the fifth transistor. ), a fourth reverse conductive transistor (Q22) whose emitter is connected to the positive power supply terminal and whose collector is connected to the second constant current source (Q16), and whose base is connected to the fourth reverse conductive transistor (Q22). a fifth reverse conductive transistor (Q15) whose collector is connected to the fourth reverse conductive transistor, whose emitter is also connected to the base of the fourth reverse conductive transistor, and whose collector is connected to the reference potential; a sixth reverse conductive transistor (Q
14), and is configured by connecting the emitter of the fifth transistor to the signal output terminal.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the differential amplifier circuit of the present invention. The embodiment shown in FIG. 1 includes a pair of transistors Ql,
A current mirror circuit composed of transistors Q3 to Q6 is connected as an active load to a differential connection circuit composed of transistor Q2 and constant current source transistor Q12, and transistors Q14 to Q23 . It is configured to include a resistor R1. The base of transistor Q1 is the signal input terminal V
INI, its collector is connected to the base and collector of transistor Q3, and its emitter is connected to the emitter of transistor Q2 and the collector of transistor Q16. The base of transistor Q2 is connected to the signal input terminal VIN2, the emitter of transistor Q3 is connected to the collector of transistor Q4, the base of transistor Q4 is connected to the base and collector of transistor Q6, and the emitter is connected to the emitter of transistor Q6. Connected to power supply terminal V+.

The base of transistor Q5 is connected to the base of transistor Q3, the collector to the collector of transistor Q2, and the emitter to the base and collector of transistor Q6. On the other hand, the base of transistor Q17 is connected to the collector of transistor Q5 and the collector of transistor Q14, the collector is connected to the base and collector of transistor Q18, and the base of transistor Q19, and the emitter is connected to the negative power supply terminal V- via resistor R1. ing. The emitter of transistor Q18 is connected to the emitter of transistor Q20. The collector of the transistor Q19 is connected to the negative power supply terminal -, and the emitter is connected to the emitter of the transistor Q21 and the signal output terminal V o (, D). The base of the transistor Q21 is connected to the base and collector of the transistor Q20, and the collector of the transistor Q23. In addition, the collector is connected to the positive power supply terminal ■.The base of transistor Q22 is connected to the base of transistor Q23, the emitter of transistor Q14, and the emitter of transistor Q15, and the collector is connected to the base of transistor Q14 and the base of transistor Q15. Transistor Q 1.
The collector and emitter of transistor Q23 are connected to the emitter of transistor Q23 and the positive voltage terminal V+. The collector of transistor Q15 is grounded to a reference potential. The base of the transistor Q12 is connected to the base of the transistor Q16 and the reference power terminal V r er, and the emitter is connected to the emitter of the transistor Q16 and the negative power terminal -.

In FIG. 1, transistor Q14. Q15゜Q22.
Due to the current mirror circuit formed by Q2B, a current approximately equal to the collector current of transistor Q16 flows to the collector of transistor Q17. Also, transistor Q22. The base current of Q2B and transistor Q14. Q
Since the base current of the transistor Q17 is supplied by the collector current of the transistor Q14, the collector current of the transistor Q1 is approximately equal to the collector current of the transistor Q15.

The currents flowing to the collector of Q2 are almost equal, and the current offset is well taken care of.

The range of the maximum output voltage amplitude is from the high side voltage of the signal output terminal vout V + V 5atQ21 to the low side voltage of the signal output terminal VOUT V - + V aatQ19
Until. However, VsatQ21 is the transistor Q
21 collector-emitter saturation voltage, VmatQ+9
is the collector-emitter saturation voltage of transistor Q19.

Therefore, the maximum output voltage amplitude is approximately 2 of VBH compared to the conventional one.
This means that the size can be doubled. Further, since class B amplification is performed, the output current flows through transistors Q21 and Q19 every half cycle, so the maximum output current amplitude can be increased.

FIG. 2 is a circuit diagram of another embodiment of the differential amplitude circuit of the present invention. In the embodiment shown in FIG. 2, the collector of transistor Q14 in the embodiment shown in FIG.
5, and the emitter of transistor Q4 and the positive power supply terminal■. A resistor R2 is connected between the transistor Q6 and the positive power supply terminal V+, and a resistor R3 is connected between the emitter of the transistor Q6 and the positive power supply terminal V+.

Here, as the operating conditions for the embodiment of FIG. 2, the resistors R2,
R3 is T EQ6 R3+ VBEQ6> VBEQ22 +
A resistance value that satisfies the condition of VmatQ14 is set. However, IEQ6 is the emitter current of the transistor Q6, VBεQ22 is the base-emitter voltage of the transistor Q22, and Vsato14 is the collector-emitter saturation voltage of the transistor Q14.

In the embodiment shown in FIG. 1, the base current of the transistor Q17 is directly supplied from the collector of the transistor Q14, but as shown in FIG. Transistors Q1 and Q2 as in the embodiment shown
The effect of reducing the collector current offset of is the same. Furthermore, the embodiment shown in FIG. 2 has the effect that the maximum output voltage amplitude and the maximum output current amplitude can be increased similarly to the embodiment shown in FIG.

〔Effect of the invention〕

As explained above, according to the differential amplifier circuit of the present invention, the current offset of a pair of differentially connected transistors can be reduced, and the differential amplifier circuit can have a large maximum output voltage amplitude and a large maximum output current amplitude. The effect is that it can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment of the present invention, and FIG. 3 is a typical conventional circuit diagram of a differential amplifier circuit. Q1-Q23...Transistor, R1-R3...Resistor, ■Y...Positive power supply terminal, ■-...Negative power supply terminal, V
INI + V IN2...Signal input terminal, VOU↑
... Signal output terminal, V r e f ... Reference power supply terminal.

Claims (1)

[Claims] The emitters of the first and second transistors (Q1 and Q2) are connected to a first constant current source (Q12), and the first
The base of the transistor is connected to the first signal input terminal, the base of the second transistor is connected to the second signal input terminal, and the current transistor is composed of a plurality of transistors and has a pair of input and output terminals. connecting an input terminal of the mirror circuit to the collector of the first transistor;
In a differential amplifier circuit in which the output terminal is connected to the collector of the second transistor, the base is connected to the output terminal of the current mirror circuit, and the collector is connected to the collector and base of the first reverse conductive transistor (Q18). A third transistor (Q17) connected to the common connection point and having its emitter connected to the voltage drop element (R1) and its base connected to this third
A second reverse conductive transistor (Q19) connected to the collector of the transistor and whose collector is connected to the negative power supply terminal.
and a fourth transistor whose collector and base are commonly connected and whose emitter is connected to the emitter of the first reverse conductive transistor.
transistor (Q20), and a fifth transistor (Q21) whose base is connected to the collector of the fourth transistor, whose collector is connected to the positive power supply terminal, and whose emitter is connected to the emitter of the second reverse conductivity transistor. )and,
a third reverse conductive transistor (Q23) whose emitter is connected to the positive power supply terminal and whose collector is connected to the base of the fifth transistor; a fourth reverse conductive transistor (Q22) connected to the current source (Q16), and a base connected to the collector of this fourth reverse conductive transistor;
A fifth reverse conductive transistor (Q15) whose emitter is also connected to the base of the fourth reverse conductive transistor and whose collector is connected to the reference potential, and whose base is connected to the collector of the fourth reverse conductive transistor. , a sixth transistor whose emitter is also connected to the base of the fourth reverse conductive transistor and whose collector is connected to the base of the third transistor.
and a reverse conductive transistor (Q14), the fifth
A differential amplifier circuit characterized in that the emitter of a transistor is connected to a signal output terminal.