JP2536156B2 - Absolute value circuit - Google Patents
Absolute value circuitInfo
- Publication number
- JP2536156B2 JP2536156B2 JP1146343A JP14634389A JP2536156B2 JP 2536156 B2 JP2536156 B2 JP 2536156B2 JP 1146343 A JP1146343 A JP 1146343A JP 14634389 A JP14634389 A JP 14634389A JP 2536156 B2 JP2536156 B2 JP 2536156B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- transistor
- absolute value
- output
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は絶対値回路に係り、特に入力電圧の絶対値を
低インピーダンスの電圧で出力する絶対値回路に関す
る。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute value circuit, and more particularly to an absolute value circuit that outputs the absolute value of an input voltage as a low impedance voltage.
第５図は、従来のこの種の絶対値回路の回路図であ
る。第５図を参照すると、正転入力が基準電位に接続さ
れた第１の演算増幅器３と、アノードがこの出力に接続
され、カソードがこの反転入力に接続された第１のダイ
オード６と、カソードがこの出力に接続された第２のダ
イオード５と、演算増幅器３の反転入力とダイオード５
のアノードとの間に接続された第１の抵抗８と、VIN信
号入力端子１と演算増幅器３の反転入力端との間に接続
された第２の抵抗７と、正転入力が基準電位に接続され
た第２の演算増幅器４と、ダイオード５のアノードと演
算増幅器４の反転入力との間に接続された第３の抵抗10
と、反転入力と出力との間に接続された第４の抵抗11
と、VIN信号入力端子１と演算増幅器４の反転入力との
間に接続された第５の抵抗９とから構成されている。そ
してVIN信号を入力端子１に印加し、出力にVIN信号の絶
対値電圧VOUTを出力するようにしたものである。次にこ
の従来回路の動作説明を行う。まず、VIN信号が正の場
合を考えるとこの時ダイオード５がオンし、ダイオード
６がオフする。従って、この時の出力電圧VOUT(+)は、
次式となる。FIG. 5 is a circuit diagram of a conventional absolute value circuit of this type. Referring to FIG. 5, a first operational amplifier 3 having a non-inverting input connected to a reference potential, a first diode 6 having an anode connected to the output and a cathode connected to the inverting input, and a cathode The second diode 5 connected to this output, the inverting input of the operational amplifier 3 and the diode 5
A first resistor 8 connected between the anode of the second resistor 7 and a second resistor 7 connected between the V IN signal input terminal 1 and the inverting input terminal of the operational amplifier 3, and the normal input of the second resistor 7. And a third resistor 10 connected between the anode of the diode 5 and the inverting input of the operational amplifier 4.
And a fourth resistor 11 connected between the inverting input and the output.
And a fifth resistor 9 connected between the V IN signal input terminal 1 and the inverting input of the operational amplifier 4. Then, the V IN signal is applied to the input terminal 1, and the absolute value voltage V OUT of the V IN signal is output to the output. Next, the operation of this conventional circuit will be described. First, considering that the V IN signal is positive, the diode 5 is turned on and the diode 6 is turned off at this time. Therefore, the output voltage V OUT (+) at this time is
It becomes the following formula.
ここで、R1は抵抗８の抵抗値,R2は抵抗７の抵抗値,R3
は抵抗10の抵抗値,R4は抵抗11の抵抗値,R5は抵抗９の抵
抗値である。 Here, R 1 is the resistance value of the resistor 8, R 2 is the resistance value of the resistor 7, and R 3
Is the resistance value of the resistor 10, R 4 is the resistance value of the resistor 11, and R 5 is the resistance value of the resistor 9.
今、R1＝R2＝R3/2＝R4＝R5とすると、前記（）式は次
のようになる。Assuming that R 1 = R 2 = R 3 /2 = R 4 = R 5, wherein () equation becomes:.
VOUT(+)＝2VIN−VIN＝VIN ……（２） 次にVIN信号が負の場合を考えると、この時ダイオー
ド５がオフし、ダイオード６がオンする。従って、演算
増幅器３の出力はダイオード６の順方向電圧VFであり、
ダイオード５がオフしているから、抵抗8,10には電流が
流れない。従って、この時の出力電圧VOUT(-)は次式と
なる。V OUT (+) = 2V IN −V IN = V IN (2) Next, considering the case where the V IN signal is negative, the diode 5 is turned off and the diode 6 is turned on at this time. Therefore, the output of the operational amplifier 3 is the forward voltage V F of the diode 6,
Since the diode 5 is off, no current flows through the resistors 8 and 10. Therefore, the output voltage V OUT (-) at this time is given by the following equation.
ここで、前記の条件と同様に、R4＝R5なら、前記
（３）式は次のようになる。 Here, similar to the above-mentioned condition, if R 4 = R 5 , the above equation (3) becomes as follows.
VOUT(-)＝−VIN ……（４） 負のVIN信号の絶対値が正の値に変換される。前記
（２），（４）式より、入力信号VINと出力電圧VOUTの
関係は次のようになる。V OUT (-) = -V IN (4) The absolute value of the negative V IN signal is converted to a positive value. From the expressions (2) and (4), the relationship between the input signal V IN and the output voltage V OUT is as follows.
VOUT＝|VIN| ……（５） このように、VINが正の時も負の時も出力は正にな
り、結果として入力信号の絶対値が出力に得られる。V OUT = | V IN | (5) In this way, the output becomes positive regardless of whether V IN is positive or negative, and as a result, the absolute value of the input signal is obtained at the output.
前述した従来の絶対値回路は、演算増幅器3,4が２個
と、ダイオード5,6が２個、そして相対精度を必要とす
る抵抗7,8,9,10,11が５本も必要であるから、多くの高
価な部品を必要とする欠点があった。又、回路電流も、
２個の演算増幅器3,4で消費する電流分の他、５本の抵
抗で消費する電流分もあり、消費電力が大きいという欠
点もあった。The above-mentioned conventional absolute value circuit requires two operational amplifiers 3 and 4, two diodes 5 and 6, and five resistors 7,8,9,10,11 that require relative accuracy. Therefore, it has the drawback of requiring many expensive parts. Also, the circuit current
In addition to the amount of current consumed by the two operational amplifiers 3 and 4, there is also the amount of current consumed by the five resistors, which has the drawback of high power consumption.
本発明の目的は、前記欠点が解消され、構成部品が少
なくて済み、消費電力も低減させた絶対値回路を提供す
ることにある。An object of the present invention is to provide an absolute value circuit in which the above-mentioned drawbacks are eliminated, the number of components is reduced, and the power consumption is reduced.
本発明の絶対値回路の構成は、反転入力がベースに印
加される第１トランジスタ、及び第１の正転入力がベー
スに印加される第２のトランジスタを有する差動増幅器
と、前記第２のトランジスタのエミッタ及びコレクタに
各々共通接続され、かつベースに第２の正転入力が印加
される第３のトランジスタと、前記第１のトランジスタ
のコレクタを入力とする演算増幅器と、前記反転入力と
前記演算増幅器の出力との間に接続された第１の抵抗
と、一端が前記反転入力に接続された第２の抵抗とを備
え、前記第１の正転入力と前記第２の抵抗の他端とを接
続して信号入力端子となし、前記第２の正転入力を所定
の基準電圧に接続したことを特徴とする。The configuration of the absolute value circuit of the present invention includes a differential amplifier having a first transistor to which an inverting input is applied to the base and a second transistor to which a first non-inverting input is applied to the base, and the second amplifier. A third transistor commonly connected to the emitter and collector of the transistor and having a second normal input applied to the base, an operational amplifier having the collector of the first transistor as an input, the inverting input and the A first resistor connected between the output of the operational amplifier and a second resistor having one end connected to the inverting input, and the first non-inverting input and the other end of the second resistor. Are connected to form a signal input terminal, and the second non-inverting input is connected to a predetermined reference voltage.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の絶対値回路を示す回路図
である。FIG. 1 is a circuit diagram showing an absolute value circuit according to an embodiment of the present invention.
第１図を参照すると、本実施例の絶対値回路は、エミ
ッタとコレクタが各々相互接続されたNPNトランジスタ2
2,23と、エミッタがトランジスタ22,23のエミッタに共
通接続され、トランジスタ22,23と差動増幅器を構成す
るNPNトランジスタ21と、トランジスタ21,22とトランジ
スタ23の差動段の能動負荷として働くカレントミラー回
路29と、前記能動負荷によりシングル・エンドに変換さ
れた信号を、電圧及び電流増幅する増幅段31と、共通接
続されたトランジスタ21,22,23のエミッタと負電源V-と
の間に接続されて前記差動段バイアス用としての定電流
源IOと、トランジスタ21のベースと、演算増幅器31の出
力端子２との間に接続された抵抗値RFを有する抵抗27
と、入力端子１とトランジスタ21のベース間に接続され
た抵抗値RSを有する抵抗28とを含み、構成されている。Referring to FIG. 1, the absolute value circuit of this embodiment has an NPN transistor 2 having an emitter and a collector interconnected with each other.
2,23 and the emitter are commonly connected to the emitters of the transistors 22 and 23, and serve as an NPN transistor 21 forming a differential amplifier with the transistors 22 and 23, and an active load of the differential stage of the transistors 21 and 22 and the transistor 23. Between the current mirror circuit 29, an amplification stage 31 for amplifying the signal converted into single end by the active load in voltage and current, and between the emitters of the transistors 21, 22 and 23 commonly connected and the negative power supply V −. A resistor 27 having a resistance value R F connected to the constant current source I O for biasing the differential stage, the base of the transistor 21 and the output terminal 2 of the operational amplifier 31.
And a resistor 28 having a resistance value R S connected between the input terminal 1 and the base of the transistor 21.
そして、共通接続されたトランジスタ22,23のコレク
タは、前記カレントミラー回路29の入力端子に接続さ
れ、トランジスタ21のコレクタは、カレントミラー回路
29の出力端子に接続されている。又、カレントミラー回
路29の共通端子30は、正電源端V+に接続される。トラン
ジスタ23のベースは基準電位に接続され、トランジスタ
22のベースは抵抗28の一端と、入力端子１に共通接続さ
れる。そして演算増幅器31の出力が、本絶対値回路の出
力端子２となる。The collectors of the transistors 22 and 23 connected in common are connected to the input terminal of the current mirror circuit 29, and the collector of the transistor 21 is connected to the current mirror circuit.
Connected to 29 output terminals. The common terminal 30 of the current mirror circuit 29 is connected to the positive power supply terminal V + . The base of the transistor 23 is connected to the reference potential and
The base of 22 is commonly connected to one end of the resistor 28 and the input terminal 1. The output of the operational amplifier 31 becomes the output terminal 2 of the absolute value circuit.
ここで、前記入力端子１に印加される入力信号VINが
正の時、トランジスタ23はカットオフし、入力段はトラ
ンジスタ21,22の差動増幅動作をする。この時、トラン
ジスタ21のベース電位とトランジスタ22のベース電位
は、イマジナリーショートとなり、抵抗28に電流は流れ
ず、出力端子２の電位VOUT(+)は、VINと同じ電圧が出力
される。従って、全体として電圧フォロワ動作となる。
即ち、次式となる。Here, when the input signal V IN applied to the input terminal 1 is positive, the transistor 23 is cut off, and the input stage performs the differential amplification operation of the transistors 21 and 22. At this time, the base potential of the transistor 21 and the base potential of the transistor 22 become an imaginary short circuit, no current flows through the resistor 28, and the potential V OUT (+) of the output terminal 2 is the same voltage as V IN. . Therefore, the voltage follower operation is performed as a whole.
That is, the following equation is obtained.
VOUT(+)＝VIN ……（６） 次に、入力信号VINが負の時の動作を考える。この
時、トランジスタ22はカットオフとなり、入力段はトラ
ンジスタ21,23の差動増幅器動作をする。そして、トラ
ンジスタ21,23のベース電位は、イマジナリーショート
となり、トランジスタ23のベースはトランジスタ21のベ
ース電位と同じ基準電位となる。従って、全体として反
転アンプ動作となる。即ち、この時の出力電位をV
OUT(-)とすると、次式となる。V OUT (+) = V IN (6) Next, consider the operation when the input signal V IN is negative. At this time, the transistor 22 is cut off, and the input stage operates as a differential amplifier of the transistors 21 and 23. Then, the base potentials of the transistors 21 and 23 become imaginary short, and the base of the transistor 23 becomes the same reference potential as the base potential of the transistor 21. Therefore, the inverting amplifier operation is performed as a whole. That is, the output potential at this time is V
When OUT (-) , it becomes the following formula.
ここで、RS＝RFならば、次式が得られる。 Here, if R S = R F , the following equation is obtained.
VOUT(-)＝−VIN ……（８） （８）式は、負の入力電圧VINの反転、即ち正のVINが
得られたことを示す。よって前記（６），（８）式よ
り、入力信号VINが正の時も負の時も出力電圧VOUTは正
となり、しかも入力信号の絶対値と等しい値となる。従
って、すべての入力信号に対して出力電圧VOUTは、次式
となる。V OUT (−) = − V IN (8) Equation (8) shows that the negative input voltage V IN is inverted, that is, the positive V IN is obtained. Therefore, according to the equations (6) and (8), the output voltage V OUT is positive when the input signal V IN is positive or negative, and is equal to the absolute value of the input signal. Therefore, for all input signals, the output voltage V OUT is:
VOUT＝|VIN| ……（９） かくて、絶対値回路が実現できたことになる。この時
の入力信号VIN対出力電圧VOUTの特性図を第２図に示
す。第２図から明白なように、前記（９）式の通りとな
る。V OUT = | V IN | (9) Thus, the absolute value circuit has been realized. FIG. 2 shows a characteristic diagram of the input signal V IN and the output voltage V OUT at this time. As is clear from FIG. 2, the equation (9) is obtained.
本実施例は、従来の絶対値回路と異なり、相対精度を
必要とする抵抗は２本だけで、その他入力トランジスタ
を１個追加した演算増幅器１個で、高精度の絶対値回路
が構成できる。In this embodiment, unlike the conventional absolute value circuit, only two resistors require relative accuracy, and one operational amplifier with one additional input transistor can form a highly accurate absolute value circuit.
第３図は本発明の他の実施例の反転型の絶対値回路図
を示す回路図である。FIG. 3 is a circuit diagram showing an inverting type absolute value circuit diagram of another embodiment of the present invention.
第３図において、本実施例では、第１図におけるトラ
ンジスタ21,22,23を逆極性のPNPトランジスタ21′,2
2′,23′に置き換え、定電流源IOの極性も反転して、か
つ正電源V+と前記PNPトランジスタ21′,22′,23′の共
通接続されたエミッタとの間に接続される。前記PNPト
ランジスタの能動負荷として働くカレントミラー回路2
9′と共通端子30′は負電源V-端に接続される。In FIG. 3, in the present embodiment, the transistors 21, 22, 23 in FIG. 1 are replaced by PNP transistors 21 ', 2 of opposite polarity.
2 ', 23', the polarity of the constant current source I O is also inverted, and it is connected between the positive power supply V + and the commonly connected emitters of the PNP transistors 21 ', 22', 23 '. . Current mirror circuit 2 acting as an active load for the PNP transistor
9'and the common terminal 30 'are connected to the negative power supply V - terminal.
その他の接続は、第１図と同じであるので、その説明
を省略する。The other connections are the same as those in FIG. 1, and therefore their explanations are omitted.
本実施例において、入力信号VINが負の時、トランジ
スタ23′はカットオフとなり、入力段はトランジスタ2
1′,22′の差動増幅器動作をする。次に、入力信号VIN
が正の時はトランジスタ22′がカットオフとなり、入力
段はトランジスタ21′,23′の差動増幅器動作をする。In this embodiment, when the input signal V IN is negative, the transistor 23 'is cut off and the input stage is the transistor 2
1 ', 22' differential amplifier operation is performed. Next, input signal V IN
Is positive, the transistor 22 'is cut off and the input stage operates as a differential amplifier of the transistors 21' and 23 '.
基本動作は、第１図の場合と同様であるのでその他の
説明を省略する。結果として、入出力の関係式は、第４
図に示すように、次式となる。Since the basic operation is the same as that in the case of FIG. 1, other description will be omitted. As a result, the input / output relational expression is
As shown in the figure, the following equation is obtained.
VOUT＝−|VIN| ……（10） 即ち、入力電圧の絶対値の反転出力が得られる。V OUT =-| V IN | (10) That is, an inverted output of the absolute value of the input voltage is obtained.
以上説明したように、本発明は、２本の抵抗と、入力
差動段にトランジスタを１個追加した１個の演算増幅器
だけで済み、しかも高精度の絶対値回路が実現できると
いう効果があり、特に他の実施例にも示すように、入力
差動段のトランジスタの極性が反対にするだけで、反転
型の絶対値回路が簡単に実現できるという効果もある。As described above, the present invention requires only two resistors and one operational amplifier in which one transistor is added to the input differential stage, and has the effect of realizing a highly accurate absolute value circuit. In particular, as shown in other embodiments, there is also an effect that an inverting absolute value circuit can be easily realized by only reversing the polarities of the transistors in the input differential stage.
第１図は本発明の一実施例の絶対値回路の回路図、第２
図は第１図の回路図の入出力特性図、第３図は本発明の
他の実施例の絶対値回路の回路図、第４図は第２図の回
路図の入出力特性図、第５図は従来の絶対値回路図であ
る。 １……入力端子、２……出力端子、V+……正電源端子電
圧、V-……負電源端子電圧、VIN……入力端子電圧、V
OUT……出力端子電圧、29,29′……カレントミラー回
路、31,31′……増幅器、3,4……演算増幅器、IO……定
電流源、21,22,23……NPNトランジスタ、21′,22′,2
3′……PNPトランジスタ、７乃至11,27,28……抵抗、5,
6……ダイオード、30……共通端子。FIG. 1 is a circuit diagram of an absolute value circuit according to an embodiment of the present invention, and FIG.
1 is an input / output characteristic diagram of the circuit diagram of FIG. 1, FIG. 3 is a circuit diagram of an absolute value circuit of another embodiment of the present invention, and FIG. 4 is an input / output characteristic diagram of the circuit diagram of FIG. FIG. 5 is a conventional absolute value circuit diagram. 1 ...... input terminal, 2 ...... output terminals, V + ...... positive power supply terminal V oltage, V - ...... negative supply terminal V oltage, V IN ...... input terminal V oltage, V
OUT: Output terminal voltage, 29,29 '... Current mirror circuit, 31,31' ... Amplifier, 3,4 ... Operational amplifier, IO ... Constant current source, 21,22,23 ... NPN transistor , 21 ', 22', 2
3 ′ …… PNP transistor, 7 to 11,27,28 …… Resistance, 5,
6 …… Diode, 30 …… Common terminal.
Claims (1)
ンジスタ、及び第１の正転入力がベースに印加される第
２のトランジスタを有する差動増幅器と、前記第２のト
ランジスタのエミッタ及びコレクタに各々共通接続さ
れ、かつベースに第２の正転入力が印加される第３のト
ランジスタと、前記第１のトランジスタのコレクタを入
力とする演算増幅器と、前記反転入力と前記演算増幅器
の出力との間に接続された第１の抵抗と、一端が前記反
転入力に接続された第２の抵抗とを備え、前記第１の正
転入力と前記第２の抵抗の他端とを接続して信号入力端
子となし、前記第２の正転入力を所定の基準電圧に接続
したことを特徴とする絶対値回路。1. A differential amplifier having a first transistor having an inverting input applied to the base and a second transistor having a first non-inverting input applied to the base, and an emitter of the second transistor and A third transistor, which is commonly connected to each collector and to which a second non-inverting input is applied to the base, an operational amplifier having the collector of the first transistor as an input, the inverting input and the output of the operational amplifier And a second resistor having one end connected to the inverting input, the first forward input and the other end of the second resistor being connected to each other. An absolute value circuit in which the second non-inverting input is connected to a predetermined reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1146343A JP2536156B2 (en) | 1989-06-07 | 1989-06-07 | Absolute value circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1146343A JP2536156B2 (en) | 1989-06-07 | 1989-06-07 | Absolute value circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0310410A JPH0310410A (en) | 1991-01-18 |
| JP2536156B2 true JP2536156B2 (en) | 1996-09-18 |
Family
ID=15405558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1146343A Expired - Lifetime JP2536156B2 (en) | 1989-06-07 | 1989-06-07 | Absolute value circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2536156B2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5295153A (en) * | 1976-02-06 | 1977-08-10 | Nippon Chemical Ind | Phase sensitive detecting circuit |
| JPS6146566A (en) * | 1984-08-13 | 1986-03-06 | Victor Co Of Japan Ltd | Absolute value circuit |
| JPS62194468A (en) * | 1986-02-21 | 1987-08-26 | Hitachi Ltd | Rectifying circuit |
-
1989
- 1989-06-07 JP JP1146343A patent/JP2536156B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5295153A (en) * | 1976-02-06 | 1977-08-10 | Nippon Chemical Ind | Phase sensitive detecting circuit |
| JPS6146566A (en) * | 1984-08-13 | 1986-03-06 | Victor Co Of Japan Ltd | Absolute value circuit |
| JPS62194468A (en) * | 1986-02-21 | 1987-08-26 | Hitachi Ltd | Rectifying circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0310410A (en) | 1991-01-18 |
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