JPS6146566A - Absolute value circuit - Google Patents
Absolute value circuitInfo
- Publication number
- JPS6146566A JPS6146566A JP59169062A JP16906284A JPS6146566A JP S6146566 A JPS6146566 A JP S6146566A JP 59169062 A JP59169062 A JP 59169062A JP 16906284 A JP16906284 A JP 16906284A JP S6146566 A JPS6146566 A JP S6146566A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- signal
- absolute value
- output
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/02—Detecting, measuring or recording pulse, heart rate, blood pressure or blood flow; Combined pulse/heart-rate/blood pressure determination; Evaluating a cardiovascular condition not otherwise provided for, e.g. using combinations of techniques provided for in this group with electrocardiography or electroauscultation; Heart catheters for measuring blood pressure
- A61B5/024—Detecting, measuring or recording pulse rate or heart rate
- A61B5/0245—Detecting, measuring or recording pulse rate or heart rate by using sensing means generating electric signals, i.e. ECG signals
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
- A61B5/316—Modalities, i.e. specific diagnostic methods
- A61B5/318—Heart-related electrical modalities, e.g. electrocardiography [ECG]
- A61B5/332—Portable devices specially adapted therefor
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
- A61B5/316—Modalities, i.e. specific diagnostic methods
- A61B5/318—Heart-related electrical modalities, e.g. electrocardiography [ECG]
- A61B5/333—Recording apparatus specially adapted therefor
- A61B5/335—Recording apparatus specially adapted therefor using integrated circuit memory devices
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B2560/00—Constructional details of operational features of apparatus; Accessories for medical measuring apparatus
- A61B2560/04—Constructional details of apparatus
- A61B2560/0462—Apparatus with built-in sensors
- A61B2560/0468—Built-in electrodes
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は絶対値回路に係り、特に入力信号レベルの絶対
値を示す信号を生成出力する絶対値回路に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an absolute value circuit, and more particularly to an absolute value circuit that generates and outputs a signal indicating the absolute value of an input signal level.
従来の技術
第３図は従来の絶対値回路の一例の回路図を示す。同図
中、入力端子３１及び３２には夫々同一直流バイアス■
１が付与され、かつ、互いに逆極性の交流信号ｅｉ及び
−ｅｉが夫々入来する。入力端子３１に入来した交流信
号ｅｉはＮＰＮｔ−ランジスタ３３のベースへ入力され
、入力端子３２に入来した交流信号−ｅｉはＮＰＮトラ
ンジスタ３４のベースへ入力される。トランジスタ３３
及び３４の各エミッタは定電流源３５に夫々共通接続さ
れると共に、出力端子３６に接続されている。BACKGROUND OF THE INVENTION FIG. 3 shows a circuit diagram of an example of a conventional absolute value circuit. In the same figure, input terminals 31 and 32 have the same DC bias.
AC signals ei and -ei are applied with a value of 1 and have opposite polarities. The AC signal ei that has entered the input terminal 31 is input to the base of the NPN transistor 33, and the AC signal -ei that has entered the input terminal 32 is input to the base of the NPN transistor 34. transistor 33
and 34 are commonly connected to a constant current source 35, and are also connected to an output terminal 36.
また、トランジスタ３３及び３４の各コレクタは夫々電
源電圧入力端子３７に接続されている。入力交流信号ｅ
ｉ及び−ｅｉは振幅が大であり、トランジスタ３３及び
３４の一方が動作をしているときには他方が略オフの状
態となる。これにより、出力端子３６には入力交流信号
ｅｉ及び−ｅｉのうちど入らか電位の高い方が取り出さ
れる。Further, the collectors of the transistors 33 and 34 are respectively connected to a power supply voltage input terminal 37. Input AC signal e
i and -ei have large amplitudes, and when one of the transistors 33 and 34 is operating, the other is substantially off. As a result, whichever of the input AC signals ei and -ei has a higher potential is taken out from the output terminal 36 .
入力交流信号ｅｉ及び−ｅｉが正弦波の場合の各部の電
圧関係を第４図に示す。トランジスタ３３のベース電位
Ｖｅａ及びトランジスタ３４のベース電位Ｖｅｂは、同
一振幅で、かつ、互いに逆極性の交流信号ｅｉ 、−ｅ
ｉに同一の直流バイアスが付与された信号電位に等しく
、第４図（Ａ＞にＶｓａ及びＶｓｂで夫々示す如くにな
る。また、出力電圧Ｖｏは、トランジスタ３３及び３４
の各ベース・エミッタ間電圧を夫々ＶＢＥとすると、第
４図（Ｂ）に示す如くになる。ここで、Ｖｓａ。FIG. 4 shows the voltage relationship of each part when the input AC signals ei and -ei are sine waves. The base potential Vea of the transistor 33 and the base potential Veb of the transistor 34 are AC signals ei and -e having the same amplitude and opposite polarity.
The output voltage Vo is equal to the signal potential when the same DC bias is applied to i, as shown by Vsa and Vsb in FIG.
Letting each base-emitter voltage be VBE, the result will be as shown in FIG. 4(B). Here, Vsa.
■Ｂｂ及びＶｏは夫々次式で表わされる。(2) Bb and Vo are each expressed by the following formulas.
Ｖｓ ａ ＝Ｖ＋ ＋ｅｉ （１
）Ｖｓ ｂ ＝Ｖ＋ −ｅｉ （
２）Ｖｏ＝Ｖ＋−ＶＢＥ＋ｌｅｉ ｌ （
ａ１発明が解決しようとする問題点
しかるに、上記の従来の絶対値回路は■出力電圧Ｖｏの
極性は−っしか得られず、■出力電圧Ｖｏの振幅は入力
交流信号ｅｉの振幅の１／２となり、■出力電圧Ｖｏの
直流成分は、入力直流バイアス■１及びトランジスタ３
３．３４のベース・エミッタ間電圧ＶＢＥに依存する等
の問題点があった。このため、この従来回路を、例えば
信号振幅を検出する回路の一部として構成し、信号振幅
を電位に変換する場合、振幅が大になると変換した電位
が小になるように設定するためには、別に反転回路が必
要となり、この反転回路は例えば振幅中心電位の揃った
正逆両極性の出力電位を得るには通常２個以上のトラン
ジスタで構成される。Vs a =V+ +ei (1
)Vs b =V+ −ei (
2) Vo=V+−VBE+lei l (
a1 Problems to be Solved by the Invention However, in the above-mentioned conventional absolute value circuit, ■ the polarity of the output voltage Vo can only be -, and ■ the amplitude of the output voltage Vo is 1/2 of the amplitude of the input AC signal ei. Therefore, ■The DC component of the output voltage Vo is determined by the input DC bias ■1 and the transistor 3.
There were problems such as dependence on the base-emitter voltage VBE of 3.34. Therefore, when configuring this conventional circuit as part of a circuit that detects signal amplitude, for example, and converting the signal amplitude into a potential, it is necessary to set it so that the converted potential becomes small as the amplitude becomes large. , a separate inverting circuit is required, and this inverting circuit is usually composed of two or more transistors in order to obtain, for example, output potentials of both positive and negative polarities with the same amplitude center potential.
また、従来回路は検出感度を向上させるためには増幅器
が必要となり、更に直流バイアスＶ１やトランジスタ３
３及び３４のベース・エミッタ間電圧ＶｅＥのバラツキ
によって、出力に直流オフセットが発生してしまう。In addition, the conventional circuit requires an amplifier to improve detection sensitivity, and also requires DC bias V1 and transistor 3.
Due to the variation in the base-emitter voltage VeE of 3 and 34, a DC offset occurs in the output.
そこで、本発明はベースに互いに逆極性の第１及び第２
の交流信号が供給される第１及び第２のトランジスタの
エミッタを第１の抵抗を共通に介して第３のトランジス
タのエミッタに接続すると共に、第３のトランジスタの
ベースに上記第１及び第２の交流信号の混合信号を供給
することにより、上記の問題点を解決した絶対値回路を
提供することを目的とする。Therefore, the present invention provides a base with first and second electrodes of opposite polarity.
The emitters of the first and second transistors to which the alternating current signal is supplied are connected to the emitter of the third transistor through the first resistor in common, and the An object of the present invention is to provide an absolute value circuit that solves the above problems by supplying a mixed signal of alternating current signals.
問題点を解決するための手段
本発明は第１乃至第３のトランジスタと第１乃至第３の
抵抗と出力手段とからなる。第１及び第２のトランジス
タの各ベースには互いに同一振幅で同一の直流分を有し
、かつ、互いに逆相の第１及び第２の交流信号が別々に
供給される。第１及び第２のトランジスタの各エミッタ
共通接続点と第３のトランジスタのエミッタと定電流源
の接続点との間には、第１の抵抗が接続されている。ま
た、第１．第２のトランジスタのベースは各別に第２．
第３の抵抗を介して第３のトランジスタのベースに接続
されている。出力手段は少なくとも第１及び第２のトラ
ンジスタの両コレクタ及び第３のトランジスタのいずれ
か一方又は両方に接続された負荷抵抗を有しており、第
１及び第２の交流信号の絶対値を示す出力信号を出力す
る。Means for Solving the Problems The present invention comprises first to third transistors, first to third resistors, and output means. First and second AC signals having the same amplitude, the same DC component, and opposite phases are separately supplied to the bases of the first and second transistors. A first resistor is connected between a common connection point between the emitters of the first and second transistors and a connection point between the emitter of the third transistor and the constant current source. Also, 1st. The bases of the second transistors are respectively connected to the second .
It is connected to the base of the third transistor via a third resistor. The output means has a load resistor connected to at least both the collectors of the first and second transistors and one or both of the third transistor, and indicates the absolute values of the first and second AC signals. Output the output signal.
作用
上記出力手段が上記第１及び第２のトランジスタの各コ
レクタに接続された第４の抵抗を有する場合は、第１及
び第２のトランジスタの電流増幅率が充分大であるもの
とすると、上記第１の抵抗を流れる電流は上記出力手段
内の第４の抵抗を通り第１．第２のトランジスタに向っ
て流れる電流となる。ここで、第１の抵抗を流れる電流
は第１及び第２の交流信号の振幅の絶対値と第１の抵抗
の抵抗値との比となるため、上記出力手段から取り出さ
れる出力信号の直流成分は、入力箱１及び第２の交流信
号の′直流バイアスに無関係となる。Effect: When the output means has a fourth resistor connected to each collector of the first and second transistors, assuming that the current amplification factors of the first and second transistors are sufficiently large, the above-mentioned The current flowing through the first resistor passes through the fourth resistor in the output means. A current flows toward the second transistor. Here, since the current flowing through the first resistor is the ratio of the absolute value of the amplitude of the first and second AC signals and the resistance value of the first resistor, the DC component of the output signal taken out from the output means is is independent of the DC bias of the input box 1 and the second AC signal.
また、上記出力手段が上記第３のトランジスタに接続さ
れた第５の抵抗を有する場合は、この第５の抵抗を通っ
て上記第３のトランジスタに流れる電流は、前記定電流
源の電流から上記第１の抵抗を流れる電流を差し引いた
値となる。このため、上記第５の抵抗を有する出力手段
から取り出される出力信号の直流成分は、入力箱１及び
第２の交流信号あ直流バイアスに無関係となる。Further, when the output means includes a fifth resistor connected to the third transistor, the current flowing through the fifth resistor to the third transistor is changed from the current of the constant current source to the This is the value obtained by subtracting the current flowing through the first resistor. Therefore, the DC component of the output signal taken out from the output means having the fifth resistor is independent of the input box 1 and the DC bias of the second AC signal.
更に、上記出力手段が上記の第４及び第５の抵抗の両方
を有する構成の場合は、互いに逆極性の第１及び第２の
出力信号を得ることができる。本発明になる絶対値回路
について実施例と共に更に詳細に説明する。Furthermore, if the output means has both the fourth and fifth resistors, first and second output signals having opposite polarities can be obtained. The absolute value circuit according to the present invention will be described in more detail along with examples.
実施例
第１図は本発明になる絶対値回路の一実施例の回路図を
示す。同図中、入力端子１０は直流分（直流バイアス）
Ｖ＋を有する第１の交流信号ｅｉが入力される入力端子
で、第１のトランジスタであるＮ Ｐ Ｎ ト・ランジ
スタ１２のベースに接続されている。また、入力端子１
１は第１の交流信号ｅｉと同一振幅で、同一の直流分Ｖ
１を有し、かつ、逆相の第２の交流信号−ｅｉが入力さ
れる入力端子で、第２のトランジスタであるＮＰＮトラ
ンジスタ１３のベースに接続されている。トランジスタ
１２及び１３の各エミッタは共通接続され、その共通接
続点が第１の抵抗１４を介して第３のトランジスタであ
るＮＰＮトランジスタ１７のエミッタと定電流源１８の
接続点に接続されている。また、トランジスタ１２のベ
ースは第２の抵抗１５を介してトランジスタ１７のベー
スに接続され、トランジスタ１３のベースは第３の抵抗
１６を介してトランジスタ１７のベースに接続されてい
る。Embodiment FIG. 1 shows a circuit diagram of an embodiment of the absolute value circuit according to the present invention. In the same figure, the input terminal 10 is a DC component (DC bias)
This is an input terminal to which the first alternating current signal ei having V+ is input, and is connected to the base of the N P N transistor 12 which is the first transistor. In addition, input terminal 1
1 has the same amplitude as the first AC signal ei and the same DC component V
1 and to which the second AC signal -ei of opposite phase is input, and is connected to the base of the NPN transistor 13, which is the second transistor. The emitters of the transistors 12 and 13 are commonly connected, and the common connection point is connected to the connection point between the emitter of an NPN transistor 17, which is a third transistor, and a constant current source 18 via a first resistor 14. Further, the base of the transistor 12 is connected to the base of the transistor 17 via the second resistor 15, and the base of the transistor 13 is connected to the base of the transistor 17 via the third resistor 16.
トランジスタ１２及び１３の各」レクタは共通接続され
、第４の抵抗である負荷抵抗１９を介してバイアス電源
電圧Ｖ２の入力端子２３に接続されている。更に、トラ
ンジスタ１７のコレクタは第５の抵抗である負荷抵抗２
０を介してバイアス電源電圧■３の入力端子２４に接続
されている。The respective collectors of transistors 12 and 13 are connected in common, and are connected to an input terminal 23 of bias power supply voltage V2 via a load resistor 19, which is a fourth resistor. Furthermore, the collector of the transistor 17 is connected to a load resistor 2 which is a fifth resistor.
0 to the input terminal 24 of the bias power supply voltage 3.
また更に、トランジスタ１２及び１３の各コレクタは出
力端子２１に接続され、トランジスタ１７の］レクタは
出力端子２２に接続されている。Furthermore, the collectors of transistors 12 and 13 are connected to output terminal 21, and the collector of transistor 17 is connected to output terminal 22.
次に本実施例の動作につき説明覆るに、トランジスタ１
２及び１３はそのベースに供給される交流信号ｅｉ及び
−ｅｉが正弦波の場合、正の半サイクル期間はそのエミ
ッタより入力交流信号を出力し、他方、負の半サイクル
期間は略オフとされる。従って、トランジスタ１２及び
１３の入力文。Next, to explain the operation of this embodiment, the transistor 1
2 and 13 output the input AC signal from their emitters during the positive half-cycle period when the AC signals ei and -ei supplied to their bases are sine waves, and are substantially off during the negative half-cycle period. Ru. Therefore, the input sentences of transistors 12 and 13.
流信号ｅｉ及び−ｅｉのうち電位の高い方の信号がトラ
ンジスタ１２及び１３のエミッタ共通接続端に出力電位
ＶＥＩとして現われる。ここで、トランジスタ１２のベ
ース電位Ｖａ＋、トランジスタ１３の１ベ一ス電位ＶＢ
２及上記びエミッタ出力電位ＶＥＩは夫々次式で表わさ
れる。・Ｖｅ ＋ ＝Ｖ＋ ＋ｅｉ
（４）Ｖｅ ２ ＝Ｖｌ −ｅ！
（５）ＶＥＩ ＝Ｖ＋−Ｖｅｐ＋ｌｅｉ ｌ
ｆ３）ただし、（６）式中、ＶＩＥはトランジスタ
１２及び１３の各ベース・エミッタ間電圧を示す。また
、入力交流信号ｅｔ及び−０１が正弦波の場合、エミッ
タ出力電位ＶＥＩは第２図（Ａ＞に承り如くになる。The signal with a higher potential among the current signals ei and -ei appears at the common emitter connection terminal of the transistors 12 and 13 as an output potential VEI. Here, the base potential Va+ of the transistor 12, the base potential VB of the transistor 13,
2 and the emitter output potential VEI are respectively expressed by the following equations.・Ve + =V+ +ei
(4) Ve 2 =Vl −e!
(5) VEI =V+-Vep+lei l
f3) However, in equation (6), VIE represents the voltage between the base and emitter of each of the transistors 12 and 13. Further, when the input AC signals et and -01 are sine waves, the emitter output potential VEI becomes as shown in FIG. 2 (A>).
一方、入力端子１０．１１に入来した入力交流信号ｅｉ
、−ｅｉは抵抗１５及び１６によって加算された後ト
ランジスタ１７のベースに印加される。いま、抵抗１５
及び１６の各抵抗値を等しく選定した場合、トランジス
タ１７のベース電位Ｖｅ３は式（４）及び６）より
Ｖｅａ＝（Ｖｓ＋＋Ｖｓ２）／２＝Ｖ１ ’（７）とな
る。従って、トランジスター７のエミッタ電位ＶＥ２は
、そのベース・エミッタ間電圧をＶＢＥとすると
ＶＥ ２ ＝ＶＢ ３−Ｖａ Ｅ ＝ＶＩ −ＶＢ Ｅ
（８）となる。On the other hand, the input AC signal ei entering the input terminal 10.11
, -ei are applied to the base of transistor 17 after being summed by resistors 15 and 16. Now resistance 15
and 16 are selected equally, the base potential Ve3 of the transistor 17 becomes Vea=(Vs++Vs2)/2=V1' (7) from equations (4) and 6). Therefore, the emitter potential VE2 of the transistor 7 is expressed as follows: VE 2 =VB 3 -Va E =VI -VBE
(8) becomes.
従って、抵抗１４をトランジスター７の方向に流れる電
流ＩＥは、式（６）及び（８）を用いて整理すると
ＩＥ ＝ （ＶＥ Ｉ −ＶＥ ２ ）／ＲＥ
＝ｌｅｉｌ／ＲＥ （９）と
なる。ただし、（９）式中、ＲＥは抵抗１４の抵抗値を
示す。トランジスタ１２．１３の電流増幅率が充分大で
あるものとすると、上記電流ＩＥはそのまま負荷抵抗１
９をトランジスター２又は１３に向って流れる電流とな
るから、トランジスタ１２及び１３のコレクタ共通接続
端である出力端子２１より出力される信号電位Ｖｏ＋は
、負荷抵抗１９の抵抗値をＲｃ＋ とすると、式（９）
を用いてＶｏ ｒ＝Ｖ’ｚ −Ｒｃ ＋ 拳ＩＥ＝■
ｚ −１ｅｉ ｌ ・Ｒｃ ＋ ／ＲＥ （１０）
となる。Therefore, the current IE flowing through the resistor 14 in the direction of the transistor 7 can be rearranged using equations (6) and (8) as follows: IE = (VE I - VE 2 )/RE
= leil/RE (9). However, in formula (9), RE indicates the resistance value of the resistor 14. Assuming that the current amplification factor of the transistors 12 and 13 is sufficiently large, the above current IE is directly applied to the load resistance 1.
9 becomes a current flowing toward the transistor 2 or 13. Therefore, the signal potential Vo+ output from the output terminal 21, which is the common connection terminal of the collectors of the transistors 12 and 13, is calculated by the formula, assuming that the resistance value of the load resistor 19 is Rc+. (9)
Using Vo r=V'z -Rc + fist IE=■
z −1ei l ・Rc + /RE (10)
becomes.
一方、負荷抵抗２０をトランジスタ１７の方向に流れる
電流ＩＥ’は、定電流源１８の電流をＩＯとすると
ＩＥ’ ＝ＩＯ＝ＩＥ （’１１
）となる。従って、トランジスタ１７のコレクタより出
力端子２２へ出力される信号電位ＶＯ２は、負荷抵抗２
０の抵抗値をＲＣ２とすると、式Ｇ）及び（１１）を用
いて
ＶＯ２＝Ｖ ３−ＲＣ２争 ＩＥ’＝Ｖ３−ＲＣ２
中Ｉｏ＋
ｌ ｅｉ ｌ ・Ｒｃ ２ ／ＲＥ （１２）
となる。On the other hand, the current IE' flowing through the load resistor 20 in the direction of the transistor 17 is expressed as IE' = IO = IE ('11
). Therefore, the signal potential VO2 output from the collector of the transistor 17 to the output terminal 22 is
If the resistance value of 0 is RC2, then using equations G) and (11), VO2=V 3-RC2 IE'=V3-RC2
Medium Io+ lei l ・Rc 2 /RE (12)
becomes.
入力交流信号ｅｉ及び−ｅｉが正弦波の場合、上記出力
信号電位Ｖｏ＋は、第２図（Ｂ）に示す如くになり、ま
た上記出力信号電位ＶＯ２は同図（Ｃ）に示す如くにな
る。式（１０）及び（１２）あるいは第２図（Ｂ）、（
Ｃ）かられかるように、出力端子２１には入力交流信号
ｅｉ及び−ｅｉの振幅の絶対値を示す負極性の信号Ｖｏ
＋が取り出され、出力端子２２には上記絶対値を示す正
極性の信号ＶＯ２が取り出される。When the input AC signals ei and -ei are sine waves, the output signal potential Vo+ becomes as shown in FIG. 2(B), and the output signal potential VO2 becomes as shown in FIG. 2(C). Equations (10) and (12) or Figure 2 (B), (
As shown in C), the output terminal 21 receives a negative polarity signal Vo indicating the absolute value of the amplitude of the input AC signals ei and -ei.
+ is taken out, and a positive polarity signal VO2 indicating the above-mentioned absolute value is taken out from the output terminal 22.
従って、出力端子２１及び２２の出力信号Ｖｏ＋及びＶ
Ｏ２のどちらか一方を選択することによって出力信号の
極性を選択することができるし、両方を選択することも
できる。また、式（１０）。Therefore, the output signals Vo+ and V at output terminals 21 and 22
By selecting either one of O2, the polarity of the output signal can be selected, or both can be selected. Also, equation (10).
（１２）かられかるように、前記抵抗値ＲＥ及びＲｃ＋
を任意に設定することによって入力信号振幅に対する出
力信号Ｖｏ＋の振幅を変えることができ、また前記抵抗
値ＲＥ及びＲＣ２を任意に設定することによって入力信
号振幅に対する出力信号ＶＯ２の振幅を変えることがで
きる。As can be seen from (12), the resistance values RE and Rc+
By arbitrarily setting , the amplitude of the output signal Vo+ can be changed with respect to the input signal amplitude, and by arbitrarily setting the resistance values RE and RC2, the amplitude of the output signal VO2 with respect to the input signal amplitude can be changed. .
更に式（１０）よりわかるように、出力信号電位Ｖｏ＋
の直流成分は、バイアス電源電圧Ｖ２のみであるから、
入力交流信号ｅｉ 、−ｅｉの直流バイアスＶ＋が変動
しても、Ｖｏ＋の直流オフセットは生じない。同様に出
力信号電位ＶＯ２の直流成分は、式（１２）よりバイア
ス電源電圧Ｖ３と前記抵抗値ＲＣ２と前記電流値１ｏと
により決まり、入力交流信号ｅｉ、−ｅｉの直流バイア
スＶ１に依存しないから、出力の直流オフセットは生じ
ない。Furthermore, as can be seen from equation (10), the output signal potential Vo+
Since the DC component of is only the bias power supply voltage V2,
Even if the DC bias V+ of the input AC signals ei and -ei fluctuates, no DC offset of Vo+ occurs. Similarly, the DC component of the output signal potential VO2 is determined by the bias power supply voltage V3, the resistance value RC2, and the current value 1o from equation (12), and does not depend on the DC bias V1 of the input AC signals ei and -ei. No DC offset of the output occurs.
なお、本発明は上記の実施例に限定されるものではなく
、例えば一つの極性の出力信号のみを使用するだけなら
ば、負荷抵抗１９及び２０のいずれか一方を省略しても
よく、また使用するトランジスタはＰＮＰ型でも良く、
更に入力交流信号波形は正弦波に限らず、のこぎり波、
方形波等すべての交流信号に適用し得ることは勿論であ
る。It should be noted that the present invention is not limited to the above-mentioned embodiments. For example, if only one polarity of output signal is used, either one of the load resistors 19 and 20 may be omitted; The transistor to be used may be a PNP type,
Furthermore, the input AC signal waveform is not limited to a sine wave, but also a sawtooth wave,
Of course, it can be applied to all alternating current signals such as square waves.
発明の効果
上述の如く、本発明により、比較的簡単な回路構成によ
って出力信号の極性の選択や出力信号の振幅の設定を任
意に行なうことができ、また入力交流信号の直流バイア
スの変動が要因となる直流オフセットを生じない絶対値
出力信号を取り出すことができ、またトランジスタ及び
抵抗更には定電流源よりなる回路構成だから集積回路（
ＩＣ）化に適しており、更に電子機器の信号処理回路と
して使用した場合は、ｉ来と比較してより多機能で出力
安定性の高い絶対値出力信号を得ることができる等の数
々の特長を有するものである。Effects of the Invention As described above, according to the present invention, it is possible to arbitrarily select the polarity of the output signal and set the amplitude of the output signal with a relatively simple circuit configuration, and it is possible to arbitrarily select the polarity of the output signal and set the amplitude of the output signal. It is possible to extract an absolute value output signal that does not cause a DC offset, and since the circuit is composed of transistors, resistors, and a constant current source, it is possible to obtain an absolute value output signal that does not cause a DC offset.
It is suitable for IC), and when used as a signal processing circuit in electronic equipment, it has many features such as being able to obtain absolute value output signals with more functions and higher output stability than conventional products. It has the following.
第１図は本発明回路の一実施例を示す回路図、第２図は
第１図図示ブロック系統の動作説明用信号波形図、第３
図は従来回路の一例を示す回路図、第４図は第３図図示
ブロック系統の動作説明用信号波形図である。
１０．１１．３１．３２・・・入力端子、１２゜１３．
１７．３３．３４・・・ＮＰＮトランジスタ、１４・・
・第１の抵抗、１５・・・第２の抵抗、１６・・・第３
の抵抗、１８．３５・・・定電流源、１９．２０・・・
負荷抵抗、２１．２２．３６・・・出力端子、２３゜２
４・・・バイアス電源電圧入力端子、ｅｉ 、 −ｅｉ
・・・入力交流信号。
特許出願人 日本ビクター株式会社
第１図
第２図
第３図
第４図FIG. 1 is a circuit diagram showing an embodiment of the circuit of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation of the block system shown in FIG. 1, and FIG.
The figure is a circuit diagram showing an example of a conventional circuit, and FIG. 4 is a signal waveform diagram for explaining the operation of the block system shown in FIG. 10.11.31.32...Input terminal, 12°13.
17.33.34...NPN transistor, 14...
・First resistor, 15... second resistor, 16... third resistor
resistance, 18.35...constant current source, 19.20...
Load resistance, 21.22.36...output terminal, 23゜2
4...Bias power supply voltage input terminal, ei, -ei
...Input AC signal. Patent applicant: Victor Japan Co., Ltd. Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
相の第１及び第２の交流信号が別々にベースに供給され
る第１及び第２のトランジスタと、該第１及び第２のト
ランジスタの各エミッタ共通接続点に一端が接続された
第１の抵抗と、該第１の抵抗の他端と定電流源に夫々エ
ミッタが接続された第３のトランジスタと、該第１のト
ランジスタのベースと該第３のトランジスタのベースと
の間に接続された第２の抵抗と、該第２のトランジスタ
のベースと該第３のトランジスタのベースとの間に接続
された第３の抵抗と、少なくとも該第１及び２のトラン
ジスタの両コレクタ及び該第３のトランジスタのいずれ
か一方又は両方に接続された負荷抵抗を有し、出力信号
を出力させる出力手段とからなることを特徴とする絶対
値回路。first and second transistors whose bases are separately supplied with first and second alternating current signals having the same amplitude and the same direct current component and having opposite phases to each other; a first resistor having one end connected to a common connection point of each emitter of the transistor; a third transistor having an emitter connected to the other end of the first resistor and a constant current source; a second resistor connected between the base and the base of the third transistor; a third resistor connected between the base of the second transistor and the base of the third transistor; An absolute value characterized by comprising an output means for outputting an output signal, the output means having a load resistor connected to at least both the collectors of the first and second transistors and one or both of the third transistor, and outputting an output signal. circuit.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59169062A JPS6146566A (en) | 1984-08-13 | 1984-08-13 | Absolute value circuit |
| GB08527111A GB2168817A (en) | 1984-08-13 | 1985-11-04 | Electrocardiography device |
| FR8516370A FR2572644A1 (en) | 1984-08-13 | 1985-11-05 | ELECTROCARDIOGRAPHY DEVICE |
| DE19853539564 DE3539564A1 (en) | 1984-08-13 | 1985-11-07 | ELECTROCARDIOGRAPHY DEVICE |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59169062A JPS6146566A (en) | 1984-08-13 | 1984-08-13 | Absolute value circuit |
| JP16906284U JPS6185204U (en) | 1984-11-07 | 1984-11-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6146566A true JPS6146566A (en) | 1986-03-06 |
| JPS6359197B2 JPS6359197B2 (en) | 1988-11-18 |
Family
ID=26492532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59169062A Granted JPS6146566A (en) | 1984-08-13 | 1984-08-13 | Absolute value circuit |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS6146566A (en) |
| DE (1) | DE3539564A1 (en) |
| FR (1) | FR2572644A1 (en) |
| GB (1) | GB2168817A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6259402A (en) * | 1985-09-09 | 1987-03-16 | Toshiba Corp | Peak detection circuit |
| JPH0310410A (en) * | 1989-06-07 | 1991-01-18 | Nec Corp | Absolute value circuit |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0299667A1 (en) * | 1987-07-10 | 1989-01-18 | Koike Seiki Kabushiki Kaisha | Portable electrocardiograph |
| FR2666977B1 (en) * | 1990-09-20 | 1993-08-13 | Lefebvre Jean Marie | PORTABLE ELECTROCARDIOGRAPHER. |
| US5339823A (en) * | 1992-08-07 | 1994-08-23 | Survival Technology, Inc. | Twelve-lead portable heart monitor and method |
| DE19623149C1 (en) * | 1996-06-10 | 1998-01-29 | Fraunhofer Ges Forschung | Diagnostic system in credit card format |
| GB2348707B (en) * | 1999-04-07 | 2003-07-09 | Healthcare Technology Ltd | Heart activity detection apparatus |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4120294A (en) * | 1976-08-26 | 1978-10-17 | Wolfe Donna L | Electrode system for acquiring electrical signals from the heart |
| US4221223A (en) * | 1978-05-24 | 1980-09-09 | Medtronic, Inc. | Cardiac monitoring apparatus |
| DE2847087A1 (en) * | 1978-10-28 | 1980-04-30 | Sachs Elektronik Kg Hugo | Pulse frequency meter worn on wrist - measures blood pulse rate from electrode and uses oscillator to give time display signals |
| US4248244A (en) * | 1979-04-06 | 1981-02-03 | Charnitski Richard D | Method for measuring heart beat rate and circuit means for same |
| JPS5886141A (en) * | 1981-11-17 | 1983-05-23 | セイコーインスツルメンツ株式会社 | Pulse meter |
| JPS58149745A (en) * | 1982-02-26 | 1983-09-06 | セイコーインスツルメンツ株式会社 | Stetoscope with pulse meter |
| EP0101870A3 (en) * | 1982-08-05 | 1986-09-17 | Kontron-Holding Ag | Portable electrocardiologic apparatus |
| ES8500037A1 (en) * | 1982-10-05 | 1984-06-16 | Ascher Gilles | Portable E.C.G. recording apparatus. |
| FR2551647A1 (en) * | 1983-09-13 | 1985-03-15 | Gilles Ascher | Portable apparatus with a bracelet intended for the recording of electrocardiograms |
| FR2554704B1 (en) * | 1983-11-10 | 1987-04-24 | Ascher Gilles | PORTABLE CARDIAC ACTIVITY MONITORING DEVICE |
-
1984
- 1984-08-13 JP JP59169062A patent/JPS6146566A/en active Granted
-
1985
- 1985-11-04 GB GB08527111A patent/GB2168817A/en not_active Withdrawn
- 1985-11-05 FR FR8516370A patent/FR2572644A1/en active Pending
- 1985-11-07 DE DE19853539564 patent/DE3539564A1/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6259402A (en) * | 1985-09-09 | 1987-03-16 | Toshiba Corp | Peak detection circuit |
| JPH0783215B2 (en) * | 1985-09-09 | 1995-09-06 | 株式会社東芝 | Peak detection circuit |
| JPH0310410A (en) * | 1989-06-07 | 1991-01-18 | Nec Corp | Absolute value circuit |
| JP2536156B2 (en) * | 1989-06-07 | 1996-09-18 | 日本電気株式会社 | Absolute value circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3539564A1 (en) | 1986-05-15 |
| FR2572644A1 (en) | 1986-05-09 |
| GB2168817A (en) | 1986-06-25 |
| JPS6359197B2 (en) | 1988-11-18 |
| GB8527111D0 (en) | 1985-12-11 |
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