JPH0263308A - Automatic gain control circuit - Google Patents

Automatic gain control circuit

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Publication number
JPH0263308A
JPH0263308A JP21616088A JP21616088A JPH0263308A JP H0263308 A JPH0263308 A JP H0263308A JP 21616088 A JP21616088 A JP 21616088A JP 21616088 A JP21616088 A JP 21616088A JP H0263308 A JPH0263308 A JP H0263308A
Authority
JP
Japan
Prior art keywords
gain control
comparator
voltage
amplitude
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21616088A
Other languages
Japanese (ja)
Inventor
Takashi Senba
仙波 隆司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21616088A priority Critical patent/JPH0263308A/en
Publication of JPH0263308A publication Critical patent/JPH0263308A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To improve the accuracy and stability of an input voltage to a comparator for producing a gain control voltage by adding outputs of a differential amplifier circuit so as to obtain a reference voltage of a comparator. CONSTITUTION:A DC potential of an output signal of a differential amplifier circuit and a minimum potential detected from the amplitude of a signal at a high potential side are brought to the same potential, the stable state. When the amplitude of the input signal is decreased, the amplitude of signal waveforms 201, 202 is decreased, a reference voltage 203 is unchanged and the amplitude of signal waveforms 204, 205 is decreased, then the minimum level in the amplitude is increased, showing a difference from the reference potential 203. Then difference is outputted at an output terminal 120 by a comparator 118 as a gain control voltage. Thus, the reference voltage is given from the differential amplifier and the control accuracy is improved.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、バイポーラ集積回路で構成される差動増幅回
路に用いられる自動利得制御回路に関し、特に高精度且
つ高安定の利得制御を可能にする自動利得制御回路に関
する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an automatic gain control circuit used in a differential amplifier circuit composed of a bipolar integrated circuit, and in particular to an automatic gain control circuit that enables highly accurate and highly stable gain control. This invention relates to an automatic gain control circuit.

し従来の技術] 従来、この種の自動利得制御回路は、差動増幅回路を構
成する差動トランジスタ対の負荷抵抗対により生成され
る出力信号振幅の最大値を検出し、この検出電圧を比較
器に入力として与え、また、外部より比較器に対して基
準電圧を与え、比較器の比較出力をもって利得制御のた
めの制御電圧としていた。
Conventionally, this type of automatic gain control circuit detects the maximum value of the output signal amplitude generated by the load resistor pair of the differential transistor pair constituting the differential amplifier circuit, and compares the detected voltage. In addition, a reference voltage was applied to the comparator from the outside, and the comparison output of the comparator was used as a control voltage for gain control.

第3図は従来の自動利得制御回路を示す。第3図におい
て、301,302を久方端子、315゜317を出力
端子として、差動トランジスタ対303.304と夫々
電源端子309及び接地端子310との間に接続される
負荷抵抗対306,307並びに差動トランジスタ対3
03,304の接続点と接地端子308との間に設けて
いる電流源305により差動増幅回路を構成している。
FIG. 3 shows a conventional automatic gain control circuit. In FIG. 3, load resistor pairs 306 and 307 are connected between a differential transistor pair 303 and 304 and a power supply terminal 309 and a ground terminal 310, respectively, with 301 and 302 as long terminals and 315° and 317 as output terminals. and differential transistor pair 3
A current source 305 provided between the connection point of 03 and 304 and the ground terminal 308 constitutes a differential amplifier circuit.

自動利得制御回路は、負荷抵抗対306,307を通し
て出力端子315,317に生成する信号振幅の最大ピ
ーク値を検出するピーク検出器312と、このピーク検
出器312の出力を入力とし、基準電圧端子31.4か
ら基準電圧が与えられる比較器313とにより構成され
、この比較器313の比較結果を利得制御出力として端
子316に出力するものとなっている。
The automatic gain control circuit includes a peak detector 312 that detects the maximum peak value of the signal amplitude generated at output terminals 315 and 317 through a load resistor pair 306 and 307, and a reference voltage terminal that receives the output of this peak detector 312 as input. 31.4 and a comparator 313 to which a reference voltage is applied, and the comparison result of this comparator 313 is output to a terminal 316 as a gain control output.

第4図に動作波形を示す。第4図において、415.4
17は第3図の夫々出力端子315,317に生成され
る出力信号を示す。出力信号としては、第3図のピーク
検出器312により信号振幅最大値が検出され電位41
2を得る。また、414は第3図の基準電圧端子314
に与えられる電位を示す。第3図の比較器313により
電位412と電位414との電位比較を行ない、比較結
果を第3図の利得制御出力端子316へ出力する。
Figure 4 shows the operating waveforms. In Figure 4, 415.4
Reference numeral 17 indicates output signals generated at output terminals 315 and 317, respectively, in FIG. As an output signal, the peak detector 312 in FIG. 3 detects the maximum signal amplitude, and the potential 41
Get 2. 414 is the reference voltage terminal 314 in FIG.
Indicates the potential applied to The comparator 313 in FIG. 3 compares the potentials 412 and 414, and outputs the comparison result to the gain control output terminal 316 in FIG.

[発明が解決しようとする課題] しかしながら、上述した従来の自動利得制御回路は、信
号振幅の最大ピーク値を検出した結果得られる電位に対
して差動増幅回路とは独立した基準電位を比較器313
に供給する構成となっているので、差動増幅回路の出力
振幅最大値と基準電圧との絶対精度が確保されないとい
う欠点がある。
[Problems to be Solved by the Invention] However, the conventional automatic gain control circuit described above uses a comparator to compare a reference potential independent of the differential amplifier circuit with respect to the potential obtained as a result of detecting the maximum peak value of the signal amplitude. 313
Therefore, there is a drawback that the absolute accuracy between the maximum output amplitude value of the differential amplifier circuit and the reference voltage cannot be ensured.

本発明はかかる問題点に鑑みてなされたものであって、
利得制御電圧生成のための比較器における入力電圧の精
度向上及び安定性を確保し、もって差動増幅回路として
の高精度化及び高安定性を実現することができる自動利
得制御回路を提供することを目的とする。
The present invention has been made in view of such problems, and includes:
To provide an automatic gain control circuit that can improve accuracy and ensure stability of input voltage in a comparator for generating gain control voltage, thereby realizing high accuracy and high stability as a differential amplifier circuit. With the goal.

[課題を解決するための手段] 本発明に係る自動利得制御回路は、負荷抵抗対を、夫々
同一比率で分割し、相対する特定の分割点の電圧を加算
し、この加算電圧を比較器の基準電圧とし、相対する他
の分割点のピーク電圧を前記比較器の入力とし、前記比
較器の出力を利得制御電圧としたことを特徴とする。
[Means for Solving the Problems] The automatic gain control circuit according to the present invention divides a pair of load resistors at the same ratio, adds voltages at specific opposing division points, and applies this added voltage to a comparator. The present invention is characterized in that the reference voltage is used as a reference voltage, the peak voltage at another opposing dividing point is used as an input to the comparator, and the output of the comparator is used as a gain control voltage.

[作用コ この構成によれば、負荷抵抗対の特定の相対する分割点
の電圧を加算することで、分割比に応じた一定の直流電
圧が得られるので、これを基準電圧とすることができ、
また、他の相対する分割点のピーク電圧は、入力電圧に
応じて変動するので、これを比較器の入力として用いる
ことができる。
[Operation] According to this configuration, by adding the voltages at specific opposing division points of the load resistor pair, a constant DC voltage corresponding to the division ratio can be obtained, so this can be used as the reference voltage. ,
Furthermore, since the peak voltage at the other opposing division points varies depending on the input voltage, this can be used as the input of the comparator.

従って、差動増幅回路とは独立した基準電位は不要とな
り、また、比較器の入力電圧の精度及び安定性の向上が
図られる。
Therefore, there is no need for a reference potential independent of the differential amplifier circuit, and the accuracy and stability of the input voltage of the comparator can be improved.

[実施例] 第1図は本発明の実施例を示す。第1図において、差動
増幅回路は、101,102を差動入力端子とし、差動
トランジスタ対103,104と、夫々電源端子113
及び114との間に夫々3分割した負荷抵抗107,1
08,109及び負荷抵抗110,111,112を接
続し、差動トランジスタ対103.104の接続点と接
地端子106との間に電流源105を設けである。そし
て、各負荷抵抗分割点の低電位側P、P’を夫々差動出
力端子119,121とする。
[Example] FIG. 1 shows an example of the present invention. In FIG. 1, the differential amplifier circuit has differential input terminals 101 and 102, a differential transistor pair 103 and 104, and a power supply terminal 113, respectively.
and 114, load resistors 107 and 1 divided into three, respectively.
08, 109 and load resistors 110, 111, 112 are connected, and a current source 105 is provided between the connection point of the differential transistor pair 103 and 104 and the ground terminal 106. The low potential sides P and P' of each load resistance dividing point are used as differential output terminals 119 and 121, respectively.

自動利得制御回路においては、低電位側P。In the automatic gain control circuit, the low potential side P.

P′の電圧を抵抗116,117により加算して比較器
118の基準入力とする。また、ピーク検出器115に
負荷抵抗分割点の高電位側Q、Q’の2点対に生じる信
号が入力され、ピーク値検出器115は振幅最小値を検
出して比較器118の他方の入力に与える。そして、比
較器118の出力は出力端子120に対して利得制御電
圧として出力される。
The voltage of P' is added by resistors 116 and 117 and is used as a reference input of comparator 118. In addition, a signal generated at a pair of points Q and Q' on the high potential side of the load resistance dividing point is input to the peak detector 115, and the peak value detector 115 detects the minimum amplitude value and inputs the signal to the other input of the comparator 118. give to The output of the comparator 118 is then outputted to the output terminal 120 as a gain control voltage.

次に第2図の動作波形例を用いて動作を説明する。Next, the operation will be explained using the example of operation waveforms shown in FIG.

201.202は夫々第1図の差動増幅回路の出力端子
119,121に生じる出力信号波形を示す。
201 and 202 indicate output signal waveforms generated at the output terminals 119 and 121 of the differential amplifier circuit shown in FIG. 1, respectively.

また、204,205は第1図の負荷抵抗分割点の高電
位側Q、Q’の2点対に生じる信号波形を示す。更に、
20Bは第1図のピーク検出器115の信号振幅最小値
出力と、低電位側P、P′の2点対の電圧を加算した比
較器118に入力される基準電圧を示す。
Further, 204 and 205 indicate signal waveforms generated at a pair of points Q and Q' on the high potential side of the load resistance dividing point in FIG. Furthermore,
Reference numeral 20B indicates a reference voltage input to the comparator 118, which is the sum of the minimum signal amplitude output of the peak detector 115 in FIG.

この動作の例の場合は、負荷抵抗107,108.10
9及び110,111,1..12は、1:1:2の比
率で夫々分割されている例を示している。
For this example of operation, the load resistances 107, 108.10
9 and 110, 111, 1. .. 12 shows an example in which each is divided at a ratio of 1:1:2.

これによれば、電源電圧を■とすると、相対する分割点
P、P’の電圧201,202は、203の電位(3/
4)Vを中心とする信号、相対する分割点Q、Q’の電
圧204,205は、(7/8)■を中心とする信号と
して取出される。図示の例では、信号波形204,20
5の信号振幅は、信号波形201,202の信号振幅の
2分の1となっており、信号波形201,202に示さ
れた信号の直流バイアス電位より2分の1の振幅の半値
分上方ヘシフトした電位となっている。
According to this, if the power supply voltage is ■, the voltages 201 and 202 at opposing dividing points P and P' are the potential (3/
4) Signal centered at V, voltages 204 and 205 at opposing dividing points Q and Q' are extracted as a signal centered at (7/8)■. In the illustrated example, signal waveforms 204, 20
The signal amplitude of No. 5 is half of the signal amplitude of the signal waveforms 201 and 202, and is shifted upward by half the amplitude of the half of the DC bias potential of the signal shown in the signal waveforms 201 and 202. It has a potential of

即ち、差動増幅回路の出力信号のもつ直流電位と、高電
位側の信号振幅から検出される最小値の電位とは、同電
位で安定状態となっている。入力される信号振幅が小さ
くなると、信号波形201゜202の振幅が小さくなっ
ても基準電圧203は変わらず、また、信号波形204
,205の振幅は小さくなっていくことで、その振幅の
最小値のレベルは上昇し、基準電位203と差をもっこ
とになり、この差を比較器118により出力端子120
に利得制御電圧として出力する動作を行なう。
That is, the DC potential of the output signal of the differential amplifier circuit and the minimum value potential detected from the signal amplitude on the high potential side are at the same potential and are in a stable state. When the input signal amplitude becomes smaller, the reference voltage 203 does not change even if the amplitude of the signal waveforms 201 and 202 becomes smaller, and the signal waveform 204
, 205 becomes smaller, the level of the minimum value of the amplitude increases and becomes different from the reference potential 203, and this difference is transferred to the output terminal 120 by the comparator 118.
It performs the operation of outputting as a gain control voltage.

このようにすることにより基準電圧を差動増幅器にて与
えることができ、制御精度が向上する。
By doing so, the reference voltage can be applied by the differential amplifier, and control accuracy is improved.

なお、本発明は、差動増幅器の負荷抵抗対を同一比率で
分割し、相対する特定の分割点の電圧を加算することで
比較器の基準電圧を得、他の特定の分割点の電圧のピー
ク値を比較器の入力とすることを骨子とするものである
から、特に負荷抵抗の分割比、分割点、ピーク値が最小
振幅値であるか最大振幅値であるか等は上記の例に限定
されるものではない。
In addition, in the present invention, the load resistance pair of the differential amplifier is divided at the same ratio, and the voltages at the opposing specific dividing points are added to obtain the reference voltage of the comparator, and the voltage at the other specific dividing points is obtained. Since the main point is to use the peak value as input to the comparator, the division ratio of the load resistance, the division point, whether the peak value is the minimum amplitude value or the maximum amplitude value, etc. should be determined in the above example. It is not limited.

[発明の効果] 以上説明したように本発明は、差動増幅回路の出力を加
算することにより、比較器の基準電圧を得るようにして
いるので、差動増幅回路とは独立した基準電位が不要に
なり、利得制御電圧生成のための比較器入力電圧の精度
及び安定性を向上させることができるという効果がある
[Effects of the Invention] As explained above, in the present invention, the reference voltage of the comparator is obtained by adding the outputs of the differential amplifier circuit, so that the reference potential independent of the differential amplifier circuit is This has the effect that the accuracy and stability of the comparator input voltage for generating the gain control voltage can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例の回路図、第2図は第1図の動
作波形図、第3図は従来例の回路図、第4図は第3図の
動作波形図である。
1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an operational waveform diagram of FIG. 1, FIG. 3 is a circuit diagram of a conventional example, and FIG. 4 is an operational waveform diagram of FIG. 3.

Claims (1)

【特許請求の範囲】[Claims] (1)差動トランジスタ対、負荷抵抗対及び電流源より
なる差動増幅回路における利得制御のための制御電圧を
得る自動利得制御回路において、前記負荷抵抗対を、夫
々同一比率で分割し、相対する特定の分割点の電圧を加
算し、この加算電圧を比較器の基準電圧とし、相対する
他の分割点のピーク電圧を前記比較器の入力とし、前記
比較器の出力を利得制御電圧とすることを特徴とする自
動利得制御回路。
(1) In an automatic gain control circuit that obtains a control voltage for gain control in a differential amplifier circuit consisting of a differential transistor pair, a load resistor pair, and a current source, each of the load resistor pairs is divided at the same ratio, and the The voltages at a specific dividing point are added, this added voltage is used as a reference voltage of a comparator, the peak voltage at another opposing dividing point is used as an input to the comparator, and the output of the comparator is used as a gain control voltage. An automatic gain control circuit characterized by:
JP21616088A 1988-08-30 1988-08-30 Automatic gain control circuit Pending JPH0263308A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21616088A JPH0263308A (en) 1988-08-30 1988-08-30 Automatic gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21616088A JPH0263308A (en) 1988-08-30 1988-08-30 Automatic gain control circuit

Publications (1)

Publication Number Publication Date
JPH0263308A true JPH0263308A (en) 1990-03-02

Family

ID=16684236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21616088A Pending JPH0263308A (en) 1988-08-30 1988-08-30 Automatic gain control circuit

Country Status (1)

Country Link
JP (1) JPH0263308A (en)

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