JPS6223164Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a cancel signal generation circuit used in a pilot signal cancel circuit in a stereo demodulation circuit of an FM receiver.

The pilot signal cancel circuit outputs a composite signal from which the pilot signal has been removed by subtracting from the composite signal a cancel signal that is phase synchronized with the pilot signal in the composite signal and has the same level as the pilot signal level. Therefore, in order to obtain the subtraction signal, the pilot signal cancel circuit requires a cancel signal generating circuit that is phase synchronized with the pilot signal and generates a cancel signal equal to the pilot signal level.

SUMMARY OF THE INVENTION An object of the present invention is to provide a cancel signal generating circuit that outputs a cancel signal that is phase synchronized with a pilot signal in a composite signal and whose level follows the pilot signal level.

The present invention will be explained below using examples.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

Transistors 1 and 2 have their emitters commonly connected through resistors 3 and 4, respectively, and a constant current circuit consisting of a bias power supply 5, transistor 6, and resistor 7 is connected to the common connection point of resistors 3 and 4. A differential amplifier circuit A is configured, and a DC voltage signal obtained by synchronously detecting and smoothing a pilot signal is applied to the base of transistor 1 via input terminal IN, and a bias voltage is applied to the base of transistor 2 via terminal B. is applied to bias transistor 2 to a certain operating point.

The output of the first differential amplifier circuit A is the transistor 1
0 and 11 and resistors 8 and 9, and a diode 12 is connected to the transistor 11.
and a resistor 13 connected in series, a load circuit is connected,
The configuration is such that the collector current of the transistor 11 flows through the load circuit.

On the other hand, transistors 18 and 19 have their emitters connected in common, and a current source circuit consisting of transistor 20, resistor 21, and a load circuit of transistor 11 consisting of diode 12 and resistor 13 is connected to the common connection point. 2 differential amplifier circuit D is constructed, and the bases of transistors 18 and 19 are connected to square waves of pilot signal frequencies that are in phase synchronization with the pilot signal and have an antiphase relation to each other through terminals P ₁ and P ₂ , respectively. Apply a signal.

Transistors 16 and 25 and resistors 14 and 23 are connected to the collectors of transistors 18 and 19, respectively.
A second current inverting circuit E consisting of a current mirror circuit configured as above and a third current inverting circuit F consisting of a current mirror circuit consisting of transistors 17 and 24 and resistors 15 and 22 are connected.

A current mirror circuit consisting of transistors 26 and 27 and resistors 28 and 29 is connected to the collectors of the transistors 24 and 25, and a resistor 31 and a bias power supply 32 are connected to the collector of the transistor 27.
An output synthesis circuit G consisting of a bias circuit consisting of the following is connected to the circuit so that the output currents of the second and third current inverting circuits E and F are combined and outputted from the output terminal OUT.

In the cancel signal generation circuit of this embodiment configured as described above, the first differential amplifier circuit A operates with a constant current defined by a constant current circuit consisting of a bias power supply 5, a transistor 6, and a resistor 7, and The operating point is the bias voltage applied to the base of transistor 2 via the input terminal.
Amplify the DC voltage signal applied to IN.

The DC voltage signal applied to the input terminal IN is a DC signal obtained by synchronously detecting and smoothing the pilot signal, and the amount of change in the DC voltage signal reaches about 1V. By the way, the linear operation range of the transfer characteristic of a normal differential amplifier circuit is not wide, and it is not possible to linearly amplify the above-mentioned DC voltage signal. However, in the first differential amplifier circuit A of this embodiment, resistors 3 and 4 are inserted into the emitters of transistors 1 and 2 to perform current feedback.
For example, as shown in Figure 2a, the constant current source 6' is 1mA.
When the resistance value R _E of resistors 3 and 4 is set to 3.6 kΩ, a linear transfer characteristic can be obtained for the variation range of the DC voltage signal of ±1 V as shown in FIG. 2b. In addition, in FIG. 2b, the broken line is R _E
=0Ω, that is, it shows the transfer characteristics of a normal differential amplifier circuit.

The output power of the first differential amplifier A which amplified the DC voltage signal applied to the input terminal IN, that is, a current having the same value as the collector current of the transistor 2 flows through a load circuit consisting of a diode 12 and a resistor 13. The sum of the voltages generated across the diode 12 and the resistor 13 becomes the bias voltage of the transistor 20 constituting the current source circuit of the second differential amplifier circuit D, and at the same time acts as a control signal that determines the current value.

On the other hand, the second differential amplifier circuit D has a transistor 2
0, a resistor 21, a diode 12, and a resistor 13. The output current value of this current source circuit is determined by the input terminal as described above.
The current value is proportional to the DC voltage signal applied to the input terminal IN, and the second differential amplifier circuit D operates with a current value proportional to the DC signal applied to the input terminal IN. Furthermore, the second differential amplifier circuit D
Since the input terminals, that is, the terminals _P1 and _P2 , are applied with signals that are in phase synchronization with the pilot signal and have an opposite phase relationship with each other, the transistors 18 and 19 alternately operate in synchronization with the frequency of the pilot signal. Repeat on and off. Therefore, a current proportional to the DC signal applied to the input terminal IN flows through the transistor 18 or 19 that is on.

Therefore, a current having the same value as the collector current flowing through the transistors 18 and 19 flows through the transistor 25 of the second current inverting circuit E and the transistor 24 of the third current inverting circuit F.

Currents flowing through transistor 24 and transistor 25 are combined in output combining circuit G.
That is, transistor 1 of the second differential amplifier D
When transistor 8 is in the on state, transistor 18
A current having the same value as the output current of the second current inverting circuit E
The current flows to transistor 25 due to the current. However, in this state, since the transistor 19 is off, the current flowing through the transistor 24 by the third current inversion circuit F is zero. Therefore, the current flowing through transistor 25 cannot flow through transistor 27, and the current flowing through transistor 25 cannot flow through resistor 3.
1, and a voltage determined by the product of the current flowing through the transistor 25 and the resistor 31 with the potential of the bias power supply 32 as the operating point is output. Further, when transistor 19 is in the on state, transistor 1
A current having the same value as the output current of No. 9 flows through the transistors 24 and 26 by the third current inverting circuit F. However, in this state, the transistor 18
Since is in the off state, the current flowing through the transistor 25 by the second current inverting circuit E is zero.
Therefore, the transistor 27 has a bias power supply 32,
A current having the same value as the current flowing through the transistor 26 flows through the resistor 31, and a voltage determined by the product of the current flowing through the transistor 27 and the resistor 31 is outputted using the potential of the bias power supply 32 as the operating point. This output voltage is the same as that of the transistor 25.
The polarity is opposite to that of the output voltage due to the current flowing through the output voltage. Further, the current flowing through the resistor 31 is a current flowing through the transistor 20, that is, a current proportional to the current voltage signal applied to the input terminal IN.

Therefore, a cancel signal whose level follows the level of the pilot signal and whose phase is synchronized with the pilot signal is outputted from the output terminal OUT.

Note that if the diode 12 and the transistor 20 are made to have the same characteristics as those used in integrated circuits, the temperature characteristics can be canceled out.

As explained above, according to the present invention, it is possible to obtain a cancel signal whose level follows the level of the pilot signal and whose phase is synchronized with the pilot signal. It also has a wide linear motion range. Moreover, it can also be made to have no temperature characteristics.

Further, it is easy to form an integrated circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention. Figure 2a
1 is a circuit diagram of a first differential amplifier circuit according to an embodiment of the present invention; FIG. FIG. 2b is a characteristic diagram for explaining the operation of the circuit of FIG. 2a. A...First differential amplifier circuit, C...First current inversion circuit, D...Second differential amplifier circuit, E and F...Second and third current inversion circuit, G... …
Output synthesis circuit, 1, 2, 6, 10, 11, 16 ~
20, 24-27...transistor, 12...diode, 5 and 32...bias power supply.

Claims (1)

[Scope of utility model registration request] the first transistor, comprising first and second resistors having one ends connected in common; and first and second transistors emitter-coupled by connecting the other ends of the first and second resistors to emitters, respectively; A DC voltage signal proportional to the level of the pilot signal is applied to the base of the first transistor, and a constant bias voltage is applied to the base of the second transistor.
a differential amplifier circuit, third and fourth transistors that are emitter-coupled, and an output that is connected to the commonly connected emitters of the third and fourth transistors and that is proportional to the output current of the first differential amplifier circuit. a second differential amplifier circuit comprising: a current source circuit that outputs a current; and a second differential amplifier circuit comprising a current source circuit that outputs a current, and applying signals that are in phase synchronization with the pilot signal and have opposite phases to each other as switch signals to the bases of the third and fourth transistors; , an output combining circuit consisting of a current mirror circuit and a series circuit connected in parallel to the current mirror circuit and consisting of a third resistor and a bias power supply; and a current equal to the output current of the third and fourth transistors, respectively. A cancel signal generation circuit comprising first and second current inverting circuits that lead to the current mirror circuit.