JP3000737B2 - Output buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit for an integrated circuit.

[0002]

2. Description of the Related Art As a conventional output buffer circuit, a circuit as shown in FIG. 2 or 3 has been known.

First, the circuit of FIG. 2 will be described.

[0004] The circuit shown in FIG.
8, a differential amplifier constituted by resistors 5, 6 and a current source 9, and an emitter follower circuit constituted by a transistor 10 and a resistor 15.

Next, the operation of the circuit shown in FIG. 2 will be described. An input signal a is input from an input terminal 1 and an inverted input signal b is input from an input terminal 2, and an amplified signal c amplified by a differential amplifier is output. can get. The amplified signal c is used as an input signal of the emitter follower, and an output signal is output from the output terminal 3. The emitter follower functions to reduce the output impedance.

Next, the circuit shown in FIG. 3 will be described.

[0007] The circuit shown in FIG.
8, a differential amplifier composed of resistors 5, 6 and a current source 9, and a push-pull output stage composed of transistors 10, 11, 13, 14 and a resistor 12. Next, the operation of the circuit shown in FIG. 3 will be described. When the input signals a and b are inputted in balance from the two input terminals 1 and 2 of the differential amplifier, respectively, a signal c obtained by amplifying them and an inverted signal d is obtained and applied to the bases of the NPN transistors 10 and 11, respectively.
Here, when the input signal a rises, the inverted input signal b falls, so that the amplified signal c rises and the inverted amplified signal d falls. Therefore, the collector current of the transistor 11 decreases, and the collector current of the transistor 14 also decreases due to the current mirror effect of the current mirror circuit including the transistors 13 and 14. On the other hand, since the amplified signal c is applied to the base of the transistor 10, the potential of the output terminal 3 rises.

Conversely, when the input signal a falls, the inverted input signal b rises, so that the amplified signal c falls and the inverted amplified signal d rises. As a result, the collector current of the transistor 11 increases, and the transistor 1
Due to the current mirror effect of the current mirror circuit composed of the transistors 3 and 14, the collector current of the transistor 14 also increases. On the other hand, since the amplified signal c is applied to the base of the transistor 10, the potential of the output terminal 3 falls.

[0009]

In the conventional output buffer circuit as shown in FIG. 2, when the output signal rises, the impedance with respect to the rise of the output signal is determined by the "on" resistance of the transistor 10 in the output stage. Falls, the output stage resistor 15
Is determined by a time constant that depends on the value of

Here, the "on" resistance of the transistor is generally several ohms to several tens of ohms, and the resistance value of the resistor 15 in the output stage is set to several hundred ohms to several kilohms. It can be seen that is sufficiently larger than the impedance for rising. For this,
In the case of the circuit shown in FIG. 2, there is a drawback that the fall of the output signal is significantly delayed with respect to the rise of the output signal.

In order to improve this point, the value of the resistor 15 in the output stage must be set to a sufficiently small value. By doing so, the fall of the output waveform becomes faster. On the other hand, a very large amount of current flows through the resistor 15
And the efficiency decreases.

In the circuit shown in FIG. 3, the impedance seen from the collector of the output stage transistor 14 is still several hundreds Ω to several kΩ, and the fall of the output signal is delayed similarly to the circuit of FIG. There is a drawback that the efficiency becomes worse.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a novel output buffer circuit which can eliminate the above-mentioned disadvantages inherent in the prior art. Is to do.

[0014]

In order to achieve the above object, an output buffer circuit according to the present invention comprises a differential amplifier comprising a transistor pair and a base electrode having a collector electrode connected to an output electrode of the differential amplifier. A first transistor connected to the first voltage source, a second transistor having a base electrode connected to the inverted output electrode of the differential amplifier and a collector electrode connected to the first voltage source, respectively. A third transistor in which a base electrode and a collector electrode are common and an emitter electrode is grounded;
A fourth transistor connected to the emitter electrode of the third transistor and having the emitter electrode grounded, and a first resistor connected between the emitter electrode of the second transistor and the collector electrode of the third transistor And a second resistor connected between the collector electrode and the emitter electrode of the fourth transistor.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a preferred embodiment of the present invention.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Referring to FIG. 1, one embodiment of the present invention is:
A differential amplifier composed of NPN transistors 7 and 8, resistors 5 and 6 and a current source 9, and an NPN transistor 1
0, 11, 13 and 14 and an output stage composed of resistors 12 and 15 are provided. This output stage receives the positive and negative outputs of the differential amplifier as inputs and outputs an output signal from an output terminal 3. Reference numerals 1 and 2 are input terminals to which an input signal and its inverted signal are respectively applied.

Next, the operation of the embodiment of the present invention shown in FIG. 1 will be described.

The input signals a and b are balanced-input from the two input terminals 1 and 2 of the differential amplifier, and a signal c and an inverted signal d obtained by amplifying them are output from the differential amplifier and output from the NPN transistors 10 and 11. Each is applied to the base. Here, when the input signal a rises, the inverted input signal b falls, so that the amplified signal c rises and the inverted amplified signal d falls. For this, transistor 1
The collector current of the transistor 14 decreases due to the current mirror effect of the current mirror circuit composed of the transistors 13 and 14.

On the other hand, the amplified signal c is applied to the base of the transistor 10, and the potential of the output terminal 3 rises. Conversely, when the input signal a falls, the inverted input signal b
Rise, the amplified signal c falls, and the inverted amplified signal d rises. For this, transistor 1
1 increases, and the collector current of the transistor 14 also increases due to the current mirror effect of the current mirror circuit composed of the transistors 13 and 14. Further, since the amplified signal c is applied to the base of the transistor 10, the potential of the output terminal 3 drops.

Here, the operation when the output waveform falls will be compared with the circuits shown in FIGS.

First, comparing with the circuit of FIG. 2, in the circuit of FIG. 1, a current source is connected in parallel to a resistor of the output stage, and this current source only outputs a current of the output stage when an output signal is at a low level. Since it is increased, the fall of the output signal becomes faster.

On the other hand, when compared with the circuit of FIG. 3, the impedance seen from the collector of the output transistor 14 is several hundred Ω to several KΩ, and the impedance seen from the output terminal to the ground by connecting the resistor 15 in parallel. Becomes smaller. Therefore, the fall of the output signal is improved to be faster.

In the embodiment of the present invention described above, an NPN transistor is used as a transistor.
Instead, it is needless to say that the present invention can be easily implemented by substituting a PNP transistor.

[0025]

As described above, according to the present invention,
By outputting the output of the differential amplifier via an output stage in which an emitter follower circuit and a current mirror circuit are combined, it is possible to output a waveform whose output waveform falls fast.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of the related art.

FIG. 3 is a circuit diagram showing another example of the related art.

[Explanation of symbols]

 1, 2 input terminal 3 output terminal 4 DC voltage source 5, 6 resistor 7, 8 NPN transistor 9 current source 10, 11 NPN transistor 12 resistor 13, 14 NPN transistor 15 …Resistor

Claims (1)

(57) [Claims] 1. A differential amplifier comprising a transistor pair, a first electrode having a base electrode connected to a non-inverting output electrode of the differential amplifier circuit and a collector electrode connected to a first voltage source. A second transistor having a base electrode connected to the inverted output electrode of the differential amplifier circuit and a collector electrode connected to the first voltage source;
A third transistor in which a base electrode and a collector electrode are common and an emitter electrode is grounded; and a base electrode is commonly connected to a base electrode of the third transistor and a collector electrode is connected to an emitter electrode of the first transistor. A fourth transistor having an emitter electrode grounded, a first resistor connected in series between an emitter electrode of the second transistor and a collector electrode of the third transistor, A second resistor connected between the collector electrode and the emitter electrode of the first transistor, a signal being input from two input terminals of the differential amplifier circuit, and an emitter electrode of the first NPN transistor being provided. An output buffer circuit, wherein a signal output is obtained from the output buffer circuit.