JP3367875B2 - Logarithmic conversion circuit and transconductor using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a logarithmic conversion circuit and a transconductor using the same.

[0002]

2. Description of the Related Art Conventionally, as a method of forming an active filter, there is a method of using transconductors G1 to G8 and a capacitor as shown in FIG. In order to widen the signal amplitude that can be handled, the transconductor is conventionally composed of a logarithmic conversion circuit 1 having a wide linear input range as shown in FIG. 13 and an antilogarithmic conversion circuit 2 composed of a differential pair of transistors Q20 and Q21. Has been configured.

As a logarithmic conversion circuit which can take a wide linear input range, for example, there is a logarithmic conversion circuit proposed in Japanese Patent Laid-Open No. 06-90127 shown in FIGS. 14 and 15 (a).

In the logarithmic conversion circuit shown in FIG. 14, a differential input signal is applied between IN + and IN-, feedback is applied through transistors Q5 and Q3 so that a current I1 flows through transistor Q1, and transistor Q2 is applied. Feedback is applied through the transistors Q6 and Q4 so that the current I2 (= I1) flows through the transistor. As a result, the emitter potentials V1 and V2 of the transistors Q1 and Q2 are respectively changed to the input terminals IN + and IN +.
The potential becomes a potential level-shifted by Vbe from the negative potential, and the voltage applied to the resistor R1 becomes equal to the differential input signal.

Assuming that the differential input signal voltage is Vd, a current I1-Vd / R1 flows through the transistor Q3, and a current I1-Vd / R1 flows through the transistor Q4. The converted voltage is applied to the transistors Q3 and Q4.
Is generated between the base and emitter of.

In the logarithmic conversion circuit shown in FIG. 14, when the transistors Q3 and Q4 are saturated, the transistor Q5 is reached.
And Q3 or the feedback circuit composed of the transistors Q6 and Q4 does not operate normally. Therefore, in order to operate the transistors Q3 and Q4 in a non-saturated state, 0.1V is applied between the collector and the emitter of the transistors Q3 and Q4.
A certain voltage Vce (sat) is required. Also, Q4 and Q5
The common emitter voltage Vc of is required to be about 0.1 V in order for the inverse logarithmic conversion circuit connected next to operate normally. Therefore, the minimum value Vc of the common mode input voltage in this logarithmic conversion circuit is
(〜0.1V) + Vce (sat) (〜0.1V) + Vbe (〜0.7V) is almost 0.9V
Will be.

Next, in the logarithmic conversion circuit shown in FIG. 15A, unlike the configuration shown in FIG. 14, since the transistors are not vertically stacked, the minimum value Vc (.about.0.
1V) + Vbe is almost 0.8V, which is 0.1V from the logarithmic conversion circuit of FIG.
The input voltage range can be widened accordingly.

However, the differential input signal voltage-output current characteristic of the transconductor realized by the configuration shown in FIG. 13 using the logarithmic conversion circuit shown in FIG.
As shown in, when the differential input voltage is applied, for example, about 1 V, the polarity of the operation of the transconductor is reversed. That is, there is a problem that the polarities of the differential output voltages of the logarithmic conversion circuit are reversed.

The operation of inverting the polarity will be briefly described. The linear input voltage range is represented by I1 × R1. When the differential input signal voltage Vd is in the linear input voltage range, as described above,
The transistors all operate in desaturation and V3 and V4 are log-transformed voltages of Vd while Vd is in the linear input voltage range.
Generate a potential of. When Vd becomes large and deviates from the linear input voltage range, at this time, all the current I1 flows through the resistor R1 and the transistor Q5 is turned off. This state is shown in FIG.
It shows in (b).

At this time, the currents I1 and I2 are transferred to the transistor Q6.
And the base potential V4 of the transistor Q6 is (I1 + I2) R
2 + Vbe | Q6 takes an almost constant value. Even in this state, the transistor Q6 operates as a grounded-emitter amplifier circuit, and the transistors Q3 and Q4 operate as a differential amplifier circuit. As a result, V8 drops according to the potential of IN-. When Vd is outside the linear input voltage range, V7 is V8 + I1 ×
Since it is decided by R1, as Vd increases (that is, the potential of IN + rises and the potential of IN- falls), V7 becomes
It goes down according to V8. Since V7 is lower than the potential of IN +, the transistor Q2 is also turned off. Current I5 tries to flow from the emitter of transistor Q1 but is supplied to collector I3
Is I3 = I5 / 2, the transistor Q1 is saturated, and the remaining current I5 / 2 is supplied from the base of the transistor Q1.

Since the transistor Q1 is saturated, the collector potential V3 of the transistor Q1 drops sharply from the emitter potential V5 to a potential higher by about 0.1V. But,
Since V5 rises according to the potential of IN +, therefore V3 also
It rises according to the potential of +. If Vd is further increased from this state (the potential of IN + is raised and the potential of IN- is lowered), V3 and V4 are eventually reversed and the polarities are reversed.

Therefore, in the filter realized by using this transconductor, once a voltage of about 1 V is applied to any one of the transconductors, the loop through the transconductor becomes positive feedback, and oscillation occurs. There was a problem of causing.

[0013]

As described above, in the conventional logarithmic conversion circuit having a wide linear input range, the common-mode input voltage range is narrowed or oscillation is caused for an excessive differential input signal voltage. There was a problem.

The present invention has been made in view of the above problems of the prior art, and an object thereof is to provide a logarithmic conversion circuit having a wide linear input range and a common mode input voltage and operating stably. That is.

[0015]

First and second amplification means for amplifying a differential input signal, and first and second level shift means for level shifting output voltages of the first and second amplification means. And the bases are respectively connected to the output terminals of the first and second level shift means, the emitters thereof are coupled to each other, and the first and second feedback means are fed back from the collector to the first and second amplifying means, respectively. A transistor, an impedance element disposed between the collectors of the first and second transistors, and a base of the first and second transistors.
Output means for extracting an output signal according to the voltage between the emitters.

[0016]

According to the logarithmic conversion circuit of the present invention, the output voltage of the amplifying means in the open loop when the voltage such that the positive input terminal becomes low is applied between the positive input terminal and the negative input terminal of the amplifying means used. , The base potential of the first or second transistor that turns off when a differential input signal voltage is applied outside the linear input voltage range even if it depends on the potential of the negative input terminal of the amplifying means. Since it becomes lower than the output voltage of the amplifying means, the differential input signal voltage input to the logarithmic conversion circuit goes out of the linear input voltage range and the polarity of the output voltage of the logarithmic conversion circuit is reversed. Since the voltage can be increased according to the voltage, the stability against an excessive differential input signal voltage can be improved.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 (a) is a diagram showing a logarithmic conversion circuit to which the present invention is applied, and FIG. 2 shows each node voltage when a differential input signal voltage Vd is applied to FIG. 1 (a).
Further, FIG. 3 is a differential input signal voltage-output current characteristic when the differential input signal voltage Vd is applied to the transconductor realized with the configuration shown in FIG.

In the logarithmic conversion circuit of FIG. 1A, the amplifying means 11 is constituted by the transistors Q1 and Q2 and the current sources I3 and I5.
And transistors Q3 and Q4 and current sources I4 and I6 constitute amplification means 12, and transistor Q7 and current source
I7 constitutes the level shift means 13 and includes a transistor Q8.
The current source I8 constitutes the level shift means 14, the base of the transistor Q1 which is the negative input terminal of the amplification means 11 is connected to the input terminal IN +, and the transistor Q1 which is the output terminal.
The collector of is connected to the base of the transistor Q5 via the level shift means 13, the base of the transistor Q3 which is the negative input terminal of the amplification means 12 is connected to the input terminal IN-, and the collector of the transistor Q3 which is the output terminal is , The base of the transistor Q6 via the level shift means 14, the emitters of the transistors Q5 and Q6 are coupled to each other and connected to the power source Vee via the resistor R2, and the collector of the transistor Q5 is the positive input terminal of the amplifying means 11. Is connected to the base of transistor Q2 which is
The collector of 6 is connected to the base of the transistor Q4 which is the positive input terminal of the amplifying means 12, and the transistors Q5 and Q6 are connected.
A resistor R1 is connected between the collectors of.

A differential input signal voltage is applied between the IN + and IN- terminals, and a voltage corresponding to the base-emitter voltage of the transistors Q5 and Q6 is output from the Out + and Out- terminals. Here, the operation of the logarithmic conversion circuit shown in FIG.
When the differential input signal voltage Vd is within the linear input voltage range,
As shown in FIG. 1B, the output of the amplifying means 11, 12 is changed to the level shifting means 13, 14 and the transistor Q5,
Negative feedback is applied to the positive inputs of the amplifying means 11 and 12 via the feedback circuit of the amplifying circuit composed of Q6, the current sources I1 and I2 and the resistors R1 and R2, and IN + and
The differential input signal voltage Vd applied to the IN- terminal is applied, and the current Vd / R1 flows through the resistor R1. Therefore, currents I1-Vd / R1 and I1 + Vd / R1 flow through the transistors Q5 and Q6, respectively.

The base-emitter voltages of the transistors Q5 and Q6 are logarithmically converted of the current flowing through them, and
It is current-voltage converted and is output as a logarithmically converted voltage from the differential input signal voltage from the Out + and Out- terminals.

The linear input voltage range is the range in which the above operation is performed, and Vd at which I1−Vd / R1 = 0, that is, I1 × R1 is the linear input voltage range. If the differential input signal voltage Vd tries to exceed the linear input voltage range, all the current I1 is
To the transistor Q6 through the transistor Q5
Is turned off and the base potential V41 of the transistor Q6 is determined as described in the conventional example. Further, the transistor Q2 is turned off, the transistor Q1 is saturated, and the amplifying means 1
The collector potential V3 of the transistor, which is the output of 1, is determined as described in the conventional example. The difference from the conventional example is that the transistor Q5
The base potential V31 of the transistor is lower than V3 by the base-emitter voltage Vbe | Q7 of the transistor Q7 constituting the level shift means 13, and in the conventional example, when Vd deviates from the linear input voltage range as shown in FIG. The base potential of the transistor Q5 (= collector potential of the transistor Q1) V3 is lowered by only about 0.9V, whereas in the logarithmic conversion circuit of the present invention, as shown in FIG.
1 is down to about 0.1V.

Therefore, Vd is further increased by ΔVd, that is,
When the potential of IN + rises by ΔVd / 2 and the potential of IN− falls by ΔVd / 2, the collector potential V3 of the transistor Q1 and the base potential V31 of the transistor Q5 which are saturated rise according to the potential of IN +, but V31 rises. Base potential of transistor Q6
In order to make it equal to V41, the potential of IN + must be raised by the base-emitter voltage Vbe | Q7 of the transistor Q7, which is the level shift voltage of the level shift means 13 as compared with the conventional example (
That is, V31 and V41 are not equal unless Vd is increased by double Vbe | Q7.

Therefore, even if the differential input signal voltage is larger than the linear input voltage range, the differential input signal voltage in which the polarity of the output of the logarithmic conversion circuit changes can be made larger than before.
Stability can be improved.

FIG. 3 is a diagram showing the input voltage-output current characteristics of the transconductor using the logarithmic conversion circuit of FIG. 1 (a), and as described above, the output polarity inversion does not occur. FIG. 4 (a) is a diagram showing a logarithmic conversion circuit according to a second embodiment of the present invention, and FIG. 5 shows each node voltage when the differential input signal voltage Vd is applied to FIG. 4 (a). ing. Also,
FIG. 6 shows the differential input signal voltage when the differential input signal voltage Vd is applied to the transconductor realized by the configuration shown in FIG.
-Output current characteristics.

In the logarithmic conversion circuit of FIG. 4 (a), the amplifying means 1 is constituted by the transistors Q1 and Q2 and the current sources I3, I5 and I9.
1 and includes transistors Q3 and Q4 and a current source I4.
The amplifying means 12 is constituted by I6 and I10, and the amplifying means 11 is provided.
The base of the transistor Q1 which is the positive input terminal of is connected to the input terminal IN +. The collector of the transistor Q1 which is the negative output terminal is connected to the base of the transistor Q5, and the transistor Q3 which is the positive input terminal of the amplifying means 12.
The base of is connected to the input terminal IN-. The collector of the transistor Q3, which is the negative output terminal, is connected to the base of the transistor Q6, the emitters of the transistors Q5 and Q6 are connected to each other and connected to the power source Vee via the resistor R2, and the collector of the transistor Q5 is the amplifying means 11. Is connected to the base of the transistor Q2, which is the negative input terminal, and the collector of the transistor Q2, which is the positive output terminal. The collector of the transistor Q6 is connected to the base of the transistor Q4, which is the negative input terminal of the amplifying means 12, and the collector of the transistor Q4, which is the positive output terminal.
A resistor R1 is connected between the collectors of 5 and Q6.

In this way, the differential input signal voltage is applied between the IN + and IN- terminals and the bases of the transistors Q5 and Q6 are connected.
The voltage corresponding to the emitter voltage is output from the Out +, Out- terminals.

The operation of the logarithmic conversion circuit shown in FIG. 4A will be described. When the differential input signal voltage Vd is within the linear input voltage range, as shown in 4 (b), the amplifying means 11 and 12 each have a voltage follower configuration in which the positive output terminal and the negative input terminal are connected. The resistor R1 has IN + and
The differential input signal voltage Vd applied to the IN- pin is applied. Further, from the negative output terminals of the amplifying means 11 and 12, via the feedback circuit of the amplifying circuit composed of the transistors Q5 and Q6, the current sources I1 and I2 and the resistors R1 and R2, the amplifying means 11 and
Negative feedback is applied to the negative input terminal 12 and the differential input signal voltage Vd applied to the IN + and IN- terminals is applied to both ends of the resistor R1 even in this loop.

Therefore, a current Vd / R1 flows through the resistor R1, and I1-Vd / R1 flows through the transistors Q5 and Q6, respectively.
A current of R1, I1 + Vd / R1 flows. The base-emitter voltages of the transistors Q5 and Q6 are obtained by logarithmically converting the currents flowing through them and current-voltage converting them.
It is output from the Out- terminal as a voltage obtained by logarithmically converting the differential input signal voltage. The linear input voltage range is Vd where I1-Vd / R1 = 0 within the range where the above operation is performed, that is, I1 × R1 is the linear input voltage range.

When Vd tries to exceed the linear input voltage range, all the current I1 flows to the transistor Q6 through the resistor R1, the transistor Q5 is turned off, and the base potential V3 of the transistor Q5 drops to about 0.9V. This is as described in the conventional example. Further, when the differential input signal voltage becomes larger than the linear input voltage range, the transistor Q5 is accordingly
The increase in the base potential V3 of is as described in the conventional example.

Although the base potential V4 of the transistor Q6 is determined as described in the conventional example, in this logarithmic conversion circuit, when Vd is increased beyond the linear input voltage range, the current flowing in the transistor Q2 gradually. I9 flows to the transistor Q6 via R1, and the emitter potential V9 of the transistor Q6 becomes high. The base potential V4 of the transistor Q6 when Vd becomes large and all the current I9 flows into the transistor Q6 via R1, is (I1 + I2 + I9) R2 + Vbe | Q6, and even if Vd is made larger than this, it is almost the same. Takes a constant value.

Therefore, the transistor Q6 is different from the conventional one.
Since the base potential V4 of can be increased by I9 × R2,
The differential input signal voltage Vd becomes larger than the linear input voltage range, the base potential V3 of the transistor Q5 rises, the magnitude relationship with the base potential V4 of the transistor Q6 reverses, and the differential input signal voltage in which the polarity reverses is changed from the conventional one. Since it can be made larger, stability can be improved.

FIG. 6 is a diagram showing the input voltage-output current characteristics of the transconductor using the logarithmic conversion circuit of FIG. 4 (a). As described above, the output polarity inversion does not occur. In the logarithmic conversion circuit shown in FIG. 4A, the current sources I9 and I1 and the current sources I2 and I10 may be integrated.

Further, as shown in FIG. 7, the level shift means described in the logarithmic conversion circuit of FIG. 1A is applied to the logarithmic conversion circuit of FIG. The input signal voltage can be further increased.

As shown in FIG. 8, in the logarithmic conversion circuit shown in FIG. 4A, the position where the resistor R1 is provided is set from the collector of the transistors Q5 and Q6 to the transistor Q1.
And between the emitters of Q2.

FIG. 9 shows each node voltage when the differential input signal voltage Vd is applied to the logarithmic conversion circuit shown in FIG.
10 is a differential input signal voltage-output current characteristic when the differential input signal voltage Vd is applied to the transconductor realized by the configuration shown in FIG.

The operation of the logarithmic conversion circuit shown in FIG. 8 will be described. In order to simplify the description, the relation of the currents of the current sources shown in FIG. 8 is as follows. I1 = I2 = I3 = I4 = I9 = I10 = I
5/2 = I6 / 2 When the differential input signal voltage Vd is within the linear input voltage range, the current I3 in each of the transistors Q1 and Q2 is
And I4 are fed back from the collectors of the transistors Q1 and Q3 to the emitters of the transistors Q1 and Q3 through the transistors Q5 and Q6 and the diodes Q2 and Q4 which operate as a level shift stage, respectively. As a result, the emitter potentials V5 and V6 of the transistors Q1 and Q3 become potentials that are level-shifted by Vbe from the potentials of the input terminals IN + and IN-, respectively.

That is, the differential input signal voltage Vd applied to IN + and IN- is applied to both ends of the resistor R1. At this time, the resistance R1
A current of Vd / R1 flows to the diode, and I9 + V flows to the diode Q2.
A current of d / R1 flows, a current of I10-Vd / R1 flows through the diode Q4, a current of I1-Vd / R1 flows through the transistor Q5, and a current of I2 + Vd / R1 flows through the transistor Q6. Flowing.

The base-emitter voltages of the transistors Q5 and Q6 are logarithmically converted and current-voltage converted, respectively, and the currents flowing through the transistors Q5 and Q6 are output as logarithmically converted voltages of the differential input signal voltages from the Out + and Out- terminals. To be done.

The linear input voltage range is the range in which the above operation is performed, and Vd at which I1−Vd / R1 = 0, that is, I1 × R1 is the linear input voltage range. When the differential input signal voltage Vd tries to exceed the linear input voltage range, all the current I1 is diode Q.
2 and the resistor R1 to the current source I6. At this time, the current
All of I4 flows to the current source I6 via the transistor Q3, and I1 + I4 = I6. Therefore, the current I10 does not flow via the diode Q4, but all flows to the transistor Q6.

Further, since the current does not flow through the transistor Q5, the transistor Q5 is turned off. As a result, the feedback through the transistor Q5 is lost, the transistor Q1 is saturated, and the collector potential V3 of the transistor Q1 drops to about 0.9V.

Further, when the differential input signal voltage Vd becomes larger than the linear input voltage range, the transistor Q5 is responded accordingly.
The increase in the base potential V3 of is as described in the conventional example.

Further, as shown in FIG. 9, V5 rises and the base current Ib of the transistor Q1 passes through the resistor R1 and becomes the current source.
Since it flows to I6, the current supplied via transistor Q3 changes from I4 to I4-Ib, and Ib is the amount of transistor Q
It flows into the base of 6 and raises the base potential. When Vd becomes large and Ib = I4, all the current supplied from the current source I4 flows into the base of the transistor Q6, and the base potential V4 of the transistor Q6 can be increased by I4 × R2 compared to the conventional one, so that the differential The input signal voltage Vd becomes larger than the linear input voltage range, the base potential V3 of Q5 rises, and Q6
Since the magnitude relationship with the base potential V4 of 1 is reversed and the differential input signal voltage whose polarity is reversed can be made larger than before, stability can be improved.

As shown in FIG. 10, it is a diagram showing the input voltage-output current characteristics of the transconductor using the logarithmic conversion circuit of FIG. 8, and as described above, the output polarity inversion does not occur.

In the logarithmic conversion circuit shown in FIG.
The current sources I9 and I1 and the current sources I2 and I10 may be combined. Further, as shown in FIG. 11, the level shift means described in the logarithmic conversion circuit of FIG. 1A is applied to the logarithmic conversion circuit of FIG. 8 to further increase the differential input signal voltage whose polarity is inverted. it can.

When integrating the logarithmic conversion circuit of the present invention described above and the transconductor by the inverse logarithmic conversion circuit using the differential pair as shown in FIG. 13, it is used in the logarithmic conversion circuit as shown in FIG. The current source generates a current in inverse proportion to the value of the integrated resistance element, and the current source used in the inverse logarithmic conversion circuit is inversely proportional to the value of the resistance element Rext provided outside the integrated circuit. By generating a current in the transistor, even if the resistance value of the integrated resistance element varies, the variation in transconductance realized by the transconductor can be suppressed.

The transconductor shown in FIG. 13 using the logarithmic conversion circuit of FIG. 1A will be described in detail below.
The transconductance G is the ratio of the maximum current that can be output by the transconductor to the linear input voltage range that can be input, and is expressed by the following equation.

G = I20 / (2R1 * I1) The bias current including the current I1 of the logarithmic conversion circuit is set to ln
The emitter area ratio of the transistors QB1 and QB2 is set to 1: 4 so that the resistance Rint that integrates 4 times VT (= kT / q, where k is the Boltzmann constant, T is the absolute temperature, and q is the electron charge) is applied. The current obtained by the VT proportional current source configured as described above is supplied to the transistors QB4 to QB14 and the resistors RB2 to RB12.
The current mirror circuit composed of is supplied in duplicate and supplies the bias current including the current I20 of the antilogarithmic conversion circuit.
ln4 times the VT is applied to the resistance Rext provided outside the integrated circuit, so that the current obtained by the VT proportional current source configured to set the emitter area ratio of the transistors QB15 and QB16 to 1: 4 is applied to the transistors QB15 to QB23 and the resistance. RB1
The transconductance G which is duplicated and supplied by the current mirror circuit composed of 3 to RB19 is G = Rint / (R1 * Rext), and even if the integrated resistances (R1, Rinit) vary by α times, As shown in the equation, α is canceled. Moreover, the accuracy of the resistor Rext provided outside the integrated circuit is 1
%, So the transconductance hardly varies.

Since the linear input voltage range is the product of R1 and the current generated so as to be inversely proportional to the value of the integrated resistance element, even if the integrated resistance is multiplied by α, the linear input voltage range is increased. The range is constant and does not vary.

As shown in FIG. 19, the current generating means shown in FIG. 18 uses a transistor QB1 to apply a bias current including the current I20 of the antilogarithmic function circuit to a resistor Rint in which VT of ln4 times is integrated. A current mirror circuit (QB16, QB17, Rint2, R) outputs the current obtained by the VT proportional current source configured to set the emitter area ratio of QB2 to 1: 4.
ext), one of the resistors is a resistor Rext provided outside the product circuit as shown in the figure, for example, Rint2 = Rint
By doing so, the current flowing through the transistor QB17 may be realized as (ln4 * VT) / Rext.

As described above, the current source used in the antilogarithmic conversion circuit is integrated by generating current so as to be inversely proportional to the value of the resistance element Rext provided outside the integrated circuit. Even if the resistance element varies, the transconductance and the linear input voltage range can be prevented from varying.

[0051]

As described above, according to the logarithmic conversion circuit and transconductor of the present invention, it is possible to provide a logarithmic conversion circuit and transconductor having a wide linear input range and a common mode input voltage and operating stably.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a logarithmic conversion circuit according to a first embodiment of this invention.

FIG. 2 is an operation explanatory diagram of the logarithmic conversion circuit according to the first embodiment of the present invention.

FIG. 3 is a characteristic diagram of input voltage-output current of a transconductor using the logarithmic conversion circuit according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of a logarithmic conversion circuit according to a second embodiment of this invention.

FIG. 5 is an operation explanatory diagram of the logarithmic conversion circuit according to the second embodiment of the present invention.

FIG. 6 is a characteristic diagram of input voltage-output current of a transconductor using the logarithmic conversion circuit according to the second embodiment of the present invention.

FIG. 7 is an explanatory diagram of a logarithmic conversion circuit according to a third embodiment of this invention.

FIG. 8 is an explanatory diagram of a logarithmic conversion circuit according to a fourth embodiment of this invention.

FIG. 9 is an operation explanatory diagram of the logarithmic conversion circuit according to the fourth embodiment of the present invention.

FIG. 10 is a characteristic diagram of input voltage-output current of a transconductor using the logarithmic conversion circuit according to the fourth embodiment of the present invention.

FIG. 11 is an explanatory diagram of a logarithmic conversion circuit according to a fifth embodiment of this invention.

FIG. 12 is a configuration diagram of an active filter using the transconductor of the present invention.

FIG. 13 is a configuration diagram of a transconductor of the present invention.

FIG. 14 is a configuration diagram showing a conventional logarithmic conversion circuit.

FIG. 15 is an operation explanatory diagram showing an operation of a conventional logarithmic conversion circuit.

FIG. 16: Input of transconductor using conventional logarithmic conversion circuit Input voltage of transconductor of the present invention
-Output

FIG. 17 is an operation explanatory diagram showing an operation of a conventional logarithmic conversion circuit.

FIG. 18 is an explanatory diagram showing a transconductor of the present invention.

FIG. 19 is an explanatory diagram showing a transconductor of the present invention.

[Explanation of symbols]

1. Logarithmic conversion circuit 2 ... Inverse logarithmic conversion circuit 11, 12 ... Amplifying means 13, 14 ... Level shift means Q1-Q8 ... transistors IN +, IN -... Input terminals Out +, Qut -... Output terminal of logarithmic variable circuit I1 to I10 ... Current source Vcc: First power supply potential point Vee: Second power supply potential point R1, R2 ・ ・ ・ Resistance

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-90127 (JP, A) JP-A-1-177208 (JP, A) JP-A-61-214811 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H03G 11/08 H03F 3/34 H03H 11/04

Claims (9)

(57) [Claims] 1. A first and second amplifying means for amplifying an input signal, and first and second level shift means for level shifting the output voltages of the first and second amplifying means, respectively. And the bases are connected to the output terminals of the first and second level shifting means, the emitters are coupled to each other, and the first and second feedback means are provided from the collector to the first and second amplifying means, respectively. A second transistor; an impedance element arranged between the collectors of the first and second transistors; and an output means for extracting an output signal according to the base-emitter voltage of the first and second transistors. A logarithmic conversion circuit characterized by being provided. 2. A first and a second amplifying means having first and second input terminals respectively connected to a positive input terminal and having a feedback path from a positive output terminal to a negative input terminal; Bases are respectively connected to the negative output terminals of the first and second amplifying means, emitters of the second amplifying means are coupled to each other, and first and second feedback elements are provided from the collectors to the negative input terminals of the first and second amplifying means. A second transistor, an impedance element connected between the collectors of the first and second transistors, and an output unit for extracting an output signal according to the base-emitter voltage of the first and second transistors. A logarithmic conversion circuit characterized in that 3. First and second amplifying means having first and second input terminals respectively connected to a positive input terminal and having a feedback path from a positive output terminal to a negative input terminal; And first and second level shifting means for level shifting the negative output voltage of the second amplifying means, and bases connected to the output terminals of the first and second level shifting means, respectively, and emitters thereof being mutually connected. An impedance connected between the first and second transistors coupled to each other and fed back from the collector to the negative input terminals of the first and second amplifying means, and the collectors of the first and second transistors. A logarithmic conversion circuit comprising an element and an output means for extracting an output signal corresponding to the base-emitter voltage of the first and second transistors. 4. A first and second transistor having a base connected to the first and second input terminals, respectively, and a collector having first and second levels to the emitters of the first and second transistors, respectively. Third and fourth transistors connected via shift means and having emitters coupled to each other; impedance element connected between collectors of the third and fourth transistors; and first and second transistors The collector is the third
And a base of a fourth transistor,
And a output means for extracting an output signal according to the base-emitter voltage of the fourth transistor, and a logarithmic conversion circuit. 5. A first and second transistor having a base connected to the first and second input terminals, respectively, and a collector having first and second levels to the emitters of the first and second transistors, respectively. Third and fourth transistors connected via shift means and having emitters coupled to each other; impedance element connected between collectors of the third and fourth transistors; and first and second transistors Means for extracting an output signal according to the base-emitter voltage of the third and fourth transistors, which is connected from the collector to the third and fourth bases through third and fourth level shift means. A logarithmic conversion circuit comprising: 6. A first and second transistor having a base connected to the first and second input terminals, respectively, and a collector having first and second levels to the emitters of the first and second transistors, respectively. Third and fourth transistors connected via shift means and having their emitters coupled to each other; an impedance element connected between the emitters of the first and second transistors; and the first and second transistors The collector is the third
And a base of a fourth transistor,
And a output means for extracting an output signal according to the base-emitter voltage of the fourth transistor, and a logarithmic conversion circuit. 7. A first and second transistor having a base connected to first and second input terminals, respectively, and a collector having first and second levels to the emitters of the first and second transistors, respectively. Third and fourth transistors connected via shift means and having their emitters coupled to each other; an impedance element connected between the emitters of the first and second transistors; and the first and second transistors Means for extracting an output signal according to the base-emitter voltage of the third and fourth transistors, which is connected from the collector to the third and fourth bases through third and fourth level shift means. A logarithmic conversion circuit comprising: 8. A logarithmic converter, and wherein the at transformer conductors constituted by the inverse logarithmic conversion circuit configured by the differential pair, the logarithmic conversion circuit is a logarithmic conversion circuit of claims 1 to 7, wherein A transconductor. 9. A transconductor formed on an integrated circuit, wherein the transconductor is the transconductor according to claim 8, and the impedance element of the logarithmic conversion circuit is an integrated resistance element. The conversion circuit includes first bias current generating means using an integrated resistance element, and the antilog conversion circuit includes second bias current generating means using a resistance element provided outside the integrated circuit. A transconductor characterized by being provided.