JPH1188093A - Logarithm conversion circuit and transformer conductor using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve stability on excessive differential input signal voltage by enlarging input voltage by which the polarity of the output voltage of a logarithm conversion circuit is inverted in accordance with level shift voltage. SOLUTION: Differential input signal voltage is applied between IN<+> and IN<-> terminals and voltage corresponding to the base emitter voltage of transistors Q5 and Q6 is outputted from out<+> and out<-> terminals. The base potential V31 of the transistor Q5 is lower than V3 by the base/emitter voltage of the transistor Q7 constituting the level shift means 13 by the level shift means 13. Thus, base voltage V31 does not become equal to V41 unless the potential of IN<+> is raised by the base/emitter voltage of the transistor Q7, which is the level shift voltage of the level shift means 13. Namely, differential input signal voltage by which the polarity of logarithm conversion circuit output changes can be made larger than former one even if differential input signal voltage is given to be larger than a linear input voltage range.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logarithmic conversion circuit and a transconductor using the same.

[0002]

2. Description of the Related Art Conventionally, as a method of constructing an active filter, there is a method of using transconductors G1 to G8 and a capacitor as shown in FIG. Conventionally, in order to widen the signal amplitude that can be handled, the transconductor has a logarithmic conversion circuit 1 having a wide linear input range as shown in FIG. 13 and an antilogarithmic conversion circuit 2 composed of a differential pair including transistors Q20 and Q21. Has been composed.

As a logarithmic conversion circuit capable of providing a wide linear input range, there is a logarithmic conversion circuit proposed in, for example, Japanese Patent Application Laid-Open No. 06-90127 shown in FIGS.

In the logarithmic conversion circuit shown in FIG. 14, a differential input signal is applied between IN + and IN-, feedback is applied via transistors Q5 and Q3 so that current I1 flows through transistor Q1, and transistor Q2 Is fed back via the transistors Q6 and Q4 so that the current I2 (= I1) flows through. As a result, the emitter potentials V1 and V2 of the transistors Q1 and Q2 become the input terminals IN + and IN +, respectively.
The potential becomes a level shifted by Vbe from the potential of-, and the voltage applied to the resistor R1 becomes equal to the differential input signal.

Assuming that the differential input signal voltage is Vd, a current I1-Vd / R1 flows through the transistor Q3, and a current I1-Vd / R1 flows through the transistor Q4. The converted voltage is applied to transistors Q3 and Q4.
Occurs between the base and the emitter of

In the logarithmic conversion circuit shown in FIG. 14, when transistors Q3 and Q4 become saturated, transistor Q5
And Q3 or the feedback circuit constituted by the transistors Q6 and Q4 does not operate normally. Therefore, in order to operate the transistors Q3 and Q4 in a non-saturated state, a voltage of 0.1 V is applied between the collector and the emitter of the transistors Q3 and Q4.
Voltage Vce (sat) is required. Q4 and Q5
The common emitter voltage Vc is required to be about 0.1 V in order to normally operate the antilogarithmic conversion circuit connected next. Therefore, the minimum value Vc of the common mode input voltage in this logarithmic conversion circuit
(~ 0.1V) + Vce (sat) (~ 0.1V) + Vbe (~ 0.7V) is almost 0.9V
Will be.

Next, in the logarithmic conversion circuit shown in FIG. 15A, unlike the configuration shown in FIG. 14, since the transistors are not stacked vertically, the minimum value Vc (〜0.
1V) + Vbe is approximately 0.8V, which is 0.1V from the logarithmic conversion circuit in FIG.
The input voltage range can be widened accordingly.

However, the differential input signal voltage-output current characteristics of the transconductor realized by the configuration shown in FIG. 13 using the logarithmic conversion circuit shown in FIG.
As shown in (1), if the differential input voltage is applied, for example, by about 1 V, the polarity of the operation of the transconductor is reversed. That is, there is a problem that the polarity of the differential output voltage of the logarithmic conversion circuit is reversed.

Here, the operation of reversing the polarity will be briefly described. The linear input voltage range is represented by I1 × R1. When the differential input signal voltage Vd is in the linear input voltage range, as described above,
All transistors operate in non-saturation and V3 and V4 as log transformed voltages of Vd while Vd is in the linear input voltage range.
Generates a potential of When Vd increases and departs from the linear input voltage range, all the current I1 flows to the resistor R1 and the transistor Q5 is turned off. This situation is shown in FIG.
(B).

At this time, currents I1 and I2 are supplied to transistor Q6.
And the base potential V4 of the transistor Q6 becomes (I1 + I2) R
It takes an almost constant value at 2 + Vbe | Q6. Even in this state, the transistor Q6 operates as a common emitter amplifier circuit, and the transistors Q3 and Q4 operate as a differential amplifier circuit. As a result, V8 decreases according to the potential of IN-. If Vd falls outside the linear input voltage range, V7 becomes V8 + I1 ×
Since it is determined by R1, as Vd increases (that is, the potential of IN + rises and the potential of IN- falls), V7 becomes
Decrease according to V8. Since V7 is lower than the potential of IN +, the transistor Q2 is also turned off. A current I5 is supplied from the emitter of the transistor Q1 to the collector, but the current I3 is supplied to the collector.
Since I3 = I5 / 2, the transistor Q1 is saturated and the remaining current I5 / 2 is supplied from the base of the transistor Q1.

Since the transistor Q1 is saturated, the collector potential V3 of the transistor Q1 drops sharply from the emitter potential V5 to a potential higher by about 0.1 V. But,
Since V5 rises according to the potential of IN +, V3
Increases according to the potential of +. In this state, when Vd is further increased (the potential of IN + is increased and the potential of IN- is decreased), V3 and V4 are reversed, and the polarity is reversed.

Therefore, in a filter realized using this transconductor, once a voltage of about 1 V is applied to any one of the transconductors, the loop through the transconductor becomes a positive feedback, and the oscillation occurs. Had the problem of causing

[0013]

As described above, in the conventional logarithmic conversion circuit having a wide linear input range, the common-mode input voltage range is narrowed or oscillation is caused for an excessively large differential input signal voltage. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to provide a logarithmic conversion circuit having a wide linear input range and a wide common-mode input voltage and operating stably. That is.

[0015]

SUMMARY OF THE INVENTION First and second amplifying means for amplifying a differential input signal, and first and second level shifting means for level shifting output voltages of the first and second amplifying means. The first and second level shift means have their bases connected to their respective output terminals, the emitters are coupled to each other, and the collectors are fed back to the first and second amplifying means respectively. A transistor; an impedance element disposed between the collectors of the first and second transistors; and a base of the first and second transistors.
Output means for extracting an output signal corresponding to the voltage between the emitters.

[0016]

According to the logarithmic conversion circuit of the present invention, the output voltage of the amplifying means at the time of open loop is applied between the positive input terminal and the negative input terminal of the amplifying means used so that the voltage of the positive input terminal becomes low. The base potential of the first or second transistor which is turned off when the differential input signal voltage is applied out of the linear input voltage range even when the potential of the negative input terminal of the amplifying means depends on the level shift means. The output voltage of the logarithmic converter becomes lower than the output voltage of the amplifying means. Since the voltage can be increased according to the voltage, the stability against an excessively large differential input signal voltage can be improved.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A shows a logarithmic conversion circuit to which the present invention is applied, and FIG. 2 shows each node voltage when the differential input signal voltage Vd is applied to FIG. 1A.
FIG. 3 shows a differential input signal voltage-output current characteristic when a differential input signal voltage Vd is applied to the transconductor realized by the configuration shown in FIG.

In the logarithmic conversion circuit shown in FIG. 1A, amplifying means 11 includes transistors Q1, Q2 and current sources I3, I5.
And the amplifying means 12 is composed of the transistors Q3 and Q4 and the current sources I4 and I6.
I7 constitutes the level shift means 13, and the transistor Q8
And a current source I8 constitute a level shift means 14. The base of a transistor Q1 which is a negative input terminal of the amplifying means 11 is connected to an input terminal IN +, and a transistor Q1 which is an output terminal.
Is connected to the base of the transistor Q5 via the level shift means 13, the base of the transistor Q3 which is the negative input terminal of the amplifying means 12 is connected to the input terminal IN-, and the collector of the transistor Q3 which is the output terminal is , The emitters of the transistors Q5 and Q6 are coupled to each other and connected to the power supply Vee via a resistor R2, and the collector of the transistor Q5 is connected to the positive input terminal of the amplifying means 11. Is connected to the base of the transistor Q2,
6 is connected to the base of the transistor Q4, which is the positive input terminal of the amplifier 12, and the transistors Q5 and Q6
The resistor R1 is connected between the collectors.

A differential input signal voltage is applied between the IN + and IN- terminals, and a voltage corresponding to the base-emitter voltage of the transistors Q5 and Q6 is output from the Out + and Out- terminals. Here, the operation of the logarithmic conversion circuit shown in FIG.
When the differential input signal voltage Vd is within the linear input voltage range,
As shown in FIG. 1B, the level shift means 13 and 14 and the transistor Q5,
Negative feedback is applied to the positive inputs of the amplifying means 11 and 12 via a feedback circuit including an amplifying circuit composed of Q6, current sources I1 and I2, and resistors R1 and R2.
The differential input signal voltage Vd applied to the IN- terminal is applied, and a current of Vd / R1 flows through the resistor R1. Therefore, currents I1-Vd / R1 and I1 + Vd / R1 flow through the transistors Q5 and Q6, respectively.

The base-emitter voltages of the transistors Q5 and Q6 are logarithmically converted from the current flowing therethrough, and
It is current-voltage converted and is output from the Out + and Out- terminals as a voltage obtained by logarithmically converting the differential input signal voltage.

The linear input voltage range is a range in which the above operation is performed, and Vd where I1−Vd / R1 = 0, that is, I1 × R1 is a linear input voltage range. If the differential input signal voltage Vd tries to exceed the linear input voltage range, all the currents I1 are equal to the resistance R1.
Through the transistor Q6, and the transistor Q5
Is turned off, and the base potential V41 of the transistor Q6 is determined as described in the conventional example. Further, the transistor Q2 is turned off, the transistor Q1 is saturated, and the amplifying means 1
As described in the conventional example, the collector potential V3 of the transistor, which is the output of 1, is determined. The difference from the conventional example is that the level shift means 13 causes the transistor Q5
Is lower than V3 by the base-emitter voltage Vbe | Q7 of the transistor Q7 constituting the level shift means 13. In the conventional example, when Vd deviates from the linear input voltage range as shown in FIG. The base potential V3 of the transistor Q5 (= collector potential of the transistor Q1) V3 drops only by about 0.9 V, whereas the logarithmic conversion circuit of the present invention, as shown in FIG.
1 drops to about 0.1V.

Therefore, Vd further increases by ΔVd, that is,
When the potential of IN + rises by ΔVd / 2 and the potential of IN− falls by ΔVd / 2, the collector potential V3 of the transistor Q1 and the base potential V31 of the transistor Q5 rise according to the potential of IN +, but V31 rises. Base potential of transistor Q6
To make it equal to V41, the potential of IN + must be increased by the base-emitter voltage Vbe | Q7 of the transistor Q7, which is the level shift voltage of the level shift means 13, as compared with the prior art (
That is, V31 and V41 are not equal unless Vd is increased by twice Vbe | Q7.

Therefore, even if the differential input signal voltage is larger than the linear input voltage range, the differential input signal voltage at which the polarity of the logarithmic conversion circuit output changes can be made larger than before.
Stability can be improved.

FIG. 3 is a diagram showing the characteristics of the input voltage-output current of the transconductor using the logarithmic conversion circuit of FIG. 1 (a). As described above, no polarity reversal of the output occurs. FIG. 4A is a diagram showing a logarithmic conversion circuit according to a second embodiment of the present invention. FIG. 5A shows each node voltage when the differential input signal voltage Vd is applied to FIG. ing. Also,
FIG. 6 shows the differential input signal voltage when the differential input signal voltage Vd is applied to the transconductor realized by the configuration shown in FIG.
-Output current characteristics.

In the logarithmic conversion circuit shown in FIG. 4A, the amplifying means 1 includes transistors Q1, Q2 and current sources I3, I5, I9.
1 and transistors Q3, Q4 and current sources I4,
I6 and I10 constitute the amplifying means 12, and the amplifying means 11
The base of the transistor Q1, which is the positive input terminal of the transistor Q1, is connected to the input terminal IN +. The collector of the transistor Q1 which is the negative output terminal is connected to the base of the transistor Q5, and the transistor Q3 which is the positive input terminal of the amplification means 12 is connected.
Is connected to the input terminal IN-. The collector of the transistor Q3, which is the negative output terminal, is connected to the base of the transistor Q6. The emitters of the transistors Q5 and Q6 are connected to each other and connected to the power supply Vee via the resistor R2. Is connected to the base of the transistor Q2, which is the negative input terminal, and the collector of the transistor Q2, which is the positive output terminal. The collector of the transistor Q6 is connected to the base of the transistor Q4, which is the negative input terminal of the amplifier 12, and to the collector of the transistor Q4, which is the positive output terminal.
A resistor R1 is connected between the collectors of 5 and Q6.

Thus, the differential input signal voltage is applied between the IN + and IN- terminals, and the bases of the transistors Q5 and Q6
A voltage corresponding to the emitter voltage is output from the Out + and Out- terminals.

The operation of the logarithmic conversion circuit shown in FIG. When the differential input signal voltage Vd is within the linear input voltage range, as shown in FIG. 4B, the amplifying means 11 and 12 each have a voltage follower configuration in which the positive output terminal and the negative input terminal are connected. And IN + and
The differential input signal voltage Vd applied to the IN- terminal is applied. Further, the amplification means 11 and 12 are connected to the negative output terminals of the amplification means 11 and 12 via a feedback circuit including an amplification circuit including transistors Q5 and Q6, current sources I1 and I2, and resistors R1 and R2.
Negative feedback is applied to the negative input terminal 12 and also in this loop, the differential input signal voltage Vd applied to the IN + and IN- terminals is applied to both ends of the resistor R1.

Accordingly, a current of Vd / R1 flows through the resistor R1, and I1-Vd / R1 flows through the transistors Q5 and Q6, respectively.
The current of R1, I1 + Vd / R1 flows. The base-emitter voltages of the transistors Q5 and Q6 are log-converted and current-voltage-converted to the currents flowing therethrough.
It is output from the Out- terminal as a voltage obtained by logarithmically converting the differential input signal voltage. The linear input voltage range is a range in which the above operation is performed, and Vd where I1−Vd / R1 = 0, that is, I1 × R1 is a linear input voltage range.

If Vd exceeds the linear input voltage range, all the current I1 flows to the transistor Q6 via the resistor R1, turning off the transistor Q5 and lowering the base potential V3 of the transistor Q5 to about 0.9V. This is as described in the conventional example. Further, when the differential input signal voltage becomes larger than the linear input voltage range, the transistor Q5 responds accordingly.
Is increased as described in the conventional example.

Although the base potential V4 of the transistor Q6 is determined as described in the conventional example, in this logarithmic conversion circuit, when Vd increases beyond the linear input voltage range, the current flowing through the transistor Q2 gradually increases. I9 flows to the transistor Q6 via R1, and the emitter potential V9 of the transistor Q6 increases. The base potential V4 of the transistor Q6 when Vd increases and all the current I9 flows through the transistor Q6 via R1 is (I1 + I2 + I9) R2 + Vbe | Q6. Take a certain value.

Therefore, compared to the conventional case, the transistor Q6
Base potential V4 can be increased by I9 × R2,
The differential input signal voltage Vd becomes larger than the linear input voltage range, the base potential V3 of the transistor Q5 rises, and the magnitude relationship is reversed with respect to the base potential V4 of the transistor Q6. Because it can be increased, the stability can be improved.

FIG. 6 shows the characteristics of the input voltage-output current of the transconductor using the logarithmic conversion circuit of FIG. 4 (a). As described above, the polarity of the output does not reverse. In the logarithmic conversion circuit shown in FIG. 4A, the current sources I9 and I1 and the current sources I2 and I10 may be combined.

As shown in FIG. 7, the level shift means described for the logarithmic conversion circuit of FIG. 1A is applied to the logarithmic conversion circuit of FIG. The input signal voltage can be further increased.

As shown in FIG. 8, in the logarithmic conversion circuit shown in FIG. 4A, the position of the resistor R2 can be changed from between the collectors of the transistors Q5 and Q6 to between the emitters of the transistors Q1 and Q2. Good.

FIG. 9 shows each node voltage when the differential input signal voltage Vd is applied to the logarithmic conversion circuit shown in FIG.
FIG. 10 shows the differential input signal voltage-output current characteristics when the differential input signal voltage Vd is applied to the transconductor realized by the configuration shown in FIG.

Here, the operation of the logarithmic conversion circuit shown in FIG. 8 will be described. For the sake of simplicity, the relationship between the currents of the current sources shown in FIG. 8 is as follows. I1 = I2 = I3 = I4 = I9 = I10 = I
5/2 = I6 / 2 When the differential input signal voltage Vd is within the linear input voltage range, the current I3 in the transistors Q1 and Q2
And I4 are fed back from the collectors of the transistors Q1 and Q3 to the emitters of the transistors Q1 and Q3 via the transistors Q5 and Q6 and the diodes Q2 and Q4 operating as a level shift stage. As a result, the emitter potentials V5 and V6 of the transistors Q1 and Q3 become potentials which are level-shifted from the potentials of the input terminals IN + and IN- by Vbe.

That is, the differential input signal voltage Vd applied to IN + and IN- is applied to both ends of the resistor R1. At this time, the resistor R1
, A current of Vd / R1 flows, and the diode Q2 has I9 + V
A current of d / R1 flows, a current of I10-Vd / R1 flows in the diode Q4, a current of I1-Vd / R1 flows in the transistor Q5, and a current of I2 + Vd / R1 flows in the transistor Q6. Flows.

The base-emitter voltages of the transistors Q5 and Q6 are obtained by logarithmically converting the currents flowing therethrough and by current-voltage conversion, and output as voltages obtained by logarithmically converting the differential input signal voltage from the Out + and Out- terminals. Is done.

The linear input voltage range is a range in which the above operation is performed, and Vd where I1-Vd / R1 = 0, that is, I1 × R1 is a linear input voltage range. If the differential input signal voltage Vd tries to exceed the linear input voltage range, all the currents I1
2 and the current flows to the current source I6 via the resistor R1. At this time, the current
All of the current I4 flows to the current source I6 via the transistor Q3, and since I1 + I4 = I6, the current I10 does not flow through the diode Q4 but all flows to the transistor Q6.

Further, the transistor Q5 is turned off because no current flows, so that the feedback via the transistor Q5 is not applied, the transistor Q1 is saturated, and the collector potential V3 of the transistor Q1 drops to about 0.9V.

Further, when the differential input signal voltage Vd becomes larger than the linear input voltage range, the transistor Q5 responds accordingly.
Is increased as described in the conventional example.

As shown in FIG. 9, V5 rises, and the base current Ib of the transistor Q1 is supplied to the current source via the resistor R1.
Since the current flows through I6, the current supplied through the transistor Q3 changes from I4 to I4-Ib, and the current Ib corresponds to the transistor Q4.
6, the base potential is increased. When Vd increases and Ib = I4, all the current supplied from the current source I4 flows into the base of the transistor Q6, and the base potential V4 of the transistor Q6 can be increased by I4 × R2 as compared with the conventional case. The input signal voltage Vd becomes larger than the linear input voltage range, the base potential V3 of Q5 rises, and Q6
Since the magnitude relationship with the base potential V4 is reversed and the differential input signal voltage whose polarity is inverted can be made higher than in the conventional case, the stability can be improved.

FIG. 10 is a graph showing the characteristics of the input voltage and the output current of the transconductor using the logarithmic conversion circuit shown in FIG. 8, in which the polarity of the output does not reverse as described above.

In the logarithmic conversion circuit shown in FIG.
The current sources I9 and I1 and the current sources I2 and I10 may be integrated. As shown in FIG. 11, the level shift means described in the logarithmic conversion circuit of FIG. 1A is applied to the logarithmic conversion circuit of FIG. 8 to further increase the differential input signal voltage whose polarity is inverted. it can.

When integrating the above-described logarithmic conversion circuit of the present invention and a transconductor using an antilogarithmic conversion circuit using a differential pair as shown in FIG. 13, it is used in a logarithmic conversion circuit as shown in FIG. The current source generates a current in inverse proportion to the value of the integrated resistance element, and the current source used in the antilogarithmic conversion circuit is inversely proportional to the value of the resistance element Rext provided outside the integrated circuit. By generating a current, the variation in transconductance realized by the transconductor can be suppressed even if the resistance value of the integrated resistance element varies.

Hereinafter, the transconductor shown in FIG. 13 using the logarithmic conversion circuit of FIG. 1A will be described in detail.
The transconductance G is the ratio of the maximum current that can be output by the transconductor to the linear input voltage range that can be input, and is expressed by the following equation.

G = I20 / (2R1 * I1) The bias current including the current I1 of the logarithmic conversion circuit is represented by ln
The emitter area ratio of the transistors QB1 and QB2 is 1: 4 so that VT (= kT / q, where k is the Boltzmann constant, T is the absolute temperature, and q is the charge of the electron) of 4 times is integrated. The current obtained by the VT proportional current source having the configuration described above is expressed by transistors QB4 to QB14 and resistors RB2 to RB12.
The bias current including the current I20 of the antilogarithmic conversion circuit is duplicated and supplied by the current mirror circuit composed of
The current obtained by the VT proportional current source is configured such that the emitter area ratio of the transistors QB15 and QB16 is 1: 4 so that the VT of ln4 times is applied to the resistor Rext provided outside the integrated circuit. RB1
The transconductance G replicated and supplied by the current mirror circuit composed of 3 to RB19 is given by G = Rint / (R1 * Rext), and even if the integrated resistors (R1, Rinit) vary by α times, As shown in the equation, α is canceled. The resistance Rext provided outside the integrated circuit has an accuracy of 1 unit.
%, So transconductance hardly varies.

Also, since the linear input voltage range is the product of R1 and the current generated in inverse proportion to the value of the integrated resistance element, even if the integrated resistance is multiplied by α each time, the linear input voltage range The range is constant and does not vary.

As shown in FIG. 19, the current generating means shown in FIG. 18 applies a bias current such as the current I20 of the antilogarithmic function circuit to the transistor QB1 so as to apply a ln4 times VT to the integrated resistor Rint. A current obtained by a VT proportional current source having a configuration in which the emitter area ratio of QB2 is 1: 4 is applied to a current mirror circuit (QB16, QB17, Rint2, Rint2).
ext), one of the resistors is a resistor Rext provided outside the integrated circuit, as shown in the drawing, for example, Rint2 = Rint
Thus, the current flowing through the transistor QB17 may be realized as (ln4 * VT) / Rext.

As described above, the current source used in the antilogarithmic conversion circuit is integrated by generating a current in inverse proportion to the value of the resistance element Rext provided outside the integrated circuit. Even if the resistance element varies, the transconductance and the linear input voltage range can be prevented from varying.

[0051]

As described above, according to the logarithmic conversion circuit and the transconductor of the present invention, it is possible to provide a logarithmic conversion circuit and a transconductor that operate stably with a wide linear input range and a common mode input voltage.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a logarithmic conversion circuit according to a first embodiment of this invention.

FIG. 2 is an operation explanatory diagram of the logarithmic conversion circuit according to the first embodiment of the present invention.

FIG. 3 is a characteristic diagram of an input voltage-output current of a transconductor using the logarithmic conversion circuit according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of a logarithmic conversion circuit according to a second embodiment of this invention.

FIG. 5 is an operation explanatory diagram of a logarithmic conversion circuit according to a second embodiment of this invention.

FIG. 6 is a characteristic diagram of an input voltage-output current of a transconductor using a logarithmic conversion circuit according to a second embodiment of the present invention.

FIG. 7 is an explanatory diagram of a logarithmic conversion circuit according to a third embodiment of this invention.

FIG. 8 is an explanatory diagram of a logarithmic conversion circuit according to a fourth embodiment of this invention.

FIG. 9 is an operation explanatory diagram of a logarithmic conversion circuit according to a fourth embodiment of the present invention.

FIG. 10 is a characteristic diagram of input voltage-output current of a transconductor using a logarithmic conversion circuit according to a fourth embodiment of the present invention.

FIG. 11 is an explanatory diagram of a logarithmic conversion circuit according to a fifth embodiment of the present invention.

FIG. 12 is a configuration diagram of an active filter using the transconductor of the present invention.

FIG. 13 is a configuration diagram of the transconductor of the present invention.

FIG. 14 is a configuration diagram showing a conventional logarithmic conversion circuit.

FIG. 15 is an operation explanatory diagram showing an operation of a conventional logarithmic conversion circuit.

FIG. 16 shows an input of a transconductor using a conventional logarithmic conversion circuit; and an input voltage of a transconductor of the present invention.
-Output

FIG. 17 is an operation explanatory diagram showing an operation of a conventional logarithmic conversion circuit.

FIG. 18 is an explanatory view showing a transconductor of the present invention.

FIG. 19 is an explanatory view showing a transconductor of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Logarithmic conversion circuit 2 ... Antilogarithmic conversion circuit 11, 12 ... Amplification means 13, 14 ... Level shift means Q1-Q8 ... Transistor IN +, IN -... Input terminal Out +, Qut-: Output terminal of logarithmic variable circuit I1 to I10: Current source Vcc: First power supply potential point Vee: Second power supply potential point R1, R2: Resistance

Claims (9)

[Claims] A first and second amplifying means for amplifying an input signal; a first and a second level shifting means for level shifting output voltages of the first and second amplifying means; A first and a second transistor respectively having a base connected to an output terminal of the second level shifting means, an emitter coupled to each other, and a feedback fed from a collector to the first and second amplifying means, respectively; An impedance element disposed between collectors of the first and second transistors; and output means for extracting an output signal corresponding to a base-emitter voltage of the first and second transistors. Logarithmic conversion circuit. 2. First and second amplifying means having first and second input terminals respectively connected to a positive input terminal and having a feedback path from a positive output terminal to a negative input terminal; First and second amplifiers each having a base connected to a negative output terminal thereof, an emitter coupled to each other, and having a collector fed back to the negative input terminals of the first and second amplifier means. 2 transistors, an impedance element connected between the collectors of the first and second transistors, and output means for extracting an output signal according to the base-emitter voltage of the first and second transistors. A logarithmic conversion circuit. 3. First and second amplifying means having first and second input terminals connected to a positive input terminal, respectively, and having a feedback path from a positive output terminal to a negative input terminal; First and second level shift means for level-shifting the output voltage of the negative output of the second amplifying means; and bases connected to the output terminals of the first and second level shift means, respectively, and the emitters are connected to each other. First and second transistors coupled to each other and fed back from the collector to negative inputs of the first and second amplifying means; and an impedance connected between the collectors of the first and second transistors. A logarithmic conversion circuit comprising: an element; and an output unit for extracting an output signal according to a base-emitter voltage of the first and second transistors. 4. A first and second transistor having a base connected to the first and second input terminals, respectively, and a collector having a first and a second level connected to the emitters of the first and second transistors, respectively. Third and fourth transistors connected via shift means and having their emitters coupled to each other; an impedance element connected between collectors of the third and fourth transistors; and the first and second transistors Of the said third
And an output means connected to the fourth base for extracting an output signal corresponding to the base-emitter voltage of the third and fourth transistors. 5. A first and second transistor having a base connected to the first and second input terminals, respectively, and a collector having first and second levels respectively connected to the emitters of the first and second transistors. Third and fourth transistors connected via shift means and having emitters coupled to each other; an impedance element connected between collectors of the third and fourth transistors; and the first and second transistors. Output means connected to the third and fourth bases via third and fourth level shift means from the collector of the first and second transistors to extract an output signal corresponding to the base-emitter voltage of the third and fourth transistors. And a logarithmic conversion circuit. 6. A first and a second transistor having a base connected to the first and second input terminals, respectively, and a collector having a first and a second level connected to the emitters of the first and second transistors, respectively. Third and fourth transistors connected via shift means and having emitters coupled to each other; an impedance element connected between the emitters of the first and second transistors; and the first and second transistors. Of the said third
And the third transistor is connected to the base of the fourth transistor.
An output means for extracting an output signal corresponding to a base-emitter voltage of the fourth transistor. 7. A first and second transistor having a base connected to first and second input terminals, respectively, and a collector having a first and a second level connected to the emitters of the first and second transistors, respectively. Third and fourth transistors connected via shift means and having emitters coupled to each other; an impedance element connected between the emitters of the first and second transistors; and the first and second transistors. Output means connected to the third and fourth bases via third and fourth level shift means from the collector of the first and second transistors to extract an output signal corresponding to the base-emitter voltage of the third and fourth transistors. And a logarithmic conversion circuit. 8. In a transconductor constituted by a logarithmic conversion circuit and an antilogarithmic conversion circuit formed by a differential pair, the logarithmic conversion circuit is characterized in that the logarithmic conversion circuit is defined by claim 1 or claim 2 or claim 3 or claim 4 or A transconductor comprising the logarithmic conversion circuit according to claim 5. 9. A transconductor formed on an integrated circuit, wherein the transconductor is formed on an integrated circuit.
Wherein the impedance element of the logarithmic conversion circuit is an integrated resistance element, and the logarithmic conversion circuit includes first bias current generation means using the integrated resistance element. The antilogarithmic conversion circuit includes a second bias current generation unit using a resistance element provided outside the integrated circuit.