CN113030554A - Zero current detection circuit and detection method thereof - Google Patents
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Abstract
The invention provides a zero current detection circuit and a method thereof, the circuit comprises a mutual inductor, a first detection module, a second detection module and a signal processing module, wherein the mutual inductor is used for sensing an inductive current zero-crossing signal of a bridgeless power factor correction circuit and reducing sampling loss according to the saturation characteristic of the inductive current zero-crossing signal, the first detection module is used for generating a zero current detection voltage signal required by a negative half period, the second detection module is used for generating a zero current detection voltage signal required by a positive half period, and the signal processing module is used for combining and generating the zero current detection signal required by the circuit in the whole power frequency period. The invention aims to reduce the sampling loss by utilizing the saturation characteristic of the mutual inductor, thereby improving the system efficiency.
Description
Technical Field
The invention relates to the field of active power factor correction converters, in particular to zero current detection.
Background
With the rapid development of modern industry, the nonlinear load of the power system is increasing. Harmonic currents generated by these nonlinear loads are injected into the grid, which distorts the voltage waveform of the utility grid and severely pollutes the grid environment. In order to reduce the serious harmonic pollution caused by frequent use of Power electronic devices to the Power grid, a Power Factor Correction (PFC) circuit is usually required to be introduced to make the input current harmonic meet a preset harmonic requirement. In addition, the trend of PFC circuits is also moving towards High efficiency (High efficiency) and High power density (High power density) as most power supply products.
Compared with the traditional bridge PFC circuit, the bridgeless PFC circuit reduces the loss of an input end rectifier bridge stack. Therefore, the circuit has the advantages of low on-state loss, low common-mode interference, high utilization rate of components and the like. Meanwhile, the bridgeless PFC can realize Zero Voltage Switching (ZVS) under specific control, so the bridgeless PFC is increasingly paid attention by research.
Taking a totem pole bridgeless PFC circuit as an example, fig. 1 shows a totem pole bridgeless PFC circuit. Because the body diode of the Si MOS tube has longer reverse recovery time, the body diode can cause great reverse recovery loss in a Continuous Current Mode (CCM), and the totem of the Si MOS tube is not suitable for working in the CCM mode without a bridge. Body diodes of the Si MOS tubes are turned off at zero current in a critical current mode (CRM) and a DCM (discontinuous mode), almost no reverse recovery loss exists, and the realization of high efficiency of totem bridgeless PFC is facilitated. Therefore, how to simply and effectively detect the zero crossing point of the inductive current in the CRM mode is a problem that designers need to solve urgently.
The bridgeless circuit can adopt series resistors to detect current, as shown in fig. 2, the scheme is that a sampling resistor is connected between an alternating current power supply and a first energy storage circuit or between the first energy storage circuit and a half-bridge switching circuit or between the alternating current power supply and a rectification circuit, but the sampling loss of the scheme is large, a sampling ground is not in common with a power ground, isolation driving is needed, differential sampling of output voltage is achieved, and a control circuit is complex. In addition, the bridgeless circuit can perform zero current detection by using the winding and adopt edge detection, as shown in fig. 3, the scheme can only work in a diode rectification mode, extra sampling loss is increased, and the bridgeless circuit is not convenient to expand into other bridgeless PFC circuits.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides the zero current detection circuit of the bridgeless power factor correction circuit and the method thereof, which not only can be conveniently expanded to other PFC circuit applications such as a staggered PFC circuit and the like, but also can reduce the sampling loss of the bridgeless power factor correction circuit by utilizing the saturation characteristic of a mutual inductor, and is beneficial to improving the working efficiency of a system.
The invention provides a zero current detection circuit, which is used for a bridgeless power factor correction circuit and comprises a mutual inductor, a first detection module, a second detection module and a signal processing module; the mutual inductor is used for being connected with one end of a main power inductor of the bridgeless power factor correction circuit, the first detection module and the second detection module are respectively connected with two ends of a secondary side of the mutual inductor, the first input end of the signal processing module is connected with the output end of the first detection module, and the second input end of the signal processing module is connected with the output end of the second detection module; the mutual inductor is used for sensing an inductive current zero-crossing signal of the bridgeless power factor correction circuit and reducing sampling loss according to the saturation characteristic of the inductive current zero-crossing signal, the first detection module is used for generating a zero-current detection voltage signal required by a negative half period, the second detection module is used for generating a zero-current detection voltage signal required by a positive half period, and the signal processing module is used for combining and generating the zero-current detection signal required by the circuit in the whole power frequency period.
The transformer comprises a primary side inductance unit and a secondary side inductance unit, wherein a first end of the primary side inductance unit is connected with one end of an input voltage source, and a second end of the primary side inductance unit is connected with one end of a main power inductance of a bridgeless power factor correction circuit; the secondary side inductance unit comprises a first inductance and a second inductance, wherein the first end of the first inductance is connected with one end of the first detection module, the second end of the first inductance is connected with the reference ground of the control circuit and the first end of the second inductance, and the second end of the second inductance is connected with one end of the second detection module.
The specific implementation mode of the first detection module comprises a resistor R1, a diode D1 and a resistor R2, wherein one end of the resistor R1 is connected with a mutual inductor, the other end of the resistor R1 is connected with the cathode of the diode D1 and one end of the resistor R2, the connection point is the output end of the first detection module, the anode of the diode D1 is connected with the other end of the resistor R2, and the connection point is connected with the control circuit and the ground.
The second detection module comprises a resistor R3, a diode D2 and a resistor R4, wherein one end of the resistor R3 is connected with the mutual inductor, the other end of the resistor R3 is connected with the cathode of the diode D2 and one end of the resistor R4, the connection point of the resistor R3 is used as the output end of the second detection module, the anode of the diode D2 is connected with the other end of the resistor R4, and the connection point of the diode D2 is connected with the control circuit reference ground.
The signal processing module comprises an OR logic gate circuit and a delay circuit, wherein a first input end of the OR logic gate circuit is connected with an output end of the first detection module, a second input end of the OR logic gate circuit is connected with an output end of the second detection module, an output end of the OR logic gate circuit is connected with an input end of the delay circuit, and an output end of the delay circuit is used for outputting a zero current detection signal of the bridgeless power factor correction circuit.
As another specific embodiment of the signal processing module, the signal processing module comprises a comparator combination circuit, a delay circuit, a signal blanking circuit and a signal output circuit; the comparator combination circuit is used for generating square wave signals and comprises a comparator U1, a comparator U2 and an OR logic gate circuit, wherein a first input end of the comparator U1 is connected with an output end of the first detection module, a second input end of the comparator U1 is connected with a reference voltage Vref, and an output end of the comparator U1 is connected with a first input end of the OR logic gate circuit; a first input end of the comparator U2 is connected with an output end of the second detection module, a second input end of the comparator U2 is connected with the reference voltage Vref, an output end of the comparator U2 is connected with a second input end of the OR logic gate circuit, and an output end of the OR logic gate circuit is connected with an input end of the delay circuit; the blanking circuit is used for shielding the zero current detection false triggering signal, the input end of the signal blanking circuit is connected with the output end of the delay circuit, and the output end of the signal blanking circuit is connected with the input end of the signal output circuit; the output end of the signal output circuit is used for outputting a zero current detection signal of the bridgeless power factor correction circuit.
Preferably, the signal blanking circuit comprises a monostable flip-flop.
Preferably, the signal output circuit comprises an and logic gate circuit.
The invention also provides a zero current detection method for the bridgeless power factor correction circuit, which comprises the following steps:
detecting current zero-crossing, namely detecting an inductive current zero-crossing signal of the bridgeless power factor correction circuit through a transformer, and enabling the voltage of a part of the inductive current zero-crossing signal directly connected to the bridgeless power factor correction circuit to be zero by utilizing the saturation characteristic of the transformer, so that the sampling loss is reduced;
a zero current detection voltage signal generation step, wherein a detection module generates zero current detection voltage signals of positive and negative half periods;
and a zero current detection voltage signal output step, namely outputting a zero current detection signal required by the whole power frequency period.
One specific process of the step of outputting the zero-current detection voltage signal is that the zero-current detection signals of the positive half period and the negative half period are combined and then output through a delay circuit.
The other specific process as the step of outputting the zero-current detection voltage signal is that the zero-current detection signals of the positive half period and the negative half period are combined and then pass through a delay circuit, then the signal blanking is carried out, the false triggering signal of the zero-current detection is shielded, and then the signal is output.
Compared with the prior art, the invention has the following beneficial effects:
1. reliable sampling of ZCD (zero current detection) can be realized, negative current is reduced, sampling loss is reduced, and system efficiency is improved;
2. the circuit is convenient to expand to other PFC circuit applications.
Drawings
Fig. 1 is a circuit diagram of a totem-pole bridgeless PFC;
FIG. 2 is a circuit diagram of a prior art zero current detection scheme;
FIG. 3 is a circuit diagram of a prior art zero current detection scheme;
FIG. 4 is a schematic circuit diagram of a first embodiment of the present invention;
FIG. 5 is a timing diagram illustrating the operation of the zero current detection circuit according to the first embodiment of the present invention;
fig. 6 is a schematic diagram of the conduction of the main pipe in the positive half period of the PFC circuit according to the first embodiment of the present invention;
fig. 7 is a schematic diagram of the conduction of the auxiliary tube in the positive half cycle of the PFC circuit according to the first embodiment of the present invention;
FIG. 8 is a circuit diagram illustrating a second embodiment of the present invention;
FIG. 9 is a timing diagram illustrating the operation of the zero current detection circuit according to the second embodiment of the present invention;
Detailed Description
First embodiment
Fig. 4 is a circuit diagram according to a first embodiment of the present invention.
A zero current detection circuit of a bridgeless power factor correction circuit comprises a mutual inductor 201, a first detection module 202, a second detection module 203 and a signal processing module 204.
The transformer 201 is used for sensing an inductive current zero-crossing signal of the bridgeless power factor correction circuit, and the transformer saturation characteristic is utilized to reduce the zero current detection sampling loss and improve the system efficiency. The transformer 201 comprises a primary side inductance unit and a secondary side inductance unit, the primary side inductance unit comprises an inductance L1, the dotted terminal of an inductance L1 is connected with one end of an input voltage source, and the unlike terminal of an inductance L1 is connected with one end of a main power inductance L of a bridgeless power factor correction circuit; the secondary side inductance unit comprises an inductance L2 and an inductance L3, the dotted terminal of the inductance L2 is connected with one end of the first detection module 202, the dotted terminal of the inductance L3 is connected with one end of the second detection module 203, and the dotted terminal of the inductance L2 and the dotted terminal of the inductance L3 are connected with the control circuit ground GND.
The first detecting module 202 is configured to generate a zero current detection voltage signal required by a negative half cycle, and includes a resistor R1, a diode D1, and a resistor R2, one end of the resistor R1 is connected to a dotted terminal of an inductor L2, the other end of the resistor R1 is connected to a cathode of a diode D1 and one end of a resistor R2, a connection point of the resistor R2 and the cathode of the diode D1 is an output terminal of the first detecting module 202, and an anode of the diode D1 and the other end of the resistor R2 are connected to a ground GND of the control circuit. The voltage at the output terminal of the first detection module 202 is determined by the voltage at the two terminals of the primary side inductance unit of the transformer, the turn ratio and the resistance,
wherein V1 is the voltage at the output end of the first detection module 202, Vs1 is the voltage at two ends of the inductor L2 of the secondary side inductor unit of the transformer, R1 is the resistance of a resistor R1, R2 is the resistance of a resistor R2, Vp is the voltage at two ends of the primary side inductor unit of the transformer, and N is the turn ratio of the transformer.
The second detection module 203 is used for generating a zero current detection voltage signal required by the positive half cycle, and comprises a resistor R3, a diode D2 and a resistor R4, wherein one end of the resistor R3 is connected with the synonym end of the inductor L3, the other end of the resistor R3 is connected with the cathode of the diode D2 and one end of the resistor R4, and the connection point is the firstThe output terminals of the two detection modules 203, the anode of the diode D2 and the other end of the resistor R4 are connected to the control circuit ground GND. The voltage at the output end of the second detection module 203 is determined by the voltage at the two ends of the primary side inductance unit of the transformer, the turn ratio and the resistance,
wherein V2 is the voltage at the output terminal of the second detection module 203, Vs2 is the voltage at both ends of the inductor L2 of the secondary side inductor unit of the transformer, R3 is the resistance of a resistor R3, R4 is the resistance of a resistor R4, Vp is the voltage at both ends of the primary side inductor unit of the transformer, and N is the turn ratio of the transformer.
The signal processing module 204 comprises an OR logic gate OR1 and a delay circuit, wherein a first input end of the OR logic gate OR1 is connected with an output end of the first detection module 202, a second input end thereof is connected with an output end of the second detection module 203, and an output end thereof is connected with an input end of the delay circuit, the delay circuit is used for setting trigger delay time, so that when the inductive current is reduced to 0 OR close to 0, the output end generates a zero current detection signal ZCD of the bridgeless power factor correction circuit, and zero voltage switching on of the switching tube is realized.
Taking the positive half cycle of the sinusoidal alternating voltage as an example (taking the L-line voltage higher than the N-line voltage as the positive half cycle), the detailed working principle of the zero-current detection circuit of the bridgeless power factor correction circuit is as follows:
the specific timing sequence is shown in FIG. 5, wherein ILIs an inductive current, VABThe voltage between the same end of a primary side inductance unit of the transformer and the other end of a main power inductance L of a bridgeless power factor correction circuit is subjected to, Vp is the voltage between the two ends of the primary side inductance unit of the transformer, Vs1 is the voltage between the two ends of an inductance L2 of a secondary side inductance unit of the transformer, Vs2 is the voltage between the two ends of an inductance L2 of the secondary side inductance unit of the transformer, and Vs1 and Vs2 are subjected to resistance voltage division to respectively obtain V1 and V2;
at time t0, the main power MOS transistor Q2 of the PFC circuit is in a conducting state, as shown in the loop of FIG. 6, the main power inductor L is excited, and the inductor current I isLAnd (4) rising. When the current through the inductor L1 rises to the forward saturation current threshold Isat (the saturation threshold is set small, close to 0), the inductor L1 coil saturates,at this time, the inductor L1 is close to a short circuit state, and the voltage Vp across the inductor L1 drops to 0, i.e., V1 and V2 are both 0;
at the time t0-t1, the main power MOS transistor Q2 of the PFC circuit is still in a conducting state, and the inductive current ILContinues to increase, the inductive current ILThe current is still larger than the forward saturation current threshold Isat, the mutual inductor is in a saturation state, Vp is 0, and the circuit almost has no sampling loss at the moment;
at time t1-t2, the main power MOS transistor Q2 is turned off, the PFC circuit power MOS transistor Q1 is turned on, and as shown in the loop of FIG. 7, the main power inductor L is demagnetized, and the inductor current I is increasedLDecrease due to the inductor current ILThe current is still larger than a forward saturation current threshold Isat, so that the mutual inductor is still in a saturation state, Vp is 0, and the circuit almost has no sampling loss;
at the time t2-t3, the main power MOS transistor Q2 is in an off state, the power MOS transistor Q1 is in an on state, and at the time t2, when the current flowing through the inductor L1 drops to a value below a forward saturation current threshold Isat, the transformer desaturates, and the voltage Vp across the coil of the inductor L1 bears negative voltage, so that the voltages across the coil of the inductor L2 and the coil of the inductor L3 simultaneously satisfy the following relations:
therefore, both Vs1 and Vs2 are negative voltages, and due to the ground GND, the diode D1 is turned on by the forward voltage at this time, and the output terminal voltage V1 is clamped by the diode D1 to be a negative voltage close to zero, whereas the diode D2 is turned off by the reverse voltage at this time, and the output terminal voltage V2 is a positive voltage;
inductive current ILAfter the current is decreased to zero and increased reversely until the time t3, the inductive current ILWhen the negative saturation current threshold value-Isat is reached, the mutual inductor is saturated again, and at the same time, the inductor L1 is close to a short circuit state, and the voltage Vp at the two ends of the inductor is reduced to 0;
at the time t3-t4, the main power MOS tube Q2 is in a turn-off state, the power MOS tube Q1 is in a turn-on state, at the time, the negative inductor current is still larger than a negative saturation current threshold value-Isat, the mutual inductor is in a saturation state, Vp is 0, and at the time, the circuit almost has no sampling loss;
at the time t4-t5, the main power MOS transistor Q2 is turned on again, the power MOS transistor Q1 is turned off, and the negative inductor current is reduced. But the negative inductance current at the stage is still larger than a negative saturation current threshold value-Isat, the mutual inductor is in a saturation state, Vp is 0, and the circuit almost has no sampling loss;
at the time t5, the main power MOS transistor Q2 is in a conducting state, when the negative current flowing through the coil of the inductor L1 of the transformer falls to a negative saturation current threshold value — Isat, the inductor L1 of the transformer is desaturated, and the voltage Vp at the two ends of the inductor L1 is subjected to positive voltage, so that both Vs1 and Vs2 are positive voltage, because of the ground GND reference, the diode D1 is subjected to reverse voltage and is cut off at the time, the voltage V1 at the output end is positive voltage, on the contrary, the diode D2 is subjected to positive voltage conduction at the time, and the voltage V2 at the output end is clamped by the diode D2 to be negative voltage;
when the current flowing through the coil of the primary inductor L1 of the transformer rises to the forward saturation current threshold Isat again until the time t6, the transformer is saturated again;
similarly, the detailed working principle of the negative half period is not repeated herein.
Comparing the prior art with the present invention, the zero current detection circuit aims to utilize the saturation characteristic of the transformer. When the current flowing through the primary side inductance unit of the transformer reaches the saturation current threshold value, the transformer is saturated, the voltage Vp at two ends of the primary side coil of the transformer is almost 0 (close to a short-circuit state), the sampling circuit has almost no loss, the purpose of reducing the sampling loss is achieved, and therefore the system efficiency is improved.
Second embodiment
Fig. 8 shows a second embodiment of the present invention, which is different from the first embodiment in that the signal processing module 204 includes a comparator combination circuit including an OR logic gate OR2, a comparator U1, and a comparator U2, a first input terminal of the comparator U1 is connected to the output terminal of the first detection module 202, a second input terminal of the comparator U1 is connected to a reference value Vref, an output terminal of the comparator U1 is connected to a first input terminal of the OR logic gate OR2, a first input terminal of the comparator U2 is connected to the output terminal of the second detection module 203, a second input terminal of the comparator U2 is connected to the reference value Vref, an output terminal of the comparator U2 is connected to a second input terminal of the OR gate OR2, OR an output terminal of the logic gate OR2 is connected to an input terminal of the delay circuit, the signal blanking circuit, and the signal output circuit are connected in series in this order, the output end of the signal output circuit outputs a zero current detection signal ZCD of the bridgeless power factor correction circuit to realize zero voltage switching-on of the switching tube.
The zero current detection circuit is used for improving the reliability of the zero current detection circuit and preventing false triggering signals from influencing the normal operation of a system.
The timing diagram for the positive half cycle operation of the second embodiment of the present invention is shown in FIG. 9, where ILIs the main power inductor current, VQ2For positive half-cycle main drive voltage signal, VZCD1For the voltage signal, V, output by the comparator combined circuit after passing through the delay circuitZCD2For processing a signal within the signal blanking circuit, VZCDIs the voltage signal output by the signal blanking circuit.
The operation principle of the comparator combination circuit is that when the voltage V1 at the output end of the first detection module 202 or the voltage V2 at the output end of the second detection module 203 is greater than Vref, the output end of the comparator U1 or U2 outputs a high level, otherwise, a low level square wave signal is output. The reference value Vref should be set reasonably and should not be too large, because when at the high input voltage peak, the voltage difference between the output voltage and the input voltage (Vo-Vin) is small, and the situation that the secondary side voltage (V1 or V2) of the transformer does not reach the reference value Vref of the comparator may occur, so that the ZCD signal cannot be detected by the circuit, and the inductor current is abnormal, thereby affecting the THD value of the system.
The signal blanking circuit is used for shielding the voltage signal V output by the comparator combined circuit after passing through the delay circuitZCD1The signal blanking function can be realized by adopting a monostable trigger.
As can be seen from FIG. 9, at the peak of the inductor current, VZCD1False trigger signal occurs because V is at this momentZCD2Is a low level signal, so the false trigger signal is blanked and then output VZCD. Therefore, the present embodiment canReliable sampling of the zero current detection signal is achieved.
The above disclosure is only a preferred embodiment of the present invention, but the present invention is not limited thereto, and those skilled in the art should make modifications to the present invention without departing from the core idea of the present invention, and fall within the protection scope of the claims of the present invention.
Claims (10)
1. A zero current detection circuit is used for a bridgeless power factor correction circuit, and is characterized in that: the system comprises a mutual inductor, a first detection module, a second detection module and a signal processing module; the mutual inductor is used for being connected with one end of a main power inductor of the bridgeless power factor correction circuit, the first detection module and the second detection module are respectively connected with two ends of a secondary side of the mutual inductor, the first input end of the signal processing module is connected with the output end of the first detection module, and the second input end of the signal processing module is connected with the output end of the second detection module; the mutual inductor is used for sensing an inductive current zero-crossing signal of the bridgeless power factor correction circuit and reducing sampling loss according to the saturation characteristic of the inductive current zero-crossing signal, the first detection module is used for generating a zero-current detection voltage signal required by a negative half period, the second detection module is used for generating a zero-current detection voltage signal required by a positive half period, and the signal processing module is used for combining and generating the zero-current detection signal required by the circuit in the whole power frequency period.
2. The zero-current detection circuit according to claim 1, wherein: the transformer comprises a primary side inductance unit and a secondary side inductance unit, wherein a first end of the primary side inductance unit is connected with one end of an input voltage source, and a second end of the primary side inductance unit is connected with one end of a main power inductance of the bridgeless power factor correction circuit; the secondary side inductance unit comprises a first inductance and a second inductance, wherein the first end of the first inductance is connected with one end of the first detection module, the second end of the first inductance is connected with the reference ground of the control circuit and the first end of the second inductance, and the second end of the second inductance is connected with one end of the second detection module.
3. The zero-current detection circuit according to claim 1, wherein: the first detection module comprises a resistor R1, a diode D1 and a resistor R2, one end of the resistor R1 is connected with the mutual inductor, the other end of the resistor R1 is connected with the cathode of the diode D1 and one end of the resistor R2, the connection point of the resistor R1 is the output end of the first detection module, the anode of the diode D1 is connected with the other end of the resistor R2, and the connection point of the diode D1 is connected with the reference ground of the control circuit.
4. The zero-current detection circuit according to claim 1, wherein: the second detection module comprises a resistor R3, a diode D2 and a resistor R4, one end of the resistor R3 is connected with the mutual inductor, the other end of the resistor R3 is connected with the cathode of the diode D2 and one end of the resistor R4, the connection point of the resistor R3 is used as the output end of the second detection module, the anode of the diode D2 is connected with the other end of the resistor R4, and the connection point of the diode D2 is connected with the reference ground of the control circuit.
5. The zero-current detection circuit according to claim 1, wherein: the signal processing module comprises an OR logic gate circuit and a delay circuit, wherein a first input end of the OR logic gate circuit is connected with an output end of the first detection module, a second input end of the OR logic gate circuit is connected with an output end of the second detection module, an output end of the OR logic gate circuit is connected with an input end of the delay circuit, and an output end of the delay circuit is used for outputting a zero current detection signal of the bridgeless power factor correction circuit.
6. The zero-current detection circuit according to claim 1, wherein: the signal processing module comprises a comparator combined circuit, a delay circuit, a signal blanking circuit and a signal output circuit; the comparator combination circuit is used for generating square wave signals and comprises a comparator U1, a comparator U2 and an OR logic gate circuit, wherein a first input end of the comparator U1 is connected with an output end of the first detection module, a second input end of the comparator U1 is connected with a reference voltage Vref, and an output end of the comparator U1 is connected with a first input end of the OR logic gate circuit; a first input end of the comparator U2 is connected with an output end of the second detection module, a second input end of the comparator U2 is connected with the reference voltage Vref, an output end of the comparator U2 is connected with a second input end of the OR logic gate circuit, and an output end of the OR logic gate circuit is connected with an input end of the delay circuit; the blanking circuit is used for shielding the zero current detection false triggering signal, the input end of the signal blanking circuit is connected with the output end of the delay circuit, and the output end of the signal blanking circuit is connected with the input end of the signal output circuit; the output end of the signal output circuit is used for outputting a zero current detection signal of the bridgeless power factor correction circuit.
7. The zero-current detection circuit according to claim 6, wherein: the signal blanking circuit includes a monostable flip-flop.
8. The zero-current detection circuit according to claim 6, wherein: the signal output circuit comprises an AND logic gate circuit.
9. A zero current detection method is used for a bridgeless power factor correction circuit, and is characterized by comprising the following steps:
detecting current zero-crossing, namely detecting an inductive current zero-crossing signal of the bridgeless power factor correction circuit through a transformer, and enabling the voltage of a part of the inductive current zero-crossing signal directly connected to the bridgeless power factor correction circuit to be zero by utilizing the saturation characteristic of the transformer, so that the sampling loss is reduced;
a zero current detection voltage signal generation step, wherein a detection module generates zero current detection voltage signals of positive and negative half periods;
and a zero current detection voltage signal output step, namely outputting a zero current detection signal required by the whole power frequency period.
10. The zero-current detection circuit according to claim 8, wherein the zero-current detection voltage signal output step comprises the specific processes of:
the zero current detection signals of the positive half period and the negative half period are combined and then output through a delay circuit;
or the zero current detection signals of the positive half period and the negative half period are combined and then pass through the delay circuit, then the signals are blanked, the false triggering signals of the zero current detection are shielded, and then the signals are output.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113252972A (en) * | 2021-07-02 | 2021-08-13 | 深圳市高斯宝电气技术有限公司 | Bridgeless PFC inductive current zero-crossing detection circuit |
| WO2023056613A1 (en) * | 2021-10-08 | 2023-04-13 | Abb Schweiz Ag | Bidirectional bridgeless pfc circuit |
| CN117129748A (en) * | 2023-10-27 | 2023-11-28 | 茂睿芯（深圳）科技有限公司 | Zero crossing monitoring circuit and method based on CRM boost PFC converter |
| CN117254674A (en) * | 2023-11-20 | 2023-12-19 | 珠海镓未来科技有限公司 | PFC drive control module and power factor correction device |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101485073A (en) * | 2006-06-30 | 2009-07-15 | 美国快捷半导体有限公司 | High-efficiency power coN. V.erter system |
| CN101860189A (en) * | 2009-04-13 | 2010-10-13 | 台达电子工业股份有限公司 | Bridgeless power factor correcting circuit for critical continuous current mode and method thereof |
| CN203967733U (en) * | 2014-07-01 | 2014-11-26 | 广东美芝制冷设备有限公司 | Without current sample and the overcurrent protective device of bridge APFC system |
| CN104518656A (en) * | 2013-10-08 | 2015-04-15 | 中兴通讯股份有限公司 | Totem-pole bridgeless power factor correction soft switching control device and method |
| CN105004910A (en) * | 2014-04-22 | 2015-10-28 | 中兴通讯股份有限公司 | Current detection method and apparatus of PFC inductor |
| CN106253658A (en) * | 2016-08-26 | 2016-12-21 | 宁波赛耐比光电科技股份有限公司 | A kind of circuit of power factor correction |
| CN109428476A (en) * | 2017-08-30 | 2019-03-05 | 中兴通讯股份有限公司 | A kind of analog control device of circuit of power factor correction |
| CN110504828A (en) * | 2018-05-17 | 2019-11-26 | 台达电子工业股份有限公司 | Control circuit and control method |
| US20200014296A1 (en) * | 2018-05-17 | 2020-01-09 | Delta Electronics (Shanghai) Co., Ltd. | Control circuit and control method for outputting pulse width modulation control signal with zero-crossing detection |
| CN210142979U (en) * | 2019-08-29 | 2020-03-13 | 台达电子企业管理（上海）有限公司 | Control circuit |
| CN111327186A (en) * | 2020-03-23 | 2020-06-23 | 上海空间电源研究所 | Inductive current zero-crossing detection method of bridgeless power factor correction circuit |
| CN112003454A (en) * | 2019-05-27 | 2020-11-27 | 恩智浦美国有限公司 | Bridgeless power factor correction converter with zero current detection circuit |
| US10917006B1 (en) * | 2019-11-01 | 2021-02-09 | Apple Inc. | Active burst ZVS boost PFC converter |
-
2021
- 2021-03-18 CN CN202110292305.4A patent/CN113030554A/en active Pending
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101485073A (en) * | 2006-06-30 | 2009-07-15 | 美国快捷半导体有限公司 | High-efficiency power coN. V.erter system |
| CN101860189A (en) * | 2009-04-13 | 2010-10-13 | 台达电子工业股份有限公司 | Bridgeless power factor correcting circuit for critical continuous current mode and method thereof |
| CN104518656A (en) * | 2013-10-08 | 2015-04-15 | 中兴通讯股份有限公司 | Totem-pole bridgeless power factor correction soft switching control device and method |
| CN105004910A (en) * | 2014-04-22 | 2015-10-28 | 中兴通讯股份有限公司 | Current detection method and apparatus of PFC inductor |
| CN203967733U (en) * | 2014-07-01 | 2014-11-26 | 广东美芝制冷设备有限公司 | Without current sample and the overcurrent protective device of bridge APFC system |
| CN106253658A (en) * | 2016-08-26 | 2016-12-21 | 宁波赛耐比光电科技股份有限公司 | A kind of circuit of power factor correction |
| CN109428476A (en) * | 2017-08-30 | 2019-03-05 | 中兴通讯股份有限公司 | A kind of analog control device of circuit of power factor correction |
| CN110504828A (en) * | 2018-05-17 | 2019-11-26 | 台达电子工业股份有限公司 | Control circuit and control method |
| US20200014296A1 (en) * | 2018-05-17 | 2020-01-09 | Delta Electronics (Shanghai) Co., Ltd. | Control circuit and control method for outputting pulse width modulation control signal with zero-crossing detection |
| CN112003454A (en) * | 2019-05-27 | 2020-11-27 | 恩智浦美国有限公司 | Bridgeless power factor correction converter with zero current detection circuit |
| CN210142979U (en) * | 2019-08-29 | 2020-03-13 | 台达电子企业管理（上海）有限公司 | Control circuit |
| US10917006B1 (en) * | 2019-11-01 | 2021-02-09 | Apple Inc. | Active burst ZVS boost PFC converter |
| CN111327186A (en) * | 2020-03-23 | 2020-06-23 | 上海空间电源研究所 | Inductive current zero-crossing detection method of bridgeless power factor correction circuit |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113252972A (en) * | 2021-07-02 | 2021-08-13 | 深圳市高斯宝电气技术有限公司 | Bridgeless PFC inductive current zero-crossing detection circuit |
| WO2023056613A1 (en) * | 2021-10-08 | 2023-04-13 | Abb Schweiz Ag | Bidirectional bridgeless pfc circuit |
| CN117129748A (en) * | 2023-10-27 | 2023-11-28 | 茂睿芯（深圳）科技有限公司 | Zero crossing monitoring circuit and method based on CRM boost PFC converter |
| CN117129748B (en) * | 2023-10-27 | 2024-03-01 | 茂睿芯（深圳）科技有限公司 | Zero crossing monitoring circuit and method based on CRM boost PFC converter |
| CN117254674A (en) * | 2023-11-20 | 2023-12-19 | 珠海镓未来科技有限公司 | PFC drive control module and power factor correction device |
| CN117254674B (en) * | 2023-11-20 | 2024-02-09 | 珠海镓未来科技有限公司 | PFC drive control module and power factor correction device |
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