CN203491883U - Isolated switch converter and controller thereof - Google Patents
Isolated switch converter and controller thereof Download PDFInfo
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- CN203491883U CN203491883U CN201320629780.7U CN201320629780U CN203491883U CN 203491883 U CN203491883 U CN 203491883U CN 201320629780 U CN201320629780 U CN 201320629780U CN 203491883 U CN203491883 U CN 203491883U
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Abstract
The utility model discloses an isolated switch converter and controller thereof. The isolated switch converter comprises a primary switch tube, a secondary switch tube, a transformer, an error amplification circuit, a first comparison circuit, a primary turn-off detection circuit, an isolation circuit, a primary logic circuit and a secondary logic circuit. The error amplification circuit generates a compensation signal based on a difference between the feedback signal and the reference signal. The first comparison circuit compares the compensation signal with the modulation signal to generate a first comparison signal. The primary turn-off detection circuit detects whether the primary switching tube is turned off or not and generates a primary turn-off detection signal. The secondary logic circuit generates a secondary control signal to control the secondary switch tube based on the primary turn-off detection signal and the first comparison signal. The isolation circuit generates a synchronization signal electrically isolated from the first comparison signal based on the first comparison signal. The primary logic circuit generates a primary control signal to control the primary switch tube based on the synchronous signal.
Description
Technical field
The utility model relates to electronic circuit, relates in particular to isolated switch converters and controller thereof.
Background technology
Synchronous rectification is to adopt power metal oxide semiconductor field-effect transistor (MOSFET) to replace the technology of rectifier diode to reduce the wastage, and it can improve the efficiency of Switching Power Supply greatly.Power MOSFET belongs to voltage-controlled device, and its voltage-current characteristic when conducting is linear.While making rectifier with power MOSFET, require its grid voltage to synchronize with the phase preserving that is rectified voltage.
Fig. 1 is the oscillogram of existing intelligent synchronization commutation technique, and wherein Vds is the drain-source voltage of secondary switch pipe, and Isec is the electric current that flows through secondary winding, and CTRLS is the control signal of secondary switch pipe.Vds is used as respectively and two threshold voltages, for example-70mV and-500mV compares.When the body diode conducting of secondary switch pipe, while making be less than-500mV of Vds, secondary switch pipe is switched on; When elementary switching tube conducting, while making be greater than-70mV of Vds, secondary switch pipe is turned off.
Existing intelligent synchronization commutation technique is after the conducting of primary switch pipe, secondary switch pipe turn-offs in side, easily cause primary switch pipe and secondary switch pipe conducting simultaneously (straight-through, shoot through), the efficiency that reduces Switching Power Supply even causes Switching Power Supply to damage.And in side circuit, the time delay due to self-characteristic and the control circuit of MOSFET, increases to be greater than-70mV and be turned off and need a period of time to secondary switch pipe from Vds, this has further increased straight-through possibility undoubtedly.
Utility model content
For problems of the prior art, the purpose of this utility model is to provide can effectively avoid the isolated switch converters and the controller thereof that lead directly to.
According to a kind of controller for isolated switch converters of the utility model embodiment, this switch converters comprises the transformer with armature winding and secondary winding, the secondary switch pipe that is coupled to the primary switch pipe of primary winding and is coupled to transformer secondary output winding, this controller comprises: error amplifying circuit, there is first input end, the second input and output, wherein first input end receives the feedback signal of representation switch converter output signal, the second input receives reference signal, error amplifying circuit is poor based on feedback signal and reference signal, at output, produce compensating signal, modulated signal producing circuit, produces modulation signal, the first comparison circuit, there is first input end, the second input and output, the output that wherein first input end is coupled to error amplifying circuit is to receive compensating signal, the second input is coupled to modulated signal producing circuit to receive modulation signal, the first comparison circuit compares compensating signal and modulation signal, at output, produces the first comparison signal, elementary shutoff testing circuit, whether detection of primary switching tube turn-offs, and produces elementary shutoff detection signal, inferior level logic circuit, is coupled to elementary shutoff testing circuit and the first comparison circuit to receive elementary shutoff detection signal and the first comparison signal, and produces secondary control signal to control secondary switch pipe based on elementary shutoff detection signal and the first comparison signal, buffer circuit, has input and output, and the output that wherein input is coupled to the first comparison circuit is to receive the first comparison signal, and buffer circuit, based on the first comparison signal, produces the synchronizing signal of isolating with the first comparison signal electricity at output, just level logic circuit, is coupled to the output of buffer circuit to receive synchronizing signal, and produces primary control signal to control primary switch pipe based on synchronizing signal, and zero cross detection circuit, detect the electric current zero passage whether flow through secondary switch pipe, and produce zero passage detection signal, wherein time level logic circuit is also coupled to zero cross detection circuit to receive zero passage detection signal, and produces secondary control signal based on elementary shutoff detection signal, the first comparison signal and zero passage detection signal.
In one embodiment, this controller also comprises: the second comparison circuit, there is first input end, the second input and output, wherein first input end receives the primary current sampled signal that primary switch tube current is flow through in representative, the second input receives first threshold voltage, the second comparison circuit compares primary current sampled signal and first threshold voltage, at output, produces the second comparison signal; The output that wherein just level logic circuit is also coupled to the second comparison circuit to be to receive the second comparison signal, and produces primary control signal based on the second comparison signal and synchronizing signal.
In one embodiment, this controller also comprises: threshold value produces circuit, there is input and output, the output that wherein input is coupled to buffer circuit is to receive synchronizing signal, output is coupled to the second input of the second comparison circuit, threshold value produces circuit based on synchronizing signal, at output, produces first threshold voltage.
In one embodiment, this controller also comprises: limit frequency circuit, there is input and output, the output that wherein input is coupled to the first comparison circuit is to receive the first comparison signal, output couples modulated signal producing circuit so that limit signal to be frequently provided, limit frequency circuit, by limit frequency signal, limits the frequency of modulation signal.
In one embodiment, elementary shutoff testing circuit comprises: the 3rd comparison circuit, there is first input end, the second input and output, wherein first input end is coupled to secondary switch pipe to receive the source voltage of secondary switch pipe, the second input receives Second Threshold voltage, the 3rd comparison circuit compares the source voltage of secondary switch pipe and Second Threshold voltage, at output, produces elementary shutoff detection signal.
In one embodiment, modulated signal producing circuit comprises: the first capacitor, there is first end and the second end, and the second input that wherein first end is coupled to the first comparison circuit is so that modulation signal to be provided, and the second end is coupled to secondary with reference to ground; The first switching tube, has first end, the second end and control end, and wherein first end is coupled to the first end of the first capacitor, and the second end is coupled to secondary with reference to ground, and control end is coupled to the output of the first comparison circuit; And first current source, there is input and output, wherein input is coupled to secondaryly with reference to ground, and output is coupled to the first end of the first capacitor.
In one embodiment, modulated signal producing circuit also comprises: Zener diode, there is anode and negative electrode, and wherein negative electrode is coupled to the first end of the first capacitor, and anode is coupled to secondary with reference to ground.
In one embodiment, threshold value produces circuit and comprises: timing circuit, there is input and output, and the output that wherein input is coupled to buffer circuit is to receive synchronizing signal, and timing circuit carries out timing based on synchronizing signal, at output, produces timing signal; The first trigger, there is first input end, the second input and output, the output that wherein first input end is coupled to buffer circuit is to receive synchronizing signal, the second input is coupled to the output of timing circuit to receive timing signal, the first trigger, based on synchronizing signal and timing signal, produces switch controlling signal at output; The second capacitor, has first end and the second end, and wherein the second end is coupled to elementary with reference to ground; The second current source, has input and output, and wherein input is coupled to the first end of the second capacitor, and output is coupled to elementary with reference to ground; The first voltage source, has anode and negative terminal, and wherein negative terminal is coupled to elementary with reference to ground; Second voltage source, has anode and negative terminal, and wherein negative terminal is coupled to elementary with reference to ground; The first diode, has anode and negative electrode, and its Anodic is coupled to the anode of the first voltage source, and negative electrode is coupled to the first end of the second capacitor; And second switch pipe, there is first end, the second end and control end, wherein first end is coupled to the first end of the second capacitor, and the second end is coupled to the anode in second voltage source, and control end is coupled to the output of the first trigger with receiving key control signal; Sampling hold circuit, there is first input end, the second input and output, wherein first input end is coupled to buffer circuit to receive synchronizing signal, the second input is coupled to the first end of the second capacitor to receive the voltage at the second capacitor two ends, sampling hold circuit to the maintenance of sampling of the voltage at the second capacitor two ends, produces first threshold voltage at output based on synchronizing signal.
In one embodiment, this controller also comprises: Fisrt fault testing circuit, and whether sense switch converter there is fault, and produces Fisrt fault detection signal; Or door, there is first input end, the second input and output, the output that wherein first input end is coupled to the first comparison circuit is to receive the first comparison signal, the second input is coupled to Fisrt fault testing circuit to receive Fisrt fault detection signal, and output is coupled to the input of buffer circuit so that Isolation input signal to be provided; Fisrt fault protective circuit; have input and output, the output that wherein input is coupled to buffer circuit is to receive synchronizing signal, and output is coupled to just level logic circuit; Fisrt fault protective circuit, based on synchronizing signal, produces Fisrt fault guard signal at output.
In one embodiment, this controller also comprises: undervoltage latch circuit, be coupled to power supply capacitor to receive supply power voltage, and undervoltage latch circuit compares supply power voltage and high threshold voltage and low threshold voltage, produces under-voltage latch signal; Start-up circuit, there is first input end, the second input and output, wherein first input end is coupled to undervoltage latch circuit to receive under-voltage latch signal, the second input is coupled to the output of buffer circuit to receive synchronizing signal, start-up circuit, based on under-voltage latch signal and synchronizing signal, produces enabling signal at output; Select circuit, there is first input end, the second input, control end and output, the output that wherein first input end is coupled to buffer circuit is to receive synchronizing signal, the second input receives peak frequency signal, control end is coupled to the output of start-up circuit to receive enabling signal, output is coupled to just level logic circuit and, so that asserts signal to be provided, selects circuit based on enabling signal, and synchronizing signal or peak frequency signal are passed to output.
In one embodiment, transformer also comprises by be coupled to the auxiliary winding of power supply capacitor for electric diode, this controller also comprises: supply current source, there is input, output and control end, wherein input is coupled to the armature winding of transformer, output is coupled to power supply capacitor, and control end is coupled to undervoltage latch circuit to receive under-voltage latch signal.
In one embodiment, start-up circuit comprises: single-shot trigger circuit, there is input and output, and wherein input is coupled to undervoltage latch circuit to receive under-voltage latch signal; And second trigger, there is first input end, the second input and output, wherein first input end is coupled to the output of single-shot trigger circuit, the second input is coupled to the output of buffer circuit to receive synchronizing signal, and output is coupled to selects the control end of circuit so that enabling signal to be provided.
In one embodiment; this controller also comprises: timing circuit; there is input and output; the output that wherein input couples start-up circuit is to receive enabling signal; output is coupled to just level logic circuit; timing circuit carries out timing based on enabling signal, at output, produces overcurrent protection signal.
According to a kind of controller for isolated switch converters of embodiment of the present utility model, this switch converters comprises the transformer with armature winding and secondary winding, be coupled to the primary switch pipe of primary winding, be coupled to secondary switch pipe and the buffer circuit of transformer secondary output winding, this controller comprises: error amplifying circuit, there is first input end, the second input and output, wherein first input end receives the feedback signal of representation switch converter output signal, the second input receives reference signal, error amplifying circuit is poor based on feedback signal and reference signal, at output, produce compensating signal, modulated signal producing circuit, produces modulation signal, the first comparison circuit, there is first input end, the second input and output, the output that wherein first input end is coupled to error amplifying circuit is to receive compensating signal, the second input is coupled to modulated signal producing circuit to receive modulation signal, output is coupled to the input of buffer circuit, the first comparison circuit compares compensating signal and modulation signal, at output, produces the first comparison signal, elementary shutoff testing circuit, whether detection of primary switching tube turn-offs, and produces elementary shutoff detection signal, inferior level logic circuit, is coupled to elementary shutoff testing circuit and the first comparison circuit to receive elementary shutoff detection signal and the first comparison signal, and produces secondary control signal to control secondary switch pipe based on elementary shutoff detection signal and the first comparison signal, just level logic circuit, is coupled to the output of buffer circuit to receive the synchronizing signal of isolating with the first comparison signal electricity, and produces primary control signal to control primary switch pipe based on synchronizing signal, and zero cross detection circuit, detect the electric current zero passage whether flow through secondary switch pipe, and produce zero passage detection signal, wherein time level logic circuit is also coupled to zero cross detection circuit to receive zero passage detection signal, and produces secondary control signal based on elementary shutoff detection signal, the first comparison signal and zero passage detection signal.
A kind of isolated switch converters according to the utility model embodiment, comprises foregoing controller.
In embodiment of the present utility model, based on elementary shutoff detection signal and the first comparison signal, produce secondary control signal to control secondary switch pipe, and the synchronizing signal based on the first comparison signal electricity isolation produces primary control signal to control primary switch pipe, can accurately control conducting and the shutoff of secondary switch pipe, without turn-off secondary switch pipe at primary switch pipe conducting rear, effectively avoided straight-through.
Accompanying drawing explanation
Fig. 1 is the oscillogram of existing intelligent synchronization commutation technique;
Fig. 2 is according to the block diagram of the isolated switch converters 200 of the utility model one embodiment;
Fig. 3 is according to the block diagram of the isolated switch converters 300 of the utility model one embodiment;
Fig. 4 is according to the circuit theory diagrams of the isolated switch converters 400 of the utility model one embodiment;
Fig. 5 is according to the working waveform figure of isolated switch converters 400 shown in Fig. 4 of the utility model embodiment under continuous current mode;
Fig. 6 is the graph of a relation between synchronizing frequency fsync and load current in isolated switch converters 400 shown in Fig. 4;
Fig. 7 produces the circuit theory diagrams of circuit 709 according to the threshold value of the utility model one embodiment;
Fig. 8 is that threshold value shown in Fig. 7 produces the graph of a relation between first threshold voltage VTH1 and synchronizing frequency fsync in circuit 709;
Fig. 9 is according to the circuit theory diagrams of the isolated switch converters 900 of the utility model one embodiment;
Figure 10 is according to the circuit theory diagrams of the Fisrt fault protective circuit 1017 of the utility model one embodiment;
Figure 11 is the working waveform figure when starting according to isolated switch converters 900 shown in Fig. 9 of the utility model embodiment;
Figure 12 is the working waveform figure when the error protection according to isolated switch converters 900 shown in Fig. 9 of the utility model embodiment.
Embodiment
To describe specific embodiment of the utility model in detail below, it should be noted that the embodiments described herein, only for illustrating, is not limited to the utility model.In the following description, in order to provide thorough understanding of the present utility model, a large amount of specific detail have been set forth.Yet, it will be obvious to those skilled in the art that and needn't adopt these specific detail to carry out the utility model.In other examples, for fear of obscuring the utility model, do not specifically describe known circuit, material or method.
In whole specification, " embodiment ", " embodiment ", " example " or mentioning of " example " are meaned: special characteristic, structure or characteristic in conjunction with this embodiment or example description are comprised at least one embodiment of the utility model.Therefore phrase " in one embodiment ", " in an embodiment ", " example " or " example ", occurring in each place of whole specification differs to establish a capital and refers to same embodiment or example.In addition, can with any suitable combination and/or sub-portfolio by specific feature, structure or property combination in one or more embodiment or example.In addition, it should be understood by one skilled in the art that the accompanying drawing providing at this is all for illustrative purposes, and accompanying drawing is not necessarily drawn in proportion.Should be appreciated that it can be directly connected or coupled to another element or can have intermediary element when claiming " element " " to be connected to " or " coupling " arrives another element.On the contrary, when claiming element " to be directly connected to " or during " being directly coupled to " another element, not having intermediary element.Identical Reference numeral is indicated identical element.Term "and/or" used herein comprises any and all combinations of one or more relevant projects of listing.
The utility model can be applied to any isolated converter.In ensuing detailed description, for simplicity, the anti exciting converter (flyback converter) of only take is explained specific works principle of the present utility model as example.
Fig. 2 is according to the block diagram of the isolated switch converters 200 of the utility model one embodiment.This isolated switch converters 200 comprises transformer T1, primary switch pipe MP, secondary switch pipe MS and controller.Transformer T1 has armature winding and secondary winding, and wherein armature winding and secondary winding all have first end and the second end, and the first end of armature winding receives input voltage vin, and the second end of secondary winding is coupled to secondary with reference to ground.Primary switch pipe MP is coupled in the second end of armature winding and elementary with reference between ground.Secondary switch pipe MS is coupled between the first end and load of secondary winding.Yet those skilled in the art are known, secondary switch pipe MS also can be coupled between second end and load of secondary winding.
Controller comprises just level logic circuit 201, buffer circuit 202, elementary shutoff testing circuit 203, inferior level logic circuit 204, the first comparison circuit 205, error amplifying circuit 206 and modulated signal producing circuit 207.In certain embodiments, controller and secondary switch pipe MS are integrated in same chip.Error amplifying circuit 206 has first input end, the second input and output, wherein first input end receives the feedback signal FB of representation switch converter output signal (for example output voltage, output current, power output), and the second input receives reference signal VREF.Error amplifying circuit 206 is poor based on feedback signal FB and reference signal VREF's, at output, produces compensating signal COMP.Modulated signal producing circuit 207 produces modulation signal VM, and this modulation signal VM can be sawtooth signal, triangular signal or other suitable signals.The first comparison circuit 205 has first input end, the second input and output, the output that wherein first input end is coupled to error amplifying circuit 206 is to receive compensating signal COMP, and the second input is coupled to modulated signal producing circuit 207 to receive modulation signal VM.The first comparison circuit 205 compares compensating signal COMP and modulation signal VM, at output, produces the first comparison signal CMPO1.
Whether elementary shutoff testing circuit 203 detection of primary switching tube MP turn-off, and produce elementary shutoff detection signal PROFF.Elementary shutoff testing circuit 203 can be based on secondary switch pipe MS drain-source voltage, the electric current that flows through secondary switch pipe MS, the electrical quantitys such as voltage at secondary winding two ends judge whether primary switch pipe MP turn-offs.Elementary shutoff testing circuit 203 also can obtain from primary side the signal whether indication primary switch pipe MP turn-offs by other means.
Inferior level logic circuit 204 has first input end, the second input and output, wherein first input end is coupled to elementary shutoff testing circuit 203 to receive elementary shutoff detection signal PROFF, and the second input is coupled to the first comparison circuit 205 to receive the first comparison signal CMPO1.Inferior level logic circuit 204 detects letter PROFF and the first comparison signal CMPO1 based on elementary shutoff, at output, produces secondary control signal CTRLS to control secondary switch pipe MS.
Buffer circuit 202 has input and output, and the output that wherein input is coupled to the first comparison circuit 205 is to receive the first comparison signal CMPO1.Buffer circuit 202, based on the first comparison signal CMPO1, produces the synchronizing signal SYNC isolating with the first comparison signal CMPO1 electricity at output.Buffer circuit 202 can comprise photoelectrical coupler, transformer or any other suitable electrical isolation device.In other embodiment, buffer circuit 202 can be arranged on controller outside.
Just level logic circuit 201 has input and output, and the output that wherein input is coupled to buffer circuit 202 is to receive synchronizing signal SYNC.Just level logic circuit 201, based on synchronizing signal SYNC, produces primary control signal CTRLP to control primary switch pipe MP at output.
Isolated switch converters 200 shown in Fig. 2 is controlled respectively primary switch pipe MP and secondary switch pipe MS based on the first comparison signal CMPO1, can accurately control the switching between primary switch pipe MP and secondary switch pipe MS, thereby without turn-off secondary switch pipe MS at primary switch pipe MP conducting rear, from principle, avoided straight-through.
In certain embodiments, turn-off rear be switched in order to ensure primary switch pipe MP at secondary switch pipe MS, delay circuit is coupled between the first comparison circuit 205 and buffer circuit 202, or between buffer circuit 202 and first level logic circuit 201.
Fig. 3 is according to the block diagram of the isolated switch converters 300 of the utility model one embodiment.With the switch converters 200 shown in Fig. 2 similarly,, switch converters 300 comprises transformer T1, primary switch pipe MP, secondary switch pipe MS, first level logic circuit 301, buffer circuit 302, elementary shutoff testing circuit 303, inferior level logic circuit 304, the first comparison circuit 305, error amplifying circuit 306 and modulated signal producing circuit 307.In addition, switch converters 300 also comprises the second comparison circuit 308.The second comparison circuit 308 has first input end, the second input and output, and wherein first input end receives the primary current sampled signal ISENP that primary switch pipe MP electric current is flow through in representative, and the second input receives first threshold voltage VTH1.The second comparison circuit 308 compares primary current sampled signal ISENP and first threshold voltage VTH1, at output, produces the second comparison signal CMPO2.The output that just level logic circuit 301 is coupled to the second comparison circuit 308 is to receive the second comparison signal CMPO2, and based on the second comparison signal CMPO2 and synchronizing signal SYNC, generation primary control signal CTRLP is to control primary switch pipe MP
First threshold voltage VTH1 can be steady state value, also can change with isolation signals SYNC.In one embodiment, switch converters 300 also comprises that threshold value produces circuit 309.Threshold value produces circuit 309 and has input and output, and the output that wherein input is coupled to buffer circuit 302 is to receive synchronizing signal SYNC, and output is coupled to the second input of the second comparison circuit 308.Threshold value produces circuit 309 and at output, produces first threshold voltage VTH1 based on synchronizing signal SYNC.
In some applications, for fear of reverse current, switch converters 300 also comprises zero cross detection circuit 310.Zero cross detection circuit 310 detects the electric current zero passage whether that flows through secondary switch pipe, and produces zero passage detection signal ZCD.Inferior level logic circuit 304 is coupled to zero cross detection circuit 310 to receive zero passage detection signal ZCD, and produces secondary control signal CTRLS based on elementary shutoff detection signal PROFF, the first comparison signal CMPO1 and zero passage detection signal ZCD.Inferior level logic circuit 304, when zero cross detection circuit 310 detects the current over-zero that flows through secondary switch pipe MS, turn-offs secondary switch pipe MS.
In certain embodiments, for the switching frequency of limit switch converter 300, limit frequency circuit 311 is coupled between the output and modulated signal producing circuit 307 of the first comparison circuit 305.Limit frequency circuit 311 has input and output, and the output that wherein input is coupled to the first comparison circuit 305 is to receive the first comparison signal CMPO1, and output is coupled to modulated signal producing circuit 307 so that limit signal FLMT to be frequently provided.Limit frequency circuit limits the frequency of modulation signal VM by limit frequency signal FLMT.
Fig. 4 is according to the circuit theory diagrams of the isolated switch converters 400 of the utility model one embodiment.Wherein just level logic circuit 401 comprises trigger FF1.Trigger FF1 has set end, reset terminal and output, the output that wherein set end is coupled to buffer circuit 402 is to receive synchronizing signal SYNC, reset terminal is coupled to the output of the second comparison circuit 408 to receive the second comparison signal CMPO2, and output is coupled to the grid of primary switch pipe MP so that primary control signal CTRLP to be provided.The second comparison circuit 408 comprises comparator C OM2.The in-phase input end of comparator C OM2 receives primary current sampled signal ISENP, and inverting input is coupled to threshold value and produces circuit 409 to receive first threshold voltage VTH1, and output is coupled to first level logic circuit 401 so that the second comparison signal CMPO2 to be provided.
Elementary shutoff testing circuit 403 comprises comparator C OM3.The in-phase input end of comparator C OM3 receives the source voltage Vss of secondary switch pipe MS, and inverting input receives Second Threshold voltage VTH2, and output is coupled to time level logic circuit 404 so that elementary shutoff detection signal PROFF to be provided.Zero cross detection circuit 410 comprises comparator C OM4.The in-phase input end of comparator C OM4 couples receives the 3rd threshold V T H3, and inverting input receives the secondary current sampled signal ISENS that secondary switch pipe MS electric current is flow through in representative, and output is coupled to time level logic circuit 404 so that zero passage detection signal ZCD to be provided.
Inferior level logic circuit 404 comprises or door OR1 and trigger FF2.Or a door OR1 has first input end, the second input and output, wherein first input end is coupled to zero cross detection circuit 410 to receive zero passage detection signal ZCD, and the second input is coupled to the first comparison circuit 405 to receive the first comparison signal CMPO1.Trigger FF2 has set end, reset terminal and output, the output that wherein set end is coupled to elementary shutoff testing circuit 403 is to receive elementary shutoff detection signal PROFF, reset terminal be coupled to or door OR1 output, output is coupled to the grid of secondary switch pipe MS so that secondary control signal CTRLS to be provided.
The first comparison circuit 405 comprises comparator C OM1.The in-phase input end of comparator C OM1 is coupled to modulated signal producing circuit 407 to receive modulation signal VM, inverting input is coupled to error amplifying circuit 406 to receive compensating signal COMP, and output is coupled to buffer circuit 402 and time level logic circuit 404 so that the first comparison signal CMPO1 to be provided.
Error amplifying circuit 406 comprises error amplifier EA.The in-phase input end of error amplifier EA receives the feedback signal FB that represents output voltage V out, and inverting input receives reference signal VREF, and output is coupled to the first comparison circuit 405 with the signal COMP that affords redress.
Modulated signal producing circuit 407 comprises capacitor C1, switching tube S1 and current source IS1.Capacitor C1 has first end and the second end, and wherein first end is coupled to the first comparison circuit 405 so that modulation signal VM to be provided, and the second end is coupled to secondary with reference to ground.Switching tube S1 has first end, the second end and control end, and wherein first end is coupled to the first end of capacitor C1, and the second end is coupled to secondary with reference to ground, and control end is coupled to the output of the first comparison circuit 405 by limit frequency circuit 411.Current source Is1 has input and output, and wherein input is coupled to secondary reference ground, and output is coupled to the first end of capacitor C1.In one embodiment, modulated signal producing circuit 407 also comprises Zener diode ZD1.The negative electrode of Zener diode ZD1 is coupled to the first end of capacitor C1, and anode is coupled to secondary with reference to ground.
Fig. 5 is according to the working waveform figure of isolated switch converters 400 shown in Fig. 4 of the utility model embodiment under continuous current mode.As shown in Figure 5, when modulation signal VM increases to compensating signal COMP, the first comparison signal CMPO1 becomes high level from low level.Trigger FF2 is reset, and secondary control signal CTRLS becomes low level from high level, and secondary switch pipe MS is turned off.Almost meanwhile, the synchronizing signal SYNC of buffer circuit 402 outputs also becomes high level from low level, and trigger FF1 is set, and primary control signal CTRLP becomes high level from low level, and primary switch pipe MP is switched on.The electric current that flows through primary switch pipe MP increases, and primary current sampled signal ISENP also increases.When elementary current sampling signal ISENP increases to first threshold voltage VTH1, trigger FF1 is reset, and primary control signal CTRLP becomes low level from high level, and primary switch pipe MP is turned off.After primary switch pipe MP is turned off, the source voltage Vss of secondary switch pipe MS becomes positive voltage from negative voltage, and is greater than Second Threshold voltage VTH2.Trigger FF2 is set, and secondary control signal CTRLS becomes high level from low level, and secondary switch pipe MS is switched on.Above step constantly repeats.
Fig. 6 is the frequency f sync of synchronizing signal SYNC and the graph of a relation between load current in isolated switch converters 400 shown in Fig. 4.When load current increases, feedback signal FB reduces, and compensating signal COMP also reduces.Modulation signal VM increases to the required time of compensating signal COMP and reduces, and cause the frequency of the first comparison signal CMPO1 to increase, thereby synchronizing frequency fsync also increases.When frequency f sync increases to after peak frequency fs_max, if load current continues to increase, under the effect of limit frequency circuit 411, frequency f sync will be restricted to peak frequency fs_max.
When load current reduces, feedback signal FB increases, and compensating signal COMP also increases.Modulation signal VM increases to the required time increase of compensating signal COMP, cause the frequency of the first comparison signal CMPO1 to reduce, thereby synchronizing frequency fsync also reduces.When compensating signal COMP increases to the puncture voltage of Zener diode ZD1, switch converters starts to enter discontinuous operation pattern, and now synchronizing frequency fsync equals fburst.If after this load current continues to reduce, modulation signal VM will be clamped to the puncture voltage that equals Zener diode ZD1, thereby slowly cannot be greater than compensating signal COMP.The first comparison signal CMPO1 and synchronizing signal SYNC will keep low level, until compensating signal COMP drops to below the puncture voltage of Zener diode ZD1.
Fig. 7 produces the circuit theory diagrams of circuit 709 according to the threshold value of the utility model one embodiment.Threshold value produces circuit 709 and comprises sampling hold circuit 7091, timing circuit 7092, trigger FF3, capacitor C2, current source Is2, voltage source V s1 and Vs2, diode D1 and switching tube S2.Timing circuit 7092 has input and output, and wherein input is coupled to buffer circuit to accept synchronizing signal SYNC.Timing circuit 7092 carries out timing based on synchronizing signal SYNC, at output, produces timing signal DLY.Trigger FF3 has set end, reset terminal and output, and wherein set end is coupled to buffer circuit to receive synchronizing signal SYNC, and reset terminal is coupled to the output of timing circuit 7092 to receive timing signal DLY.Trigger FF3, based on synchronizing signal SYNC and timing signal DLY, produces switch controlling signal CTRL at output.Capacitor C2 has first end and the second end, and wherein the second end is coupled to elementary with reference to ground.Current source Is2 has input and output, and wherein input is coupled to the first end of capacitor C2, and output is coupled to elementary with reference to ground.Voltage source V s1, Vs2 all have anode and negative terminal, and wherein negative terminal is all coupled to elementary with reference to ground.Diode D1 has anode and negative electrode, and its Anodic is coupled to the anode of voltage source V s1, and negative electrode is coupled to the first end of capacitor C2.Switching tube S2 has first end, the second end and control end, and wherein first end is coupled to the first end of capacitor C2, and the second end is coupled to the anode of voltage source V s2, and control end is coupled to the output of trigger FF3 with receiving key control signal CTRL.Sampling hold circuit 7091 has first input end, the second input and output, and wherein first input end is coupled to buffer circuit to receive synchronizing signal SYNC, and the second input is coupled to the first end of capacitor C2 with the voltage at receiving condenser C2 two ends.Sampling hold circuit 7091 for example,, to the maintenance of sampling of the voltage at capacitor C2 two ends, produces first threshold voltage VTH1 at output based on synchronizing signal SYNC (synchronizing signal SYNC rising edge).
Fig. 8 is that threshold value shown in Fig. 7 produces the graph of a relation between first threshold voltage VTH1 and synchronizing frequency fsync in circuit 709.As shown in Figure 8, when synchronizing frequency fsync is greater than second frequency threshold value fs2, the cycle of synchronizing signal SYNC is less than the timing threshold value 1/fs2 of timing circuit.At synchronizing signal SYNC, when low level becomes high level, timing circuit 7091 is reset, timing circuit 7091 timing of starting from scratch.Meanwhile, trigger FF3 is set, and switching tube S2 is switched on, and the voltage at capacitor C2 two ends equals the voltage that voltage source V s2 provides.Because cycle of synchronizing signal SYNC is less than the timing threshold value of timing circuit 7091, trigger FF3 will can not be reset, and switching tube S2 keeps conducting, and the voltage at capacitor C2 two ends remains unchanged.First threshold voltage VTH1 equals the voltage that voltage source V s2 provides.
When synchronizing frequency fsync is less than second frequency threshold value fs2 and is greater than first frequency threshold value fs1, the cycle of synchronizing signal SYNC is greater than the timing threshold value of timing circuit 7091.At synchronizing signal SYNC, when low level becomes high level, timing circuit 7091 is reset, timing circuit 7091 timing of starting from scratch.Meanwhile, trigger FF3 is set, and switching tube S2 is switched on, and the voltage at capacitor C2 two ends equals the voltage that voltage source V s2 provides.When the timing time of timing circuit 7091 reaches timing threshold value, trigger FF3 is reset.Switching tube S2 is turned off, and current source Is2 discharges to capacitor C2, and the voltage at capacitor C2 two ends reduces gradually.The cycle of synchronizing signal SYNC is longer, and the voltage at capacitor C2 two ends is less.That is to say, when synchronizing frequency fsync is less than second frequency threshold value fs2 and is greater than first frequency threshold value fs1, first threshold voltage VTH1 reduces with synchronizing frequency fsync and reduces.
When synchronizing frequency fsync is less than first frequency threshold value fs1, the cycle of synchronizing signal SYNC is greater than the timing threshold value of timing circuit 7091.At synchronizing signal SYNC, when low level becomes high level, timing circuit 7091 is reset, timing circuit 7091 timing of starting from scratch.Meanwhile, trigger FF3 is set, and switching tube S2 is switched on, and the voltage at capacitor C2 two ends equals the voltage that voltage source V s2 provides.When the timing time of timing circuit 7091 reaches timing threshold value, trigger FF3 is reset.Switching tube S2 is turned off, and current source Is2 discharges to capacitor C2, and the voltage at capacitor C2 two ends reduces gradually.Voltage when capacitor C2 two ends is decreased to the voltage that is less than voltage source V s1, and diode D1 is switched on, and the voltage at capacitor C2 two ends is clamped to the voltage of voltage source V s1.First threshold voltage VTH1 equals the voltage of voltage source V s1.
Fig. 9 is according to the circuit theory diagrams of the isolated switch converters 900 of the utility model one embodiment.It is basic identical that first level logic circuit 901 in Fig. 9, buffer circuit 902, elementary shutoff testing circuit 903, inferior level logic circuit 904, the first comparison circuit 905, error amplifying circuit 906, modulated signal producing circuit 907, the second comparison circuit 908, threshold value produce related circuit shown in circuit 909, zero cross detection circuit 910, limit frequency circuit 911 and Fig. 4.Compare with switch converters shown in Fig. 4 400, transformer T1 also comprises the auxiliary winding with first end and the second end, and wherein the second end of auxiliary winding is coupled to elementary with reference to ground.Switch converters 900 also comprises for electric diode Ds, power supply capacitor Cs, supply current source Iss, selects circuit 912, start-up circuit 913 and undervoltage latch circuit 914.Power supply capacitor Cs has first end and the second end, and the control circuit that wherein first end is primary side provides supply power voltage Vcc, and the second end is coupled to elementary with reference to ground.For electric diode Ds, have anode and negative electrode, its Anodic is coupled to the first end of auxiliary winding, and negative electrode is coupled to the first end of power supply capacitor Cs.Undervoltage latch circuit 914 is coupled to the first end of power supply capacitor Cs to receive supply power voltage Vcc, and supply power voltage Vcc and high threshold voltage VTH_H and low threshold voltage VTH_L are compared, and produces under-voltage latch signal UVLO.Supply current source Iss has input, output and control end, the first end that wherein input is coupled to armature winding is to receive input voltage vin, output is coupled to the first end of power supply capacitor Cs, and control end is coupled to undervoltage latch circuit 914 to receive under-voltage latch signal UVLO.When supply power voltage Vcc is during higher than high threshold voltage VTH_H, supply current source Iss is closed.When supply power voltage Vcc is during lower than low threshold voltage VTH_L, supply current source Iss is unlocked, thereby is power supply capacitor Cs charging.In certain embodiments, when supply power voltage Vcc is during lower than low threshold voltage VTH_L, by supply power voltage Vcc, provide the primary side control circuit of energy mostly to quit work, to avoid misoperation.
Start-up circuit 913 has first input end, the second input and output, and wherein first input end is coupled to undervoltage latch circuit 914 to receive under-voltage latch signal UVLO, and the second input is coupled to the output of buffer circuit 902 to receive synchronizing signal SYNC.Start-up circuit 913, based on under-voltage latch signal UVLO and synchronizing signal SYNC, produces enabling signal STAUP at output.Select circuit 912 to there is first input end, the second input, control end and output, the output that wherein first input end is coupled to buffer circuit 902 is to receive synchronizing signal SYNC, the second input receives peak frequency signal FMAX, control end is coupled to the output of start-up circuit 913 to receive enabling signal STAUP, and output is coupled to first level logic circuit 901 so that asserts signal SET to be provided.Select circuit 912 based on enabling signal STAUP, synchronizing signal SYNC or peak frequency signal FMAX are passed to output.
In the embodiment shown in fig. 9, undervoltage latch circuit 914 comprises hysteresis comparator COM5, and start-up circuit 913 comprises single-shot trigger circuit 9131 and trigger FF4.Single-shot trigger circuit 9131 has input and output, and wherein input is coupled to undervoltage latch circuit 914 to receive under-voltage latch signal UVLO.Trigger FF4 has set end, reset terminal and output, wherein set end is coupled to the output of single-shot trigger circuit 9131, reset terminal is coupled to the output of buffer circuit 902 to receive synchronizing signal SYNC, and output is coupled to selects the control end of circuit 912 so that enabling signal STAUP to be provided.Trigger FF4 is preferential for resetting.
In certain embodiments, under nonserviceabling, cannot move by shutdown switch for fear of switch converters 900, switch converters 900 also comprises timing circuit 915.Timing circuit 915 has input and output, and the output that wherein input couples start-up circuit 913 is to receive enabling signal STAUP, and output is coupled to just level logic circuit 901.Timing circuit 915 carries out timing based on enabling signal STAUP, at output, produces overcurrent protection signal OCP.When the timing time of timing circuit 915 surpasses Preset Time threshold value, first level logic circuit 901 turn-offs primary switch pipe MP.
In certain embodiments, switch converters 900 also comprises Fisrt fault protective circuit 916, Fisrt fault testing circuit 917 and or door OR2.Whether Fisrt fault testing circuit 917 sense switch converters 900 there is fault (such as overvoltage, excess temperature etc.), and produce Fisrt fault detection signal FAUT1.Or door OR2 has first input end, the second input and output, the output that wherein first input end is coupled to the first comparison circuit 905 is to receive the first comparison signal CMPO1, the second input is coupled to Fisrt fault testing circuit 917 to receive Fisrt fault detection signal FAUT1, and output is coupled to the input of buffer circuit 902 so that Isolation input signal ISOIN to be provided.Fisrt fault protective circuit 916 has input and output, and the output that wherein input is coupled to buffer circuit 902 is to receive synchronizing signal SYNC, and output is coupled to just level logic circuit 901.Fisrt fault protective circuit, based on synchronizing signal SYNC, produces Fisrt fault guard signal FAP1 at output.If Fisrt fault testing circuit 917 detects switch converters 900 and has fault, Fisrt fault detection signal FAUT1 is set to high level, Isolation input signal ISOIN and synchronizing signal SYNC or door OR2 effect under keep high level.When Fisrt fault protective circuit 916 detects synchronizing signal SYNC for lasting high level, first level logic circuit 901 turn-offs primary switch pipe MP.
In other embodiments, switch converters 900 also can make synchronizing signal SYNC keep low level when fault being detected, thereby maintain primary switch pipe MP, turn-offs.This can be by being coupled to realizing with door of buffer circuit 902 inputs.
Above two kinds of error protection modes also can mutually combine, thereby protect for switch converters 900 provides more fully.In embodiment as shown in Figure 9, switch converters 900 also comprise the second failure detector circuit 918 and with door AND1.Whether the second failure detector circuit 918 sense switch converters there is fault (such as overload, overcurrent etc.), and produce the second fault detection signal FAUT2.There is first input end, the second input and output with door AND1, the output that wherein first input end is coupled to the first comparison circuit 905 is to receive the first comparison signal CMPO1, the second input is coupled to the second failure detector circuit 918 to receive the second fault detection signal FAUT2, output be coupled to or door OR2 first input end.
Figure 10 is according to the circuit theory diagrams of the Fisrt fault protective circuit 1017 of the utility model one embodiment.Fisrt fault protective circuit 1017 comprises not gate NOT1, switching tube S3, capacitor C3, current source Is3 and comparator C OM6.Not gate NOT1 has input and output, and wherein input receives synchronizing signal SYNC.Capacitor C3 has first end and the second end, and wherein the second end is coupled to elementary with reference to ground.Switching tube S3 has first end, the second end and control end, and wherein first end is coupled to the first end of capacitor C3, and the second end is coupled to elementary with reference to ground, and control end is coupled to the output of not gate NOT1.Current source Is3 has input and output, and wherein input is coupled to elementary reference ground, and output is coupled to the first end of capacitor C3.The in-phase input end of comparator C OM6 is coupled to the first end of capacitor C3, and inverting input receives the 4th threshold V T H4, and output provides Fisrt fault guard signal FAP1.
When synchronizing signal SYNC is high level, switching tube S3 turn-offs, and current source Is3 charges to capacitor C3, and the voltage at capacitor C3 two ends increases gradually.When synchronizing signal SYNC is low level, switching tube S3 conducting, capacitor C3 electric discharge, the voltage at capacitor C3 two ends reduces rapidly.In normal operation, synchronizing signal SYNC is pulse signal, and the voltage at capacitor C3 two ends can be discharged to zero before increasing to the 4th threshold V T H4, and Fisrt fault guard signal FAP1 keeps low level.When Fisrt fault testing circuit detects malfunction, synchronizing signal SYNC continues high level, and the voltage at capacitor C3 two ends will increase to the 4th threshold V T H4, makes Fisrt fault guard signal FAP1 become high level.
Figure 11 is the working waveform figure when starting according to isolated switch converters 900 shown in Fig. 9 of the utility model embodiment.At t0 constantly, switch converters 900 starts, and supply current source Iss is to power supply capacitor Cs charging, and supply power voltage Vcc increases gradually.Now, because supply power voltage Vcc is not enough, the control circuit of primary side is not worked, and peak frequency signal FMAX does not produce, and under-voltage latch signal UVLO is initial low level.Meanwhile, owing to not having energy to be passed to the primary side of transformer T1, the supply power voltage of primary side (for example output voltage V out) deficiency, the control circuit of primary side is not worked, and Isolation input signal ISOIN does not also produce.Primary switch pipe MP and secondary switch pipe MS all keep turn-offing.
At t1 constantly, supply power voltage Vcc increases to low threshold voltage VTH_L, and under-voltage latch signal UVLO keeps low level.
At t2 constantly, supply power voltage Vcc increases to high threshold voltage VTH_H, and peak frequency signal FMAX occurs.Under-voltage latch signal UVLO becomes high level from low level, and supply current source Iss is closed, and the auxiliary winding of transformer T1 provides energy for power supply capacitor Cs.Trigger FF4 is set, and enabling signal STAUP becomes high level from low level, and asserts signal SET equals peak frequency signal FMAX.Primary switch pipe MP starts conducting and shutoff, thereby the body diode by secondary switch pipe MS is passed to load by energy.
At t3 constantly, the control circuit of primary side is started working, and Isolation input signal ISOIN is admitted to buffer circuit 902.Trigger FF4 is reset at the rising edge of synchronizing signal SYNC, and enabling signal STAUP becomes low level from high level, and asserts signal SET equals synchronizing signal SYNC.Switch converters 900 enters normal operating conditions.
Figure 12 is the working waveform figure when the error protection according to isolated switch converters 900 shown in Fig. 9 of the utility model embodiment.At t4 constantly, the second failure detector circuit 918 detects malfunction, makes Isolation input signal ISOIN keep low level.Synchronizing signal SYNC also keeps low level.Primary switch pipe MP keeps turn-offing, and stops providing energy to load.The auxiliary winding of transformer T1 cannot continue as power supply capacitor Cs energy is provided, and supply power voltage Vcc starts to reduce.
At t5 constantly, supply power voltage Vcc is decreased to low threshold voltage VTH_L, and under-voltage latch signal UVLO becomes low level from high level, and supply current source Iss is switched on, and supply power voltage Vcc starts to increase immediately.
At t6 constantly, supply power voltage Vcc increases to high threshold voltage VTH_H, and under-voltage latch signal UVLO becomes high level from low level, and supply current source Iss is closed.Trigger FF4 is set, and enabling signal STAUP becomes high level from low level, and asserts signal SET equals peak frequency signal FMAX.
At t7 constantly, the second failure detector circuit 918 detects malfunction and disappears, and Isolation input signal ISOIN equals the first comparison signal CMPO1.Trigger FF4 is reset at the rising edge of synchronizing signal SYNC, and enabling signal STAUP becomes low level from high level, and asserts signal SET equals synchronizing signal SYNC.Switch converters 900 recovers normal operating conditions.
Above-mentioned specification and execution mode are only exemplary, and are not used in the scope of the present utility model that limits.It is all possible for disclosed embodiment, changing and revise, the selectivity embodiment that other are feasible and can being understood by those skilled in the art the equivalent variations of element in embodiment.Other variations of embodiment disclosed in the utility model and modification do not exceed spirit of the present utility model and protection range.
Claims (15)
1. the controller for isolated switch converters, this switch converters comprise there is the transformer of armature winding and secondary winding, the secondary switch pipe that is coupled to the primary switch pipe of primary winding and is coupled to transformer secondary output winding, it is characterized in that, this controller comprises:
Error amplifying circuit, there is first input end, the second input and output, wherein first input end receives the feedback signal of representation switch converter output signal, the second input receives reference signal, error amplifying circuit is poor based on feedback signal and reference signal, at output, produces compensating signal;
Modulated signal producing circuit, produces modulation signal;
The first comparison circuit, there is first input end, the second input and output, the output that wherein first input end is coupled to error amplifying circuit is to receive compensating signal, the second input is coupled to modulated signal producing circuit to receive modulation signal, the first comparison circuit compares compensating signal and modulation signal, at output, produces the first comparison signal;
Elementary shutoff testing circuit, whether detection of primary switching tube turn-offs, and produces elementary shutoff detection signal;
Inferior level logic circuit, is coupled to elementary shutoff testing circuit and the first comparison circuit to receive elementary shutoff detection signal and the first comparison signal, and produces secondary control signal to control secondary switch pipe based on elementary shutoff detection signal and the first comparison signal;
Buffer circuit, has input and output, and the output that wherein input is coupled to the first comparison circuit is to receive the first comparison signal, and buffer circuit, based on the first comparison signal, produces the synchronizing signal of isolating with the first comparison signal electricity at output;
Just level logic circuit, is coupled to the output of buffer circuit to receive synchronizing signal, and produces primary control signal to control primary switch pipe based on synchronizing signal; And
Zero cross detection circuit, detects the electric current zero passage whether flow through secondary switch pipe, and produces zero passage detection signal;
Wherein time level logic circuit is also coupled to zero cross detection circuit to receive zero passage detection signal, and produces secondary control signal based on elementary shutoff detection signal, the first comparison signal and zero passage detection signal.
2. controller as claimed in claim 1, is characterized in that, also comprises:
The second comparison circuit, there is first input end, the second input and output, wherein first input end receives the primary current sampled signal that primary switch tube current is flow through in representative, the second input receives first threshold voltage, the second comparison circuit compares primary current sampled signal and first threshold voltage, at output, produces the second comparison signal;
The output that wherein just level logic circuit is also coupled to the second comparison circuit to be to receive the second comparison signal, and produces primary control signal based on the second comparison signal and synchronizing signal.
3. controller as claimed in claim 2, is characterized in that, also comprises:
Threshold value produces circuit, have input and output, the output that wherein input is coupled to buffer circuit is to receive synchronizing signal, and output is coupled to the second input of the second comparison circuit, threshold value produces circuit based on synchronizing signal, at output, produces first threshold voltage.
4. controller as claimed in claim 1, is characterized in that, also comprises:
Limit frequency circuit, have input and output, the output that wherein input is coupled to the first comparison circuit is to receive the first comparison signal, and output couples modulated signal producing circuit so that limit signal to be frequently provided, limit frequency circuit, by limit frequency signal, limits the frequency of modulation signal.
5. controller as claimed in claim 1, is characterized in that, elementary shutoff testing circuit comprises:
The 3rd comparison circuit, there is first input end, the second input and output, wherein first input end is coupled to secondary switch pipe to receive the source voltage of secondary switch pipe, the second input receives Second Threshold voltage, the 3rd comparison circuit compares the source voltage of secondary switch pipe and Second Threshold voltage, at output, produces elementary shutoff detection signal.
6. controller as claimed in claim 1, is characterized in that, modulated signal producing circuit comprises:
The first capacitor, has first end and the second end, and the second input that wherein first end is coupled to the first comparison circuit is so that modulation signal to be provided, and the second end is coupled to secondary with reference to ground;
The first switching tube, has first end, the second end and control end, and wherein first end is coupled to the first end of the first capacitor, and the second end is coupled to secondary with reference to ground, and control end is coupled to the output of the first comparison circuit; And
The first current source, has input and output, and wherein input is coupled to secondary reference ground, and output is coupled to the first end of the first capacitor.
7. controller as claimed in claim 6, is characterized in that, modulated signal producing circuit also comprises:
Zener diode, has anode and negative electrode, and wherein negative electrode is coupled to the first end of the first capacitor, and anode is coupled to secondary with reference to ground.
8. controller as claimed in claim 3, is characterized in that, threshold value produces circuit and comprises:
Timing circuit, has input and output, and the output that wherein input is coupled to buffer circuit is to receive synchronizing signal, and timing circuit carries out timing based on synchronizing signal, at output, produces timing signal;
The first trigger, there is first input end, the second input and output, the output that wherein first input end is coupled to buffer circuit is to receive synchronizing signal, the second input is coupled to the output of timing circuit to receive timing signal, the first trigger, based on synchronizing signal and timing signal, produces switch controlling signal at output;
The second capacitor, has first end and the second end, and wherein the second end is coupled to elementary with reference to ground;
The second current source, has input and output, and wherein input is coupled to the first end of the second capacitor, and output is coupled to elementary with reference to ground;
The first voltage source, has anode and negative terminal, and wherein negative terminal is coupled to elementary with reference to ground;
Second voltage source, has anode and negative terminal, and wherein negative terminal is coupled to elementary with reference to ground;
The first diode, has anode and negative electrode, and its Anodic is coupled to the anode of the first voltage source, and negative electrode is coupled to the first end of the second capacitor; And
Second switch pipe, has first end, the second end and control end, and wherein first end is coupled to the first end of the second capacitor, and the second end is coupled to the anode in second voltage source, and control end is coupled to the output of the first trigger with receiving key control signal;
Sampling hold circuit, there is first input end, the second input and output, wherein first input end is coupled to buffer circuit to receive synchronizing signal, the second input is coupled to the first end of the second capacitor to receive the voltage at the second capacitor two ends, sampling hold circuit to the maintenance of sampling of the voltage at the second capacitor two ends, produces first threshold voltage at output based on synchronizing signal.
9. controller as claimed in claim 1, is characterized in that, also comprises:
Fisrt fault testing circuit, whether sense switch converter there is fault, and produces Fisrt fault detection signal;
Or door, there is first input end, the second input and output, the output that wherein first input end is coupled to the first comparison circuit is to receive the first comparison signal, the second input is coupled to Fisrt fault testing circuit to receive Fisrt fault detection signal, and output is coupled to the input of buffer circuit so that Isolation input signal to be provided;
Fisrt fault protective circuit; have input and output, the output that wherein input is coupled to buffer circuit is to receive synchronizing signal, and output is coupled to just level logic circuit; Fisrt fault protective circuit, based on synchronizing signal, produces Fisrt fault guard signal at output.
10. controller as claimed in claim 1, is characterized in that, also comprises:
Undervoltage latch circuit, is coupled to power supply capacitor to receive supply power voltage, and undervoltage latch circuit compares supply power voltage and high threshold voltage and low threshold voltage, produces under-voltage latch signal;
Start-up circuit, there is first input end, the second input and output, wherein first input end is coupled to undervoltage latch circuit to receive under-voltage latch signal, the second input is coupled to the output of buffer circuit to receive synchronizing signal, start-up circuit, based on under-voltage latch signal and synchronizing signal, produces enabling signal at output;
Select circuit, there is first input end, the second input, control end and output, the output that wherein first input end is coupled to buffer circuit is to receive synchronizing signal, the second input receives peak frequency signal, control end is coupled to the output of start-up circuit to receive enabling signal, output is coupled to just level logic circuit and, so that asserts signal to be provided, selects circuit based on enabling signal, and synchronizing signal or peak frequency signal are passed to output.
11. controllers as claimed in claim 10, is characterized in that, transformer also comprises that this controller also comprises by be coupled to the auxiliary winding of power supply capacitor for electric diode:
Supply current source, has input, output and control end, and wherein input is coupled to the armature winding of transformer, and output is coupled to power supply capacitor, and control end is coupled to undervoltage latch circuit to receive under-voltage latch signal.
12. controllers as claimed in claim 10, is characterized in that, start-up circuit comprises:
Single-shot trigger circuit, has input and output, and wherein input is coupled to undervoltage latch circuit to receive under-voltage latch signal; And
The second trigger, there is first input end, the second input and output, wherein first input end is coupled to the output of single-shot trigger circuit, and the second input is coupled to the output of buffer circuit to receive synchronizing signal, and output is coupled to selects the control end of circuit so that enabling signal to be provided.
13. controllers as claimed in claim 10, is characterized in that, also comprise:
Timing circuit, has input and output, and the output that wherein input couples start-up circuit is to receive enabling signal, and output is coupled to just level logic circuit, and timing circuit carries out timing based on enabling signal, at output, produces overcurrent protection signal.
14. 1 kinds of controllers for isolated switch converters, this switch converters comprise have armature winding and secondary winding transformer, be coupled to primary winding primary switch pipe, be coupled to secondary switch pipe and the buffer circuit of transformer secondary output winding, it is characterized in that, this controller comprises:
Error amplifying circuit, there is first input end, the second input and output, wherein first input end receives the feedback signal of representation switch converter output signal, the second input receives reference signal, error amplifying circuit is poor based on feedback signal and reference signal, at output, produces compensating signal;
Modulated signal producing circuit, produces modulation signal;
The first comparison circuit, there is first input end, the second input and output, the output that wherein first input end is coupled to error amplifying circuit is to receive compensating signal, the second input is coupled to modulated signal producing circuit to receive modulation signal, output is coupled to the input of buffer circuit, the first comparison circuit compares compensating signal and modulation signal, at output, produces the first comparison signal;
Elementary shutoff testing circuit, whether detection of primary switching tube turn-offs, and produces elementary shutoff detection signal;
Inferior level logic circuit, is coupled to elementary shutoff testing circuit and the first comparison circuit to receive elementary shutoff detection signal and the first comparison signal, and produces secondary control signal to control secondary switch pipe based on elementary shutoff detection signal and the first comparison signal;
Just level logic circuit, is coupled to the output of buffer circuit to receive the synchronizing signal of isolating with the first comparison signal electricity, and produces primary control signal to control primary switch pipe based on synchronizing signal; And
Zero cross detection circuit, detects the electric current zero passage whether flow through secondary switch pipe, and produces zero passage detection signal;
Wherein time level logic circuit is also coupled to zero cross detection circuit to receive zero passage detection signal, and produces secondary control signal based on elementary shutoff detection signal, the first comparison signal and zero passage detection signal.
15. 1 kinds of isolated switch converters, is characterized in that, comprise the controller as described in any one in claim 1 to 14.
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| CN108923654A (en) * | 2018-07-16 | 2018-11-30 | 成都芯源系统有限公司 | Fully integrated isolation conversion circuit and method |
| CN111541361A (en) * | 2020-06-05 | 2020-08-14 | 上海晶丰明源半导体股份有限公司 | Synchronous rectification isolation drive circuit and synchronous rectification isolation power supply system |
| CN112260550A (en) * | 2019-11-12 | 2021-01-22 | 成都芯源系统有限公司 | Isolated resonant converter and control method thereof |
| CN112583271A (en) * | 2019-09-30 | 2021-03-30 | 比亚迪半导体股份有限公司 | Secondary synchronous rectification circuit and secondary synchronous rectification chip of charging system |
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2013
- 2013-10-12 CN CN201320629780.7U patent/CN203491883U/en not_active Expired - Fee Related
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| CN108923654A (en) * | 2018-07-16 | 2018-11-30 | 成都芯源系统有限公司 | Fully integrated isolation conversion circuit and method |
| CN108923654B (en) * | 2018-07-16 | 2020-08-25 | 成都芯源系统有限公司 | Fully integrated isolation conversion circuit and method |
| CN112583271A (en) * | 2019-09-30 | 2021-03-30 | 比亚迪半导体股份有限公司 | Secondary synchronous rectification circuit and secondary synchronous rectification chip of charging system |
| CN112583271B (en) * | 2019-09-30 | 2022-05-20 | 比亚迪半导体股份有限公司 | Secondary synchronous rectification circuit and secondary synchronous rectification chip of charging system |
| CN112260550A (en) * | 2019-11-12 | 2021-01-22 | 成都芯源系统有限公司 | Isolated resonant converter and control method thereof |
| CN112260550B (en) * | 2019-11-12 | 2022-01-07 | 成都芯源系统有限公司 | Isolated resonant converter and control method thereof |
| CN111541361A (en) * | 2020-06-05 | 2020-08-14 | 上海晶丰明源半导体股份有限公司 | Synchronous rectification isolation drive circuit and synchronous rectification isolation power supply system |
| CN111541361B (en) * | 2020-06-05 | 2023-09-22 | 上海晶丰明源半导体股份有限公司 | Synchronous rectification isolation driving circuit and synchronous rectification isolation power supply system |
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Inventor after: Wang Siran Inventor after: Yang Xianqing Inventor after: John Wei Genhuoen Inventor after: Zhao Qiming Inventor before: Wang Siran Inventor before: Yang Zhijiang Inventor before: John Wei Genhuoen Inventor before: Zhao Qiming |
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