CN209029377U - Current foldback circuit for GaN power integration module - Google Patents
Current foldback circuit for GaN power integration module Download PDFInfo
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- CN209029377U CN209029377U CN201821963635.1U CN201821963635U CN209029377U CN 209029377 U CN209029377 U CN 209029377U CN 201821963635 U CN201821963635 U CN 201821963635U CN 209029377 U CN209029377 U CN 209029377U
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Abstract
The utility model discloses a kind of current foldback circuit for GaN power integration module, including 2 current sense resistors, 5 biasing resistors, 1 voltage clamping diode, 1 rectifier diode, 1 filter capacitor C1,2 triodes, 7 NMOS tubes and 6 PMOS tube；It is low that the current foldback circuit can detect power device output off current HIGH automatically, automatically shuts down GaN FETs device when current is excessive, and can filter out the interference of the spike burr signal occurred on supply voltage, guarantees that the working characteristics of GaN FETs is in safety zone.
Description
Technical field
The invention belongs to electronic circuit design fields, are applied to HEMT device in GaN power module more particularly, to one kind
The current foldback circuit of part gate driving and protection.
Technical background
Conventional electric power electronic power components based on silicon materials its theoretical limit of Step wise approximation, it is difficult to meet electric power
The growth requirement of electronic technology high frequency and high power density.Compared with traditional Si device, GaN device presents it and is leading
The advantage being powered on resistance and gate charge can make power converter realize smaller volume, higher frequency and higher efficiency, thus
It has broad application prospects in the fields such as automobile, communication, industry.The raising of switching frequency, can not only effectively reduce and be
The size of capacitor, inductance and transformer in system circuit, but also interference can be inhibited, reduce ripple, improve power-supply system unit
Gain bandwidth is to improve its dynamic response performance.And the gate driving circuit of high speed is used to drive GaN power device, so that whole
A power converter reaches high efficiency and reduces circuit area, saves cost.
Fig. 1 shows most common typical case's GaN half-bridge drive circuit block diagram in power module.As shown in Figure 1, typical
GaN half-bridge drive circuit is divided into high-end and low side two paths, by the way of Bootstrap, two-way low pressure input channel.?
During low side power GaN device is connected, switching node (SW) is pulled down to ground, and VDD gives bootstrapping electricity by bootstrap diode at this time
Capacity charge makes bootstrap capacitor voltage difference of the two ends close to VDD.Instantly when end pipe is closed, high-end input signal opens high-end tubes,
Node voltage rises to VIN, i.e. VSW rises to VIN.Since bootstrap capacitor both end voltage is constant, therefore bootstrap voltage mode rail HB
VSW+VDD is arrived by bootstrapping.High side circuitry remains VHB-VSW ≈ VDD.And HB is by bootstrap capacitor when being booted, bootstrap diode
Cathode voltage be high potential, be higher than anode voltage VDD, therefore the reverse-biased cut-off of bootstrap diode.
It is widely used for GaN FETs at present in GaN power device, mainly there is following spy compared with Si MOSFET
Point: small in same resistance to pressure conducting resistance and device volume；Switching speed is fast；Current density is big, and power density is high.GaN
These features of FETs ensure that GaN FETs has boundless prospect and market in the following power electronics applications field.But
Be that there is also some factors paid particular attention to: threshold voltage is low；Gate source voltage upper limit VGS (MAX) is low；It can reverse-conducting.
It is above-mentioned need to special consideration should be given to factor can bring some problems when driving GaN device, cause to be traditionally used for MOS power device at present
The driving circuit of part is not particularly suited for GaN power device.Since the working frequency of GaN FETs is often in MHz rank, GaN
The frequency converter of FETs will become abnormal important, wherein the 6th excessively high bring integrity problem caused by short circuit is a weight
Limiting factor is wanted, therefore it is necessary to provide a kind of novel current foldback circuit, the working characteristics of guarantee GaN FETs is in peace
The whole district.
Summary of the invention
The purpose of this utility model is to improve the reliability of GaN power module, and in particular to one kind is applied to GaN power mould
The current foldback circuit of HEMT device gate driving and protection in block.
The purpose of this utility model can be achieved through the following technical solutions:
A kind of current foldback circuit for GaN power integration module, it is characterized in that: including 2 current sense resistors, 5
A biasing resistor, 1 voltage clamping diode, 1 rectifier diode, 1 filter capacitor C1,2 triodes, 7 NMOS tubes
With 6 PMOS tube；
The connection relationship of the current foldback circuit for GaN power integration module are as follows: the first current sense resistor Rd1
Upper end be connected to the upper end of the second current sense resistor Rd2, be also connected to the first triode Q1 base stage and electric current to be detected
Input terminal；The lower end of first current sense resistor Rd1 is connected to the lower end of the second current sense resistor Rd2, is also connected to ground electricity
It is flat；The collector of first triode Q1 is connected to the source of the 6th NMOS tube M6, and the emitter of the first triode Q1 is connected to
The emitter of the upper end of three biasing resistor R3 and the second triode Q2；The base stage of second triode Q2 connects the second biasing resistor R2
Upper end and the first biasing resistor R1 lower end；The lower end of second biasing resistor R2 is connected to ground level；First biasing resistor R1
Upper end connect the 5th biasing resistor R5 lower end and voltage clamping diode Z1 anode；The negative terminal of voltage clamping diode Z1
It is connected to ground level；The upper termination supply voltage of 5th biasing resistor R5；The drain terminal of 6th NMOS tube M6 is connected to the first PMOS
The drain terminal and grid end of pipe M1 is also connected to the grid end of the second PMOS tube M2 and the grid end of the 4th PMOS tube M4；Second PMOS tube M2
Drain terminal be connected to the drain terminal of the 7th NMOS tube M7, be also connected to the drain terminal and grid end of third PMOS tube M3, be also connected to the 5th
The grid end of PMOS tube M5；The drain terminal of 4th PMOS tube M4 is connected to the drain terminal of the 8th NMOS tube M8；The drain terminal of 5th PMOS tube M5
It is connected to the drain terminal of the 9th NMOS tube M9；The source of 8th NMOS tube M8 is connected to the drain terminal of the tenth NMOS tube M10, is also connected to
The grid end of 13rd NMOS tube M13 and the 12nd PMOS tube M12；The source of 9th NMOS tube M9 is connected to the 11st NMOS tube
The drain terminal and grid end of M11；13rd NMOS tube M13's is connected with the 12nd PMOS tube M12 drain terminal, and exports and differentiate signal OC；
The lower end earth level of filter capacitor C1, the upper end of filter capacitor C1 are connected to two poles of lower end and rectification of the 4th biasing resistor R4
The anode of pipe D1, the upper end of filter capacitor C1 are also connected to the 6th NMOS tube M6, the 7th NMOS tube M7, the 8th NMOS tube M8 and
The grid end of nine NMOS tube M9, the upper end of filter capacitor C1 are also connected to the source of the 12nd PMOS tube M12；Except the 12nd PMOS tube
The source of remaining PMOS tube other than M12 connects supply voltage；11st NMOS tube M11, the 13rd NMOS tube M13 and the tenth
The equal earth level of the source of NMOS tube M10；The substrate of all PMOS tube connects supply voltage, and the substrate of all NMOS tubes is grounded
Level.
The utility model has the advantages that: automatic detection power device output off current HIGH is low, automatically shuts down when current is excessive
GaN FETs device, and the interference of the spike burr signal occurred on supply voltage can be filtered out, guarantee the work of GaN FETs
Make characteristic and is in safety zone.
Detailed description of the invention
Fig. 1 shows typical GaN half-bridge drive circuit block diagram according to prior art；
Fig. 2 is schematic diagram of the utility model for the current foldback circuit of GaN power integration module；
Fig. 3 is the Transient figure of the utility model current foldback circuit.
Specific embodiment
The utility model is described in more detail with example with reference to the accompanying drawing.
As shown in Fig. 2, a kind of current foldback circuit for GaN power integration module, including 2 current sense resistors, 5
A biasing resistor, 1 voltage clamping diode, 1 rectifier diode, 1 filter capacitor C1,2 triodes, 7 NMOS tubes
With 6 PMOS tube.
The connection relationship of circuit shown in Fig. 2 are as follows: the upper end of the first current sense resistor Rd1 is connected to the second current detecting electricity
Hinder Rd2 upper end, be also connected to the first triode Q1 base stage and current input terminal to be detected；First current sense resistor Rd1
Lower end be connected to the lower end of the second current sense resistor Rd2, be also connected to ground level；The collector of first triode Q1 connects
To the source of the 6th NMOS tube M6, the emitter of the first triode Q1 is connected to the upper end and the two or three pole of third biasing resistor R3
The emitter of pipe Q2；The base stage of second triode Q2 connects under the upper end and the first biasing resistor R1 of the second biasing resistor R2
End；The lower end of second biasing resistor R2 is connected to ground level；The upper end of first biasing resistor R1 connects the 5th biasing resistor R5's
The anode of lower end and voltage clamping diode Z1；The negative terminal of voltage clamping diode Z1 is connected to ground level；5th biasing resistor
The upper termination supply voltage of R5；The drain terminal of 6th NMOS tube M6 is connected to the drain terminal and grid end of the first PMOS tube M1, is also connected to
The grid end of second PMOS tube M2 and the grid end of the 4th PMOS tube M4；The drain terminal of second PMOS tube M2 is connected to the 7th NMOS tube M7's
Drain terminal is also connected to the drain terminal and grid end of third PMOS tube M3, is also connected to the grid end of the 5th PMOS tube M5；4th PMOS tube M4
Drain terminal be connected to the drain terminal of the 8th NMOS tube M8；The drain terminal of 5th PMOS tube M5 is connected to the drain terminal of the 9th NMOS tube M9；The
The source of eight NMOS tube M8 is connected to the drain terminal of the tenth NMOS tube M10, is also connected to the 13rd NMOS tube M13 and the 12nd PMOS
The grid end of pipe M12；The source of 9th NMOS tube M9 is connected to the drain terminal and grid end of the 11st NMOS tube M11；13rd NMOS tube
M13's is connected with the 12nd PMOS tube M12 drain terminal, and exports and differentiate signal OC；The lower end earth level of filter capacitor C1, filtering
The upper end of capacitor C1 is connected to the lower end of the 4th biasing resistor R4 and the anode of rectifier diode D1, and the upper end of filter capacitor C1 is also
It is connected to the grid end of the 6th NMOS tube M6, the 7th NMOS tube M7, the 8th NMOS tube M8 and the 9th NMOS tube M9, filter capacitor C1's
Upper end is also connected to the source of the 12nd PMOS tube M12；The source of remaining PMOS tube in addition to the 12nd PMOS tube M12 connects
Supply voltage；The equal earth level of source of 11st NMOS tube M11, the 13rd NMOS tube M13 and the tenth NMOS tube M10；It is all
The substrate of PMOS tube connects supply voltage, the equal earth level of the substrate of all NMOS tubes.
In figure by R1, R2, R3, R4, R5, Q1, Q2, Z1, C1, D1, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10,
The circuit that M11, M12 and M13 are constituted is a hysteresis voltage comparator.Electric current to be detected passes through 2 current detecting electricity in parallel
After hindering Rd1 and Rd2, detection voltage Vt is obtained.Current sense resistor Rd2 be variable resistance, for adjust current detection range and
Overcurrent threshold size.The negative terminal of comparator is the base voltage of Q1, to detect voltage Vt；The base stage electricity that the anode of comparator is Q2
Pressure is reference voltage REF.The filter capacitor C1 that M6, M7, M8 are connected with the grid end of M9 is for filtering out the point occurred on supply voltage
The interference of peak burr signal.Wherein R4, C1 and D1, which form biasing circuit, is fixed as the grid voltage of M6, M7, M8, M9 about
5.7V, the electric current of M2, M4 mirror image M1 in figure, and M2 electric current is 3 times of M1 electric current, the electric current of M5 mirror image M3.It is exported by GaN device
Electric current to be detected by current sense resistor Rd1 and Rd2 real-time detection, the voltage value Vt detected is input to the negative of comparator
End, is compared with the reference voltage REF of comparator anode.When electric current is normal, Vt ratio VREF high, comparator exports low electricity
It is flat.When electric current starts to become larger, Vt is further change in, and after feedback to comparator, the state of lock-in circuit keeps output constant.
When electric current slowly restores, Vt ratio REF high, the overturning of comparator output voltage.
The input and output simulation result of Fig. 3 is temperature when being 25 DEG C current foldback circuit, in figure as can be seen that voltage Vt just
Chang Shi, OC are height, and after Vt is slowly reduced, OC is lower from height；After Vt is slowly increased, OC is got higher from low.Data can from figure
With, it is evident that circuit realizes the function of hysteresis, negative sense threshold voltage is about 11.694V, and forward threshold voltage is about
12.643V amount of hysteresis is about 0.95V.
It will be appreciated by those skilled in the art that attached drawing is the schematic diagram of a preferred embodiment, above-mentioned the utility model is real
It is for illustration only to apply a serial number, does not represent the advantages or disadvantages of the embodiments.
The above is only the preferred embodiment of the present invention, is not intended to limit the utility model, all practical at this
Within novel spirit and principle, any modification, equivalent replacement, improvement and so on should be included in the guarantor of the utility model
Within the scope of shield.
Claims (1)
1. a kind of current foldback circuit for GaN power integration module, it is characterized in that: including 2 current sense resistors, 5
Biasing resistor, 1 voltage clamping diode, 1 rectifier diode, 1 filter capacitor C1,2 triodes, 7 NMOS tubes and 6
A PMOS tube；
The connection relationship of the current foldback circuit for GaN power integration module are as follows: the first current sense resistor Rd1's is upper
End is connected to the upper end of the second current sense resistor Rd2, is also connected to the base stage and electric current to be detected input of the first triode Q1
End；The lower end of first current sense resistor Rd1 is connected to the lower end of the second current sense resistor Rd2, is also connected to ground level；The
The collector of one triode Q1 is connected to the source of the 6th NMOS tube M6, and the emitter of the first triode Q1 is connected to third biasing
The emitter of the upper end of resistance R3 and the second triode Q2；The base stage of second triode Q2 connects the upper end of the second biasing resistor R2
With the lower end of the first biasing resistor R1；The lower end of second biasing resistor R2 is connected to ground level；The upper end of first biasing resistor R1
Connect the lower end of the 5th biasing resistor R5 and the anode of voltage clamping diode Z1；The negative terminal of voltage clamping diode Z1 is connected to
Ground level；The upper termination supply voltage of 5th biasing resistor R5；The drain terminal of 6th NMOS tube M6 is connected to the first PMOS tube M1's
Drain terminal and grid end are also connected to the grid end of the second PMOS tube M2 and the grid end of the 4th PMOS tube M4；The drain terminal of second PMOS tube M2
It is connected to the drain terminal of the 7th NMOS tube M7, the drain terminal and grid end of third PMOS tube M3 is also connected to, is also connected to the 5th PMOS tube
The grid end of M5；The drain terminal of 4th PMOS tube M4 is connected to the drain terminal of the 8th NMOS tube M8；The drain terminal of 5th PMOS tube M5 is connected to
The drain terminal of 9th NMOS tube M9；The source of 8th NMOS tube M8 is connected to the drain terminal of the tenth NMOS tube M10, is also connected to the 13rd
The grid end of NMOS tube M13 and the 12nd PMOS tube M12；The source of 9th NMOS tube M9 is connected to the leakage of the 11st NMOS tube M11
End and grid end；13rd NMOS tube M13's is connected with the 12nd PMOS tube M12 drain terminal, and exports and differentiate signal OC；Filter capacitor
The lower end earth level of C1, the upper end of filter capacitor C1 are connected to the lower end of the 4th biasing resistor R4 and the sun of rectifier diode D1
Pole, the upper end of filter capacitor C1 are also connected to the 6th NMOS tube M6, the 7th NMOS tube M7, the 8th NMOS tube M8 and the 9th NMOS tube
The grid end of M9, the upper end of filter capacitor C1 are also connected to the source of the 12nd PMOS tube M12；In addition to the 12nd PMOS tube M12
The source of remaining PMOS tube connect supply voltage；11st NMOS tube M11, the 13rd NMOS tube M13 and the tenth NMOS tube M10
The equal earth level of source；The substrate of all PMOS tube connects supply voltage, the equal earth level of the substrate of all NMOS tubes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821963635.1U CN209029377U (en) | 2018-11-27 | 2018-11-27 | Current foldback circuit for GaN power integration module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821963635.1U CN209029377U (en) | 2018-11-27 | 2018-11-27 | Current foldback circuit for GaN power integration module |
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| CN209029377U true CN209029377U (en) | 2019-06-25 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112230115A (en) * | 2020-10-13 | 2021-01-15 | 南京大学 | Avalanche test circuit integrating gallium nitride diode and triode and control method thereof |
| CN114825263A (en) * | 2022-05-26 | 2022-07-29 | 电子科技大学 | Integrated two-stage turn-off overcurrent protection circuit of full gallium nitride |
-
2018
- 2018-11-27 CN CN201821963635.1U patent/CN209029377U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112230115A (en) * | 2020-10-13 | 2021-01-15 | 南京大学 | Avalanche test circuit integrating gallium nitride diode and triode and control method thereof |
| CN114825263A (en) * | 2022-05-26 | 2022-07-29 | 电子科技大学 | Integrated two-stage turn-off overcurrent protection circuit of full gallium nitride |
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