CN114629488A

CN114629488A - Anti-backflow interface circuit

Info

Publication number: CN114629488A
Application number: CN202210296611.XA
Authority: CN
Inventors: 丁维贤; 肖建宏
Original assignee: Xinyi Information Technology Nanjing Co ltd; Xinyi Information Technology Shanghai Co ltd
Current assignee: Xinyi Information Technology Nanjing Co ltd; Xinyi Information Technology Shanghai Co ltd
Priority date: 2022-03-24
Filing date: 2022-03-24
Publication date: 2022-06-14

Abstract

The invention provides an anti-backflow interface circuit which comprises a power supply module, a gate tracking module, a floating well stabilizing module, an output driving stage module and a transistor. The backflow prevention is realized, and the chip is prevented from being awakened by mistake; the backflow prevention is realized through the cooperation of the gate tracking module, the floating well stabilizing module and the transistor, and the backflow prevention of the voltage or current of the chip is more stable and reliable; the floating trap module stabilizes the potential of the floating trap module, so that the floating trap module provides a stable first high potential, the backflow prevention stability is further improved, and the problems in the prior art are solved.

Description

Anti-backflow interface circuit

Technical Field

The invention relates to the technical field of semiconductors, in particular to an anti-backflow interface circuit.

Background

When the chip is in a low-power-consumption power-saving mode, for example, after the chip enters a sleep state, the voltage of the IO end of a General-purpose input/output (GPIO) power supply is 0, and if the GPIO peripheral interface is still hung with an electric IO interface, because there is a potential difference between the periphery and the inside of the GPIO, the voltage or the current of the peripheral IO interface will flow back to the chip power supply from the GPIO, thereby waking up the chip by mistake.

Chinese patent publication No. CN 203243306U discloses a chip multiplexing signal interface backflow prevention circuit, which includes a diode D1, a triode T1, a resistor R1 and a resistor R2, wherein a negative electrode of the diode D1 is connected to a system hardware interface, and a positive electrode of the diode D1 is connected to an emitter E of the triode T1; the base set B of the triode T1 is connected with the output pin of the chip, and the collector C of the triode T1 is grounded; the resistor R1 and the resistor R2 are connected in parallel and are connected with the anode of the diode D1, and the resistor R2 is also connected with an output pin of the chip. The utility model discloses a through add schottky diode D1 in order playing the effect of preventing flowing backward between hardware interface and triode T1, guarantee that 5V or 9V power can' T pour into the UART circuit, but this utility model only prevents flowing backward through a schottky diode, prevents flowing backward and unstable.

Therefore, it is desirable to provide a backflow prevention interface circuit to solve the above-mentioned problems in the prior art.

Disclosure of Invention

The invention aims to provide a backflow prevention interface circuit to solve the problems of backflow and unstable backflow prevention of a chip.

In order to achieve the above object, the interface circuit of the invention comprises a power supply module, a gate tracking module, a floating well stabilization module, an output driving stage module and a transistor, wherein the power supply module is connected with the gate tracking module, the floating well module and the floating well stabilization module, the gate tracking module is connected with a control movable end of the transistor and the floating well module, a source electrode of the transistor is connected with the power supply module, a drain electrode of the transistor is connected with the output driving stage module, the floating well module is connected with the floating well stabilization module, and the floating well module is used for stabilizing the potential of the floating well module;

when the chip enters a low power consumption state, the floating well module transmits a first high potential to the gate tracking module, and the gate tracking module receives the first high potential and then outputs a second high potential to the control end of the transistor so as to disconnect the power supply module from the output driving stage module.

The backflow prevention interface circuit has the advantages that: the backflow-preventing interface circuit comprises a power supply module, a gate tracking module, a floating trap stabilizing module, an output driving stage module and a transistor, wherein when a chip enters a low power consumption state, the floating trap module transmits a first high potential to the gate tracking module, the gate tracking module receives the first high potential and outputs a second high potential to a control end of the transistor so as to disconnect the electric connection between the power supply module and the output driving stage module, thereby preventing current from flowing backwards to the output power supply module, realizing backflow prevention and preventing the chip from being awakened by mistake; the backflow prevention is realized through the cooperation of the gate tracking module, the floating well stabilizing module and the transistor, and the backflow prevention of the voltage or the current of the chip is more stable and reliable; the floating trap module stabilizes the potential of the floating trap module, and the backflow prevention stability is further improved.

Optionally, the power supply module includes a battery, an IO power supply and an external power supply, the battery is connected to the IO power supply, the IO power supply is connected to the gate tracking module, the source of the transistor, the floating well module and the floating well stabilization module, and the external power supply is connected to the drain of the transistor through the backflow end.

Optionally, the floating well module includes a first PMOS transistor and a floating N-well, a gate of the first PMOS transistor is connected to the IO power supply, a substrate and a source of the first PMOS transistor are shorted and connected to the floating N-well, and the source of the first PMOS transistor is connected to the reverse flow end.

Optionally, the gate tracking module includes a second PMOS transistor, a gate of the second PMOS transistor is connected to the IO power supply, a source of the second PMOS transistor is connected to a source of the first PMOS transistor, a drain of the second PMOS transistor is connected to the control terminal of the transistor, and a substrate of the second PMOS transistor and a substrate of the transistor are both connected to the floating N-well.

Optionally, after the chip enters a low power consumption state, the output voltage of the IO power supply is 0, the gate voltage of the first PMOS transistor is 0, the source and the drain of the first PMOS transistor are turned on, the external power supply generates the first high potential and transmits the first high potential to the drain and the substrate of the first PMOS transistor through the backflow end, so that the potential of the floating N-well is the first high potential, and the potential of the substrate from the first high potential to the second PMOS transistor is the first high potential;

the grid voltage of the second PMOS tube is 0, the source electrode and the drain electrode of the second PMOS tube are conducted, and the drain electrode of the second PMOS tube outputs a second high potential to the control end of the transistor, so that the source electrode and the drain electrode of the transistor are disconnected, and the power supply module is disconnected from the output driving stage module. The power supply module has the advantages that after the chip enters a low power consumption state, the first PMOS tube is started to transmit the first high potential to the substrate of the second PMOS tube, the second PMOS tube is started to output the second high potential to the grid electrode of the transistor, so that the source electrode and the drain electrode of the transistor are disconnected, the power supply module is disconnected from the electric connection of the output driving stage module, the backflow prevention function is realized, the source electrode voltage of the second PMOS tube is raised by starting the first PMOS tube, the grid electrode voltage of the transistor is raised by starting the second PMOS tube, the backflow prevention stability is enhanced, and the situation of preventing backflow through false triggering is avoided.

Optionally, the floating well stabilizing module includes a first NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, where a gate of the first NMOS transistor is connected to the IO power supply and a gate of the third PMOS transistor, a drain of the first NMOS transistor is connected to a source of the third PMOS transistor and a source of the first PMOS transistor, and a source of the first NMOS transistor is connected to a drain of the third PMOS transistor and a gate of the fourth PMOS transistor;

the drain electrode of the fourth PMOS tube is connected with the IO power supply, and the source electrode of the fourth PMOS tube is in short circuit with the substrate and is connected with the source electrode of the first PMOS tube.

Optionally, when the chip is in a normal operating state, and when the chip is in the normal operating state, after the gate of the first NMOS transistor receives the output voltage of the IO power supply, the drain potential of the first NMOS transistor is a first low potential, the source and the drain of the first NMOS transistor are turned on, so that the first low potential is transmitted to the gate of the fourth PMOS transistor, so that the source and the drain of the fourth PMOS transistor are turned on, and the output voltage of the IO power supply is transmitted to the floating N-well through the fourth PMOS transistor;

after the grid electrode of the second PMOS tube receives the output voltage of the IO power supply, the source electrode and the drain electrode of the second PMOS tube are disconnected, and the drain electrode of the second PMOS tube outputs a second low potential to the control end of the transistor, so that the source electrode and the drain electrode of the transistor are conducted, and the output driving stage module works normally. The low-potential power amplifier has the advantages that when the chip is in a normal working state, the first NMOS tube is started, the source electrode and the drain electrode of the first NMOS tube are conducted so as to transmit the first low potential to the grid electrode of the fourth PMOS tube, so that the fourth PMOS tube is started, the source electrode and the drain electrode of the second PMOS tube are disconnected and output the second low potential to the control end of the transistor, so that the transistor is started, and the output driving stage module of the chip works normally; therefore, the floating well stabilizing module not only plays a role in stably preventing backflow when the chip enters a low power consumption state, but also plays a role in stabilizing the working state of the chip when the chip works normally.

Optionally, the backflow prevention interface circuit further includes an electrostatic discharge protection module, the electrostatic discharge protection module includes a battery electrostatic discharge unit, an IO power supply electrostatic discharge unit, and a floating N-well electrostatic discharge unit, the battery electrostatic discharge unit is connected to the battery, the IO power supply electrostatic discharge unit is connected to the IO power supply, and the floating N-well electrostatic discharge unit is connected to the floating N-well. The electrostatic discharge protection module has the advantages that the electrostatic discharge protection module is used for electrostatic discharge protection, so that damage of static electricity to a chip is reduced or even avoided, and the service life of the chip is prolonged.

Optionally, the output driving stage module includes a switch, a plurality of first inverters and a plurality of second inverters, the plurality of first inverters are connected in series, an output end of one of the first inverters is connected to a first end of the switch, a second end of the switch is connected to a control end of the transistor and a drain of the second PMOS transistor, and the plurality of second inverters are connected in series.

Optionally, the backflow-preventing interface circuit further includes a second NMOS transistor and a third NMOS transistor, a drain of the first NMOS transistor is connected to an output end of one of the second inverters and a gate of the third NMOS transistor, and a source of the second NMOS transistor and the substrate are shorted and grounded;

the drain electrode of the third NMOS tube is connected with the drain electrode of the transistor, and the source electrode of the third NMOS tube is in short circuit with the substrate and is grounded.

Optionally, the backflow prevention interface circuit further comprises a second NMOS transistor and a third NMOS transistor, a drain of the first NMOS transistor is connected to an output end of one of the second inverters and a gate of the third NMOS transistor, and a source of the second NMOS transistor is shorted with the substrate and grounded;

the drain electrode of the third NMOS tube is connected with the drain electrode of the transistor, and the source electrode of the third NMOS tube is in short circuit with the substrate and is grounded. The power supply circuit has the advantages that when the chip is in a low power consumption state, the grid electrode of the fifth PMOS tube receives a low level to be started, the drain electrode of the fifth PMOS tube outputs a high level to the grid electrode of the second NMOS tube, so that the second NMOS tube is started, current can flow out of the source electrode of the second NMOS tube to the ground, and the effect of preventing the current from flowing backwards to the output driver electrode module is achieved; therefore, the backflow prevention logic module can play a role in further backflow prevention, so that the backflow prevention effect is further enhanced, and the backflow prevention fault tolerance rate is improved.

Optionally, a gate of the fifth PMOS transistor is connected to a gate of the fourth NMOS transistor and the first end of the switch, a source of the fifth PMOS transistor is connected to a drain of the first PMOS transistor, a drain of the fifth PMOS transistor is connected to a drain of the fourth NMOS transistor and a gate of the second NMOS transistor, a substrate of the fifth PMOS transistor is connected to the floating N-well, and a source of the fourth NMOS transistor is grounded;

when the chip enters a low power consumption state, the fifth PMOS tube and the fourth PMOS tube generate switch control signals to control the switch to be switched off so as to prevent the first phase inverter from outputting current to the control end of the output driving stage transistor. The power supply circuit has the advantages that after the chip enters a low power consumption state, the fifth PMOS tube and the fourth PMOS tube generate switch control signals to control the switch to be switched off, the condition that the level of the second PMOS tube is pulled high is prevented from being transmitted to a previous electrode circuit, the condition that current at the first phase inverter flows backward to an IO power supply is avoided, and backflow prevention is further achieved.

Drawings

FIG. 1 is a schematic structural diagram of a backflow prevention interface circuit according to the present invention;

fig. 2 is a circuit diagram of the backflow prevention interface circuit according to the embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.

In view of the problems in the prior art, an embodiment of the present invention provides a backflow prevention interface circuit, and fig. 1 is a schematic structural diagram of the backflow prevention interface circuit of the present invention.

Referring to fig. 1, the anti-backflow interface circuit of the present invention includes a power supply module 1, a gate tracking module 2, a floating well module 3, a floating well stabilization module 4, an output driving stage module 5, and a transistor 6, where the power supply module 1 is connected to the gate tracking module 2, the floating well module 3, and the floating well stabilization module 4, the gate tracking module 2 is connected to the floating well module 3 and a control end of the transistor 6, a source of the transistor 6 is connected to the power supply module 1, a drain of the transistor 6 is connected to the output driving stage module 5, a substrate of the transistor 6 is connected to the floating well module 3, the floating well module 3 is connected to the floating well stabilization module 4, and the floating well module 3 is configured to stabilize a potential of the floating well module 3;

when the chip enters a low power consumption state, the floating well module 3 provides a first high potential to the gate tracking module 2, and the gate tracking module 2 receives the first high potential and then outputs a second high potential to the control end of the transistor 6 so as to disconnect the electric connection between the power supply module 1 and the output driving stage module 5.

The backflow prevention interface circuit has the advantages that: the anti-backflow interface circuit comprises a power supply module 1, a gate tracking module 2, a floating well module 3, a floating well stabilizing module 4, an output driving stage module 5 and a transistor 6, wherein when a chip enters a low power consumption state, the floating well module 3 transmits a first high potential to the gate tracking module 2, and the gate tracking module 2 receives the first high potential and outputs a second high potential to a control end of the transistor 6 so as to disconnect the electric connection between the power supply module 1 and the output driving stage module 5, so that the current is prevented from flowing backwards to the output power supply module, the anti-backflow is realized, and the chip is prevented from being awakened by mistake; the backflow prevention is realized through the cooperation of the gate tracking module 2, the floating well module 3, the floating well stabilizing module 4 and the transistor 6, and the backflow prevention of the voltage or current of the chip is more stable and reliable; the floating trap module 3 stabilizes the potential of the floating trap module 3, and the backflow prevention stability is further improved.

In some embodiments, the transistor 6 is a PMOS transistor, and the control terminal of the transistor 6 refers to a gate of the PMOS transistor.

In some embodiments, the anti-backflow interface circuit provided by the invention can be used for preventing backflow of GPIO (general purpose input/output), can be compatible with a segment code type LCD (liquid crystal display) interface, namely can be used for preventing backflow of the segment code type LCD interface, and has high compatibility.

As an alternative embodiment of the present invention, referring to fig. 2, the power supply module 1 includes a battery 11, an IO power supply 12, and an external power supply 13, the battery 11 is connected to the IO power supply 12, the IO power supply 12 is connected to the gate tracking module 2, the source of the transistor 6, the floating well module 3, and the floating well stabilization module 4, and the external power supply 13 is connected to the drain of the transistor 6 through a backward-flow terminal PAD.

As an optional implementation manner of the present invention, referring to fig. 2, the floating well module 3 includes a first PMOS transistor 31 and a floating N-well 32, a gate of the first PMOS transistor 31 is connected to the IO power supply 12, a substrate and a source of the first PMOS transistor 31 are shorted and connected to the floating N-well 32, and a source of the first PMOS transistor 31 is connected to the drain PAD.

As an optional implementation manner of the present invention, referring to fig. 2, the gate tracking module 2 includes a second PMOS transistor 21, a gate of the second PMOS transistor 21 is connected to the IO power supply 12, a source of the second PMOS transistor 21 is connected to a drain of the first PMOS transistor 31, a drain of the second PMOS transistor 21 is connected to the control terminal of the transistor 6, and a substrate of the second PMOS transistor 21 and a substrate of the transistor 6 are both connected to the floating N-well 32. Referring to fig. 2, FN of the substrate of the second PMOS transistor 21 and the substrate of the transistor 6 in the figure each represents a substrate-connected floating N-well 32.

As an optional implementation manner of the present invention, after the chip enters the low power consumption state, the output voltage of the IO power supply 12 is 0, the gate voltage of the first PMOS transistor 31 is 0, the source and the drain of the first PMOS transistor 31 are turned on, the external power supply 13 generates the first high potential and transmits the first high potential to the source of the first PMOS transistor 31 through the backward terminal PAD, the source and the drain of the first PMOS transistor 31 are turned on, and the source of the first PMOS transistor 31 transmits the first high potential to the drain of the first PMOS transistor 31, so that the floating N-well potentials of the third PMOS transistor 42 and the fourth PMOS transistor 43 are also the first high potential;

the gate voltage of the second PMOS transistor 21 is 0, the source and the drain of the second PMOS transistor 21 are turned on, and the drain of the second PMOS transistor 21 outputs a second high potential to the control end of the transistor 6, so that the source and the drain of the transistor 6 are disconnected, and the power supply module 1 and the output driver stage module 5 are disconnected from each other. The advantage is that, after the chip enters the low power consumption state, the first PMOS transistor 31 is turned on to transmit the first high potential to the substrate of the second PMOS transistor 21, and the second PMOS transistor 21 is turned on to output the second high potential to the gate of the transistor 6, so that the source and the drain of the transistor 6 are disconnected, thereby playing a role of layer-by-layer control, enhancing the stability of preventing backflow, and avoiding the situation of preventing backflow due to false triggering.

As an optional implementation manner of the present invention, referring to fig. 2, the floating well stabilizing module 4 includes a first NMOS transistor 41, a third PMOS transistor 42, and a fourth PMOS transistor 43, a gate of the first NMOS transistor 41 is connected to gates of the IO power supply 12 and the third PMOS transistor 42, a drain of the first NMOS transistor 41 is connected to a source of the third PMOS transistor 42 and a source of the first PMOS transistor 31, a source of the first NMOS transistor 41 is connected to a drain of the third PMOS transistor 42 and a gate of the fourth PMOS transistor 43, and a substrate of the first NMOS transistor 41 is grounded;

the source electrode of the fourth PMOS transistor 43 is connected to the IO power supply 12, and the source electrode of the fourth PMOS transistor 43 is shorted with the substrate and connected to the drain electrode of the first PMOS transistor 31;

referring to fig. 2, the substrate of the third PMOS transistor 42 is connected to FN, i.e., to the floating N-well 32, and the source and the substrate of the fourth PMOS transistor 43 are both connected to FN, i.e., to the floating N-well 32.

As an optional implementation manner of the present invention, when the chip is in a normal operating state, after the gate of the first NMOS transistor 41 receives the output voltage of the IO power supply 12, the potential of the drain of the first NMOS transistor is a first low potential, the source and the drain of the first NMOS transistor 41 are turned on, and the first low potential is transmitted to the gate of the fourth PMOS transistor 43, so that the source and the drain of the fourth PMOS transistor 43 are turned on, and the output voltage of the IO power supply 12 is transmitted to the floating N-well 32 through the fourth PMOS transistor 43;

after the gate of the second PMOS transistor 21 receives the output voltage of the IO power supply 12, the source and the drain of the second PMOS transistor 21 are disconnected, and the drain of the second PMOS transistor 21 outputs a second low potential to the control end of the transistor 6, so that the source and the drain of the transistor 6 are connected to enable the output driver module 5 to work normally. The advantage is that when the chip is in a normal working state, the first NMOS transistor 41 is turned on, so that the fourth PMOS transistor 43 is turned on, the source and the drain of the second PMOS transistor 21 are turned off, and a second low potential is output to the control end of the transistor 6, so that the transistor 6 is turned on, and the output driver stage module 5 of the chip works normally; therefore, the floating well stabilization module 4 not only plays a role in stabilizing and preventing backflow when the chip enters a low power consumption state, but also plays a role in stabilizing the working state of the chip when the chip works normally.

As an optional implementation manner of the present invention, referring to fig. 2, the backflow prevention interface circuit further includes an electrostatic discharge protection module 7, where the electrostatic discharge protection module 7 includes a battery electrostatic discharge unit 71, an IO power supply electrostatic discharge unit 72, and a floating well electrostatic discharge unit 73, the battery electrostatic discharge unit 71 is connected to the battery 11, the IO power supply electrostatic discharge unit 72 is connected to the IO power supply 12, and the floating well electrostatic discharge unit 73 is connected to the floating N well 32. The electrostatic discharge protection module 7 is used for electrostatic discharge protection, so that damage of static electricity to the chip is reduced or even avoided, and the service life of the chip is prolonged.

As an alternative embodiment of the present invention, referring to fig. 2, the output driving stage module 5 includes a switch 51, a plurality of first inverters 53 and a plurality of second inverters 54, the plurality of first inverters 53 are connected in series, an output terminal of one of the first inverters 53 is connected to a first terminal of the switch 51, a second terminal of the switch 51 is connected to a control terminal of the transistor 6 and a drain of the second PMOS transistor 21, and the plurality of second inverters 54 are connected in series.

As an optional implementation manner of the present invention, referring to fig. 2, the anti-backflow interface circuit further includes a second NMOS tube 9 and a third NMOS tube 91, a drain of the first NMOS tube 41 is connected to the second end of the second switch 52 and a gate of the third NMOS tube 91, and a source of the second NMOS tube 9 and a substrate are shorted and grounded;

the drain electrode of the third NMOS tube 91 is connected to the drain electrode of the transistor 6, and the source electrode of the third NMOS tube 91 is shorted with the substrate and grounded.

As an optional implementation manner of the present invention, referring to fig. 2, the anti-backflow interface circuit further includes an anti-backflow logic module 8, where the anti-backflow logic module 8 includes a fifth PMOS transistor 81 and a fourth NMOS transistor 82;

the gate of the fifth PMOS transistor 81 is connected to the gate of the fourth NMOS transistor 82 and the switch 51, the source of the fifth PMOS transistor 81 is connected to the drain of the first PMOS transistor 31, and the source of the fifth PMOS transistor 81 receives a potential signal of the PAD at the backward flow end; the substrate of the fifth PMOS transistor is connected to FN, that is, the substrate of the fifth PMOS transistor 81 is connected to the floating N-well 32; the drain electrode of the fifth PMOS transistor 81 is connected to the drain electrode of the fourth NMOS transistor 82 and the gate electrode of the second NMOS transistor 9, and the source electrode of the fourth NMOS transistor 82 is grounded;

when the chip enters a low power consumption state, the fifth PMOS transistor 81 and the fourth PMOS transistor 82 generate switch control signals to control the switch 51 to be switched off, so as to prevent the gate tracking module 2 from working, the second PMOS transistor 21 is turned on to pull up the potential on the right side of the switch 51, thereby preventing the pulled-up level of the second PMOS transistor 21 from being transmitted to a previous electrode circuit, and preventing the current at the first phase inverter 52 from flowing backwards to the IO power supply;

the gate of the fifth PMOS transistor 81 receives a low level to turn on, and the drain of the fifth PMOS transistor 81 outputs a high level to the gate of the second NMOS transistor 9, so that the second NMOS transistor 9 is turned on, and thus current flows out from the source of the second NMOS transistor 9 to ground, and a path from the PAD of the backward flow end of the third NMOS transistor 91 to ground is turned off; therefore, the backflow prevention logic module 8 can play a role in further backflow prevention, so that the backflow prevention effect is further enhanced, and the backflow prevention fault tolerance rate is improved.

Therefore, the backflow prevention logic module 8 can play a role in further backflow prevention, so that the backflow prevention effect is further enhanced, and the backflow prevention fault tolerance rate is improved.

In some embodiments, the flow of the backflow prevention interface circuit of the present invention is as follows:

(1) when the chip is in a normal working state, the IO power supply 12 outputs voltage VDDIO, and the external power supply 13 floats; the backward flow terminal PAD passively receives the high level transmitted by the transistor 6 or passively receives the low level transmitted by the third NMOS tube 91; at this time, the drain potential of the first NMOS transistor 41 is PAD low potential, the switch 51 is closed, and the third NMOS transistor 91 is turned on; the first PMOS tube 31, the second PMOS tube 21, the third PMOS tube 42 and the second NMOS tube 9 are all in a cut-off state; the gate of the first NMOS transistor 41 is turned on after receiving VDDIO, and the source and the drain of the first NMOS transistor 41 are conducted, so that a low level is transmitted to the fourth PMOS transistor 43, so that the fourth PMOS transistor 43 is turned on, and the source and the drain of the fourth PMOS transistor 43 are conducted, so that a voltage VDDIO is input to the floating N-well 32 through the fourth PMOS transistor 43, so that the voltage of the floating N-well 32 is VDDIO;

because the second PMOS transistor 21 is in the off state, the drain of the second PMOS transistor 21 outputs a low level to the control terminal of the transistor 6, so that the transistor 6 is turned on, and the source and the drain of the transistor 6 are turned on, thereby implementing the circuit connection between the IO power supply 12 and the output driver stage module 5, and at this time, the chip works normally.

(2) When the chip enters a low power consumption state, the output voltage VDDIO of the IO power supply 12 is 0, the first PMOS transistor 31, the second PMOS transistor 21, and the third PMOS transistor 42 are all turned on, the first NMOS transistor 41 is in an off state, the external power supply 13 generates the first high potential and transmits the first high potential to the source of the first PMOS transistor 31, and the first high potential is a PAD high potential; at this time, the drain of the first PMOA transistor 31, the drain of the first NMOS transistor 41, the drain of the third PMOS transistor, the drain of the transistor 6 and the floating N-well 32 are all PAD high potentials;

the drain of the first PMOS transistor 31 outputs a PAD high potential to the source of the second PMOS transistor 21, so as to pull up the source potential of the second PMOS transistor 21, and after the second PMOS transistor 21 is turned on, the potential output from the drain of the second PMOS transistor 21 to the gate of the transistor 6 is high, so that the transistor 6 is in a cut-off state, and the source and the drain of the transistor 6 are disconnected, so as to disconnect the electrical connection between the power supply module 1 and the output driver stage module 5, thereby realizing backflow prevention;

meanwhile, the fifth PMOS transistor 81 and the fourth PMOS transistor 82 generate switch control signals to control the switch 51 to be turned off, so as to prevent the first inverter 52 from outputting current to the control end of the transistor 6, and prevent the current output by the drain of the second PMOS transistor 21 from flowing backward to the output driver stage module 5, thereby further realizing backflow prevention;

meanwhile, as the potential of the output driving stage module 5 is low, the gate of the fifth PMOS transistor 81 receives a low potential and is turned on, and the source and the drain of the fifth PMOS transistor 81 are turned on, the PAD high potential is transmitted to the gate of the second NMOS transistor 9, so that the second NMOS transistor 9 is turned on, the current of the second inverter 53 is output to the ground, the backward flow of the current is avoided, and the backward flow prevention is further realized;

meanwhile, the second NMOS tube 9 is turned on to transmit the current of the second inverter 53 to the ground, and the gate level of the third NMOS tube 91 is low, so that the third NMOS tube 91 is in a cut-off state, the circuit connection between the external power supply 13 and the output driver stage module 5 is disconnected, and the current output by the external power supply 13 is prevented from leaking to GND through the third NMOS tube 91, thereby further achieving backflow prevention.

In summary, after the chip enters the low power consumption state, the interface circuit for preventing backflow can not only disconnect the power supply circuit 1 from the output driver stage module 5 by controlling the transistor 6 to enter the cut-off state, thereby realizing the first-stage backflow prevention; the first phase inverter 52 can be disconnected with the control end of the transistor 6 by controlling the switch 51 to be disconnected, so that secondary backflow prevention is realized; the current of the second phase inverter 53 can be transmitted to the ground by controlling the opening of the second NMOS tube 9, so that three-level backflow prevention is realized; the current output by the external power supply 13 is prevented from leaking to GND through the third NMOS tube 91 by controlling the third NMOS tube 91 to be turned off, so that four-stage backflow prevention is realized; therefore, the interface circuit for preventing backflow can perform multi-stage backflow prevention after the chip enters a low power consumption state, the backflow prevention stability is greatly enhanced, and the possibility of mistaken awakening of the chip is greatly reduced.

In some embodiments, the floating N-well 32 of the present invention can more broadly prevent the occurrence of back-flow, and has a fool-proof function;

in the prior art, when the voltage VDDIO of the IO power supply 12 is any value (0V/0.7V/1.8V/3V …), the GPIO will have a backward flow phenomenon as long as the PAD voltage is higher than VDDIO + Vth voltage; the floating well module 3 and the floating well stabilizing module 4 are matched to effectively avoid the backflow phenomenon, when VDDIO is less than PAD-Vth, the gate tracking module is started, wherein Vth is the threshold voltage of the second PMOS tube 21, when the interface circuit for preventing backflow works, as long as the PAD voltage is any voltage less than the voltage VBAT of the battery 11, the backflow preventing operation can be carried out, the backflow preventing is realized, and the function of preventing stagnation is achieved;

compared with the existing anti-backflow circuit, the circuit is simply added, the anti-backflow performance and stability are greatly improved, and the fault-tolerant rate of the circuit is improved.

In order to verify the effect of the anti-backflow interface circuit, the inventor also performs the following experiment:

(1) the chip enters a low power consumption state, the voltage VDDIO of the IO power supply 12 of the GPIO is 0, and the first high potential PAD of the GPIO is any level smaller than the voltage VBAT of the battery 11; through testing, the transistor 6 is in a cut-off state, the anti-backflow function of the GPIO is started, and the chip is not awakened by mistake;

(2) the voltage VBAT of a battery 11 of the chip is made to be 0V, the voltage VDDIO of an IO power supply 12 of the GPIO is also made to be 0 at the moment, the first high potential PAD of the GPIO is any level smaller than the voltage VBAT of the battery 11, through testing, the transistor 6 is in a cut-off state, the backflow prevention function of the GPIO is started, and the chip is not awoken by mistake;

therefore, when the battery is not charged, the backflow prevention interface circuit can still realize the backflow prevention function.

Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims

1. An interface circuit capable of preventing backflow is characterized by comprising a power supply module, a gate tracking module, a floating well stabilizing module, an output driving stage module and a transistor, wherein the power supply module is connected with the gate tracking module, the floating well module and the floating well stabilizing module;

2. The anti-backflow interface circuit as claimed in claim 1, wherein the power supply module comprises a battery, an IO power supply and an external power supply, the battery is connected to the IO power supply, the IO power supply is connected to the gate tracking module, the source of the transistor, the floating well module and the floating well stabilization module, and the external power supply is connected to the drain of the transistor through a backflow terminal.

3. The anti-backflow interface circuit as claimed in claim 2, wherein the floating well module comprises a first PMOS transistor and a floating N-well, a gate of the first PMOS transistor is connected to the IO power supply, a substrate and a drain of the first PMOS transistor are shorted and connected to the floating N-well, and a source of the first PMOS transistor is connected to the backflow terminal.

4. The anti-backflow interface circuit of claim 3, wherein the gate tracking module comprises a second PMOS tube, a gate of the second PMOS tube is connected to the IO power supply, a source of the second PMOS tube is connected to a source of the first PMOS tube, a drain of the second PMOS tube is connected to the control terminal of the transistor, and a substrate of the second PMOS tube and a substrate of the transistor are both connected to the floating N-well.

5. The anti-backflow interface circuit according to claim 4, wherein after the chip enters a low power consumption state, the output voltage of the IO power supply is 0, the gate voltage of the first PMOS transistor is 0, the source and the drain of the first PMOS transistor are turned on, the external power supply generates the first high potential and transmits the first high potential to the drain and the substrate of the first PMOS transistor through the backflow terminal, so that the potential of the floating N-well is the first high potential, and the potential of the first high potential to the substrate of the second PMOS transistor is the first high potential;

the grid voltage of the second PMOS tube is 0, the source electrode and the drain electrode of the second PMOS tube are conducted, and the drain electrode of the second PMOS tube outputs a second high potential to the control end of the transistor, so that the source electrode and the drain electrode of the transistor are disconnected, and the power supply module is disconnected from the output driving stage module.

6. The anti-backflow interface circuit of claim 4, wherein the floating well stabilization module comprises a first NMOS transistor, a third PMOS transistor and a fourth PMOS transistor, a gate of the first NMOS transistor is connected to the IO power supply and a gate of the third PMOS transistor, a drain of the first NMOS transistor is connected to a source of the third PMOS transistor and a source of the first PMOS transistor, and a source of the first NMOS transistor is connected to a drain of the third PMOS transistor and a gate of the fourth PMOS transistor;

7. The anti-backflow interface circuit as claimed in claim 6, wherein when the chip is in a normal operating state, after the gate of the first NMOS transistor receives the output voltage of the IO power supply, the drain potential of the first NMOS transistor is a first low potential, the source and the drain of the first NMOS transistor are turned on, so that the first low potential is transmitted to the gate of the fourth PMOS transistor, so that the source and the drain of the fourth PMOS transistor are turned on, and the output voltage of the IO power supply is transmitted to the floating N-well through the fourth PMOS transistor;

after the grid electrode of the second PMOS tube receives the output voltage of the IO power supply, the source electrode and the drain electrode of the second PMOS tube are disconnected, the drain electrode of the second PMOS tube outputs a second low potential to the control end of the transistor, the source electrode and the drain electrode of the transistor are connected, and the output driving stage module works normally.

8. The anti-backflow interface circuit according to claim 3, further comprising an electrostatic discharge protection module, wherein the electrostatic discharge protection module comprises a battery electrostatic discharge unit, an IO power supply electrostatic discharge unit and a floating N-well electrostatic discharge unit, the battery electrostatic discharge unit is connected to the battery, the IO power supply electrostatic discharge unit is connected to the IO power supply, and the floating N-well electrostatic discharge unit is connected to the floating N-well.

9. The anti-backflow interface circuit as claimed in claim 6, wherein the output driving stage module comprises a switch, a plurality of first inverters and a plurality of second inverters, the plurality of first inverters are connected in series, an output terminal of one of the first inverters is connected to a first terminal of the switch, a second terminal of the switch is connected to a control terminal of the transistor and a drain of the second PMOS transistor, and the plurality of second inverters are connected in series.

10. The anti-backflow interface circuit as claimed in claim 9, further comprising a second NMOS transistor and a third NMOS transistor, wherein a drain of the first NMOS transistor is connected to an output terminal of one of the second inverters and a gate of the third NMOS transistor, and a source of the second NMOS transistor is shorted to the substrate and grounded;

11. The interface circuit of claim 10, further comprising a back-flow prevention logic module, wherein the back-flow prevention logic module comprises a fifth PMOS transistor and a fourth NMOS transistor;

the grid electrode of the fifth PMOS tube is connected with the grid electrode of the fourth NMOS tube and the first end of the switch, the source electrode of the fifth PMOS tube is connected with the drain electrode of the first PMOS tube, the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fourth NMOS tube and the grid electrode of the second NMOS tube, the substrate of the fifth PMOS tube is connected with the floating N-well, and the source electrode of the fourth NMOS tube is grounded;

when the chip enters a low power consumption state, the fifth PMOS tube and the fourth PMOS tube generate a switch control signal to control the switch to be switched off so as to prevent the first phase inverter from outputting current to the control end of the output driving stage transistor.