CN210742767U

CN210742767U - Circuit for stabilizing grid voltage of driving tube by buzzer

Info

Publication number: CN210742767U
Application number: CN201921386309.3U
Authority: CN
Inventors: 张怀东
Original assignee: Wuxi Shiding Electronic Technology Co ltd
Current assignee: Wuxi Shiding Electronic Technology Co ltd
Priority date: 2019-08-26
Filing date: 2019-08-26
Publication date: 2020-06-12
Anticipated expiration: 2029-08-26

Abstract

The utility model provides a circuit that is used for buzzer to stabilize driving tube grid voltage, including logic control circuit, NMOS pipe MN1, NMOS pipe MN 2. The input F of the logic control circuit is a frequency signal, the output N1 of the logic control circuit is connected to the grid of an NMOS tube MN1, the output N2 of the logic control circuit is connected to the grid of the NMOS tube MN2, the drain of the NMOS tube MN1 is connected to a power line, the source of the NMOS tube MN1 is connected to the grid G of an NMOS driving tube of the buzzer, the substrate of the NMOS tube MN1 is connected to the ground line, the drain of the NMOS tube MN2 is connected to the grid G of the NMOS driving tube of the buzzer, the source of the NMOS tube MN2 is connected to the ground line, and the substrate of the NMOS tube MN2 is connected to the ground line. The utility model discloses a logic control circuit control MN1, the opening time of the grid of two NMOS pipes of MN2 play and prevent that buzzer NMOS drive tube grid voltage from following the effect that mains voltage descends together. The circuit has the advantages of simple structure and low cost.

Description

Circuit for stabilizing grid voltage of driving tube by buzzer

Technical Field

The utility model relates to a buzzer circuit field, concretely relates to a circuit that is used for buzzer to stabilize driving tube grid voltage.

Background

As shown in fig. 6, in the conventional gate driving circuit of the buzzer driving tube, when the voltage of the power line drops, the gate voltage of the buzzer driving tube drops along with the voltage of the power line, so that the driving capability of the buzzer driving tube is insufficient, and even the output frequency of the buzzer is unstable.

SUMMERY OF THE UTILITY MODEL

The utility model provides a circuit that is used for bee calling organ to stabilize driving tube grid voltage when mains voltage descends to solve the grid voltage of bee calling organ driving tube and follow the problem that mains voltage descends together, when preventing mains voltage from descending, the driving force of bee calling organ driving tube is not enough, can arouse bee calling organ output frequency's unstability even.

In order to solve the technical problem, the utility model provides a circuit that is used for buzzer to stabilize drive tube grid voltage, including logic control circuit, NMOS pipe MN1, NMOS pipe MN 2. The input F of the logic control circuit is a frequency signal, the output N1 of the logic control circuit is connected to the grid of an NMOS tube MN1, the output N2 of the logic control circuit is connected to the grid of the NMOS tube MN2, the drain of the NMOS tube MN1 is connected to a power line, the source of the NMOS tube MN1 is connected to the grid G of an NMOS driving tube of the buzzer, the substrate of the NMOS tube MN1 is connected to the ground line, the drain of the NMOS tube MN2 is connected to the grid G of the NMOS driving tube of the buzzer, the source of the NMOS tube MN2 is connected to the ground line, and the substrate of the NMOS tube MN2 is connected to the ground line.

Preferably, the source terminal and the drain terminal of the NMOS transistor MN1 and MN2 are reversed.

The utility model discloses the beneficial effect who brings: the utility model provides a pair of a circuit that is used for bee calling organ to stabilize driving tube grid voltage plays the effect that prevents that bee calling organ NMOS driving tube grid voltage from following mains voltage and descend together through the opening time of the grid of two NMOS pipes of logic control circuit control MN1, MN 2. The circuit has the advantages of simple structure and low cost.

Drawings

Fig. 1 is a schematic structural diagram of a circuit for stabilizing a gate voltage of a driving tube of a buzzer according to the present invention.

Fig. 2 is a schematic diagram of a circuit timing sequence for stabilizing a gate voltage of a driving tube of a buzzer according to a first embodiment of the present invention.

Fig. 3 is a schematic diagram of a circuit timing sequence for stabilizing the gate voltage of the driving tube by the buzzer according to the second embodiment of the present invention.

Fig. 4 is a schematic diagram of a circuit timing sequence for stabilizing the gate voltage of the driving tube by the buzzer according to the third embodiment of the present invention.

Fig. 5 is a schematic diagram of a circuit timing sequence for stabilizing the gate voltage of the driving tube by the buzzer according to the fourth embodiment of the present invention.

Fig. 6 is a schematic diagram of the background art.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.

As shown in fig. 1, the utility model provides a circuit for buzzer stabilizes drive tube grid voltage, including editing control circuit, NMOS pipe MN1, NMOS pipe MN 2. The input F of the logic control circuit is a frequency signal, the output N1 of the logic control circuit is connected to the grid of an NMOS tube MN1, the output N2 of the logic control circuit is connected to the grid of the NMOS tube MN2, the drain of the NMOS tube MN1 is connected to a power line, the source of the NMOS tube MN1 is connected to the grid G of an NMOS driving tube of the buzzer, the substrate of the NMOS tube MN1 is connected to the ground line, the drain of the NMOS tube MN2 is connected to the grid G of the NMOS driving tube of the buzzer, the source of the NMOS tube MN2 is connected to the ground line, and the substrate of the NMOS tube MN2 is connected to the ground line.

The utility model discloses a first embodiment: the working sequence is shown in fig. 2, and referring to fig. 1, F is the frequency signal generated inside the chip, when the level of F changes to open the driving tube of the NMOS of the buzzer, that is, at the beginning of t1, the output N1 of the logic control circuit is at low level, the NMOS transistor MN1 is kept at off state, the output N2 of the logic control circuit changes from high level to low level, the NMOS transistor MN2 changes from on state to off state, the gate G of the buzzer NMOS driving transistor is kept at low level, at the end of t1, the output N1 of the logic control circuit changes from low to high, and since the NMOS transistor MN2 is turned off, therefore, the power supply charges the grid G of the buzzer NMOS driving tube through the MOS tube MN1, the buzzer NMOS driving tube is turned on, when the power supply voltage drops below the grid voltage of the buzzer NMOS driving tube, since the NMOS transistor MN1 is turned off, the gate voltage of the buzzer NMOS driver transistor does not drop along with the power supply voltage.

The utility model discloses a second embodiment: the working sequence is as shown in fig. 3, with reference to fig. 1, F is a frequency signal generated inside the chip, when the level of F changes to open the buzzer NMOS driving tube, the output N1 of the logic control circuit changes from low level to high level, the NMOS tube MN1 changes from off state to on state, the output N2 of the logic control circuit changes from high level to low level, and the NMOS tube MN2 changes from on state to off state, so that the power supply charges the gate G of the buzzer NMOS driving tube through the MOS tube MN1, the buzzer NMOS driving tube is turned on, and when the power supply voltage drops below the gate voltage of the buzzer NMOS driving tube, the gate voltage of the buzzer NMOS driving tube does not drop along with the power supply voltage because the NMOS tube MN1 is turned off.

The utility model discloses a third embodiment: as shown in fig. 4, with reference to fig. 1, F is a frequency signal generated inside the chip, when the level of F changes to turn on the NMOS transistor of the buzzer, i.e. at the beginning of t1, the output N1 of the logic control circuit is at a high level, the NMOS transistor MN1 changes from an off state to an on state, the output N2 of the logic control circuit is at a low level, and the NMOS transistor MN2 remains at an on state, at this time, since the NMOS transistor MN1 and the NMOS transistor MN2 are both in an on state, the magnitude of the current charging the gate G of the NMOS transistor of the buzzer is related to the resistance values of the NMOS transistor MN1 and the NMOS transistor MN2, and the sum of the resistance values of the NMOS transistor MN1 and the NMOS transistor MN2 cannot be too small, which causes a large drop of the power supply inside the chip, at the end of t1, the output N2 of the logic control circuit changes from a high level to a low level, the NMOS transistor MN2 changes from an on state to an off state, so that the power supply charges the gate G of the NMOS transistor MN1 of the buzzer through the, the opening degree of the buzzer NMOS driving tube is increased, and when the power voltage drops to be lower than the grid voltage of the buzzer NMOS driving tube, the grid voltage of the buzzer NMOS driving tube cannot drop along with the power voltage because the NMOS tube MN1 is cut off.

The fourth embodiment of the present invention: the working sequence is shown in fig. 5, and referring to fig. 1, F is the frequency signal generated inside the chip, when the level of F changes to open the driving tube of the NMOS of the buzzer, that is, at the beginning of t1, the output N1 of the logic control circuit changes from low level to high level, the NMOS transistor MN1 changes from off state to on state, the output N2 of the logic control circuit changes from high level to low level, the NMOS transistor MN2 changes from on state to off state, therefore, the power supply charges the grid G of the buzzer NMOS driving tube through the MOS tube MN1, the buzzer NMOS driving tube is turned on, at the end of t1, the output N1 of the logic control circuit changes from high level to low level, the NMOS transistor MN1 changes from on state to off state, when the power voltage drops below the gate voltage of the buzzer NMOS driving transistor, since the NMOS transistor MN1 is turned off, the gate voltage of the buzzer NMOS driver transistor does not drop along with the power supply voltage.

The fourth embodiment of the utility model discloses a second embodiment's an improve embodiment, it is similar, also can be right the utility model discloses a first embodiment with right the utility model discloses a third embodiment improves, after the grid G to the buzzer NMOS drive tube charges, quick ending NMOS pipe MN1, when supply voltage descends to reduce the electric leakage of buzzer NMOS drive tube grid.

To sum up, the utility model provides a pair of a circuit that is used for buzzer to stabilize driving tube grid voltage plays the effect that prevents buzzer NMOS driving tube grid voltage from following mains voltage and descend together through the open time of the grid of two NMOS pipes of logic control circuit control MN1, MN 2. The circuit has the advantages of simple structure and low cost.

The above description is only an example of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A circuit for stabilizing grid voltage of a driving tube of a buzzer comprises a logic control circuit, an NMOS tube MN1 and an NMOS tube MN2, wherein input F of the logic control circuit is a frequency signal, an output N1 of the logic control circuit is connected to the grid of the NMOS tube MN1, an output N2 of the logic control circuit is connected to the grid of the NMOS tube MN2, the drain of the NMOS tube MN1 is connected to a power line, the source of the NMOS tube MN1 is connected to the grid G of the NMOS driving tube of the buzzer, the substrate of the NMOS tube MN1 is connected to the ground line, the drain of the NMOS tube MN2 is connected to the grid G of the NMOS driving tube of the buzzer, the source of the NMOS tube MN2 is connected to the ground line, and the substrate of the NMOS tube MN2 is connected to the.

2. The circuit for stabilizing the gate voltage of the driving tube of the buzzer as claimed in claim 1, wherein the source terminal and the drain terminal of the NMOS tube MN1 and MN2 are reversed without affecting the normal operation of the circuit.