CN102195578A - Output buffer circuit and method capable of inhibiting voltage overshoot - Google Patents
Output buffer circuit and method capable of inhibiting voltage overshoot Download PDFInfo
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Abstract
The invention relates to an output buffer circuit capable of inhibiting voltage overshoot. The output buffer circuit comprises an input stage, an output stage, a clamping circuit and a control unit, wherein, the input stage is used for generating a current signal according to an input voltage; the output stage is used for generating an output voltage according to the current signal; the clamping circuit is coupled with the input stage and the output stage and is used for confining the output voltage within a preset range; and the control unit is coupled with the clamping circuit and is used for starting the clamping circuit when the output buffer circuit receives the input voltage and shutting down the clamping circuit when the level of the output voltage reaches a stable state. The invention further relates to an output buffer method capable of inhibiting voltage overshoot.
Description
Technical field
The present invention refers to a kind of output buffer that suppresses voltage overshoot, refer to especially a kind of by in time closing clamp circuit, the output buffer of avoiding leakage current to cause system deviation voltage to change.
Background technology
The output stage of existing display driver adopts operation amplifier circuit, to reach the purpose to the load end fast charging and discharging, makes that its driving force is more and more stronger.Yet, when operational amplifier internal current recovery capacity is not enough, can produce voltage overshoot (overshoot) phenomenon to the load end fast charging and discharging.Generally speaking, between the input of the output of operational amplifier and its output stage, add a clamp circuit (clamping circuit) and can suppress the voltage overshoot phenomenon.Yet, having at operational amplifier under the situation of full swing (fullswing) output, clamp circuit may cut out fully, causes a little leakage current generating (about nA grade).Under lower powered application, this unnecessary leakage current will cause the change of display driver overall offset voltage (offset voltage).
Please refer to Fig. 1, Fig. 1 is the schematic diagram of a known operational amplifier 10.Operational amplifier 10 is a two-stage amplifier, and it includes an input stage 11, an output bias circuit 12, an output stage 13 and a clamp circuit 14.Input stage 11 is differential input levels of a tool track to track input range, and it has a positive input terminal AVP and a negative input end AVN.Input stage 11 produces a current signal IAB according to the input voltage that positive input terminal AVP is received.Output bias circuit 12 is coupled to input stage 11, is used for according to current signal IAB, in producing a dynamic biasing VAB (being the voltage difference between node AA and node AB) between node AA and the AB.The AB class output stage that output stage 13 is made up of transistor P9 and N9, it has the negative input end AVN that input AVF back coupling is coupled to input stage 11.Output stage 13 provides a drive current to output terminals A VF according to dynamic biasing AB, to produce an output voltage.14 of clamp circuits are made up of transistor POS1, POS2, NOS1, NOS2, are used for the output voltage of operational amplifier 10 is fixed in the preset range, to avoid taking place the phenomenon of voltage overshoot.
When 10 pairs of loads of operational amplifier are charged, for example receive the input voltage of high levle, the voltage of positive input terminal AVP rises, and the current signal IAB of the feasible output bias circuit 12 of flowing through diminishes, and causes the voltage of node AA and node AB to descend.In this case, the drive current that provides to output terminals A VF will be provided output stage 13, improves the output voltage of operational amplifier, shown in the part of the solid line among Fig. 1.On the contrary, when 10 pairs of loads of operational amplifier are discharged, for example receive the input voltage of low level, the voltage of positive input terminal AVP descends, and it is big that the current signal IAB of the feasible output bias circuit 12 of flowing through becomes, and causes the voltage of node AA and node AB to rise.In this case, the drive current that provides to output terminals A VF will be provided output stage 13, to reduce the output voltage of operational amplifier, shown in the dotted portion among Fig. 1.
Under normal circumstances, the accurate position of output voltage can make the overdrive voltage (overdrive voltage) of transistor POS2 or NOS2 less than its critical voltage, i.e. (AVF-VBPOS)＜Vthp or (VBNOS-AVF)＜Vthn, and cause transistor POS2 or NOS2 to close.Therefore, under normal circumstances, clamp circuit 14 can not produce any effect to discharging and recharging of operational amplifier.Yet when the accurate position of output voltage exceeded a preset range, the overdrive voltage of transistor POS2 or NOS2 can be greater than its critical voltage, i.e. (AVF-VBPOS)＞Vthp or (VBNOS-AVF)＞Vthn, and cause transistor POS2 or NOS2 conducting.In this case, electric current can flow into node AA or AB from output terminals A VF, helps the voltage of node AA or AB to reply normal accurate position, and reduces the degree of voltage overshoot.
Yet, having at operational amplifier under the situation of full swing output, transistor POS2 or NOS2 may close fully, and cause a little leakage current generating.With the discharge is example, and the output voltage of operational amplifier may be low to moderate 0.1 volt, and transistor NOS1 and NOS2 can't close fully this moment, causes still having a little electric current on the path of transistor NOS1 and NOS2 and flows through (flowing into node AB by output terminals A VF).Under lower powered application, the electric current on each road falls lower and lower in the operational amplifier, so leakage current causes the change amount of transistor P11 and N11 current value and the variable quantity of overdrive voltage to get over obviously, and then influences the bias state and the direct current of output stage 13.When the direct current of output stage 13 changes, the transduction value of output stage 13 and the gain size of operational amplifier also can change, and the gain size of operational amplifier can directly have influence on the system deviation voltage (systematicoffset voltage) of operational amplifier.
In brief, under lower powered application, the electric current on each road falls lower and lower in the operational amplifier, under the situation of full swing output, clamp circuit can't cut out the current value change that causes the output bias circuit fully and get over obviously, cause integral operation Amplifier Gain value to change, and influence the system deviation voltage of operational amplifier.
Summary of the invention
The present invention discloses a kind of output buffer that suppresses voltage overshoot, and it includes an input stage, an output bias circuit, an output stage, a clamp circuit and a control unit.This input stage includes a positive input terminal and a negative input end, and this positive input terminal is used for receiving an input voltage, and this input stage produces a current signal according to this input voltage.This output bias circuit is coupled to this input stage, is used for producing a dynamic biasing according to this current signal.This output stage is coupled to this input stage and this output bias circuit, includes an output and at least one output transistor.This output is feedback and is coupled to this negative input end.This at least one output transistor is coupled to this output bias circuit and this output, is used for according to this dynamic biasing, provides a drive current to this output, to produce an output voltage.This clamp circuit is coupled to this input stage, this output bias circuit and this output, be used for when the accurate position of this output voltage exceeds a preset range, draw electric current from this output,, make this dynamic biasing reply a default accurate position so that this current signal is compensated.This control unit is coupled to this clamp circuit, is used for starting this clamp circuit when this output buffer receives this input voltage, and when the accurate position of this output voltage reaches a stable state, closes the running of this clamp circuit.
The present invention discloses a kind of method that an output buffer suppresses voltage overshoot that is used in addition.This output buffer includes an input stage, an output stage and a clamp circuit.This input stage produces a current signal according to an input voltage.This output stage produces an output voltage according to this current signal.This clamp circuit is coupled to this input stage and this output stage, is used for this output voltage strangulation within a preset range.This method includes the following step: when receiving this input voltage, start the running of this clamp circuit; Begin to export this output voltage; And when the accurate position of this output voltage reaches a stable state, close the running of this clamp circuit.
Therefore, main purpose of the present invention is to provide a kind of output buffer and method that suppresses voltage overshoot.The present invention adds clamp circuit in output buffer, and by suitable FREQUENCY CONTROL, solve simultaneously under lower powered application, more and more stronger voltage overshoot phenomenon that causes of its output stage driving force and the inhibition system deviation voltage that it changed, but additionally do not increase operational amplifier current drain and area cost.
Description of drawings
Fig. 1 is the schematic diagram of a known operational amplifier.
Fig. 2 can improve the schematic diagram of an output buffer of voltage overshoot for the embodiment of the invention.
Fig. 3 is the signal timing diagram of Fig. 2 output buffer.
Fig. 4 is an embodiment schematic diagram of Fig. 1 control unit.
Fig. 5 is another embodiment schematic diagram of Fig. 1 control unit.
Fig. 6 is the schematic diagram that a voltage overshoot of the embodiment of the invention suppresses flow process.
Wherein, description of reference numerals is as follows:
10,41,51 operational amplifiers
11,21 input stages
12,22 output bias circuit
13,23 output stages
14,24 clamp circuits
AVP, AVN input
The AVF output
AA, AB node
The IAB current signal
N1～N3, P1～P3, P9, N9, P11, transistor
N11、POS1、POS2、NOS1、NOS2
VBPOS, VBNOS, VBN1, VBP1, bias voltage
VBP3、VBN3
20 output buffers
25 control units
VDDA power supply supply voltage
The GNDA ground voltage
252 circuits for triggering
254 timers
The T1 triggering signal
256 voltage detection circuits
258 comparing units
60 voltage overshoots suppress flow process
600～640 steps
Embodiment
Please refer to Fig. 2, Fig. 2 can improve the schematic diagram of an output buffer 20 of voltage overshoot for the embodiment of the invention.Output buffer 20 includes an input stage 21, an output bias circuit 22, an output stage 23, a clamp circuit 24 and a control unit 25.Input stage 21 is differential input levels of a tool track to track input range, and it has a positive input terminal AVP and a negative input end AVN.Input stage 11 produces a current signal IAB according to the input voltage that positive input terminal AVP is received.Output bias circuit 22 is coupled to input stage 21, is used for according to current signal IAB, in producing a dynamic biasing VAB (being the voltage difference between node AA and node AB) between node AA and the AB.The AB class output stage that output stage 23 is made up of transistor P9 and N9, it has the negative input end AVN that input AVF back coupling is coupled to input stage 21.Output stage 23 provides a drive current to output terminals A VF according to dynamic biasing AB, to produce an output voltage.24 of clamp circuits are made up of transistor POS1, POS2, NOS1, NOS2, be used for when the accurate position of output voltage exceeds a preset range, VF draws electric current from output terminals A, so that current signal IAB is compensated, make dynamic biasing reply a default accurate position, and avoid taking place the phenomenon of voltage overshoot.Control unit 25 is coupled to clamp circuit 24, is used for when output buffer 20 receives input voltage, and control clamp circuit 24 comes into operation it, and when the accurate position of output voltage reaches a stable state, closes the running of clamp circuit 24.Note that input stage 21, output bias circuit 22, output stage 23 and clamp circuit 24 only are of the present invention one explanation for example, it can pass through operation amplifier circuit realization of arbitrary form, and is not limited thereto.
In embodiments of the present invention, transistor POS1 and POS2 are P type MOS (metal-oxide-semiconductor) transistor, are used for the accurate position strangulation of output voltage is preset under the accurate position of high voltage one; And transistor NOS1, NOS2 are N type MOS (metal-oxide-semiconductor) transistor, then are used for the accurate position strangulation of output voltage is preset on the accurate position of low-voltage one.The gate of transistor POS2 is coupled to a working bias voltage VBPOS, and the gate of transistor NOS2 is coupled to a working bias voltage VBNOS.The accurate position of working bias voltage VBPOS, VBNOS is switched by control unit 25.When output buffer 20 received input voltage, control unit 25 can switch to working bias voltage VBPOS, VBNOS the accurate position of one normal bias voltage, so that clamp circuit 24 comes into operation; And when the voltage quasi position of output terminals A VF reached stable state, control unit 25 can switch to working bias voltage VBPOS, VBNOS respectively one a power supply supply voltage VDDA and a ground voltage GNDA, to close transistor POS2 and NOS2, clamp circuit 24 was decommissioned.
Please refer to Fig. 3, Fig. 3 is the signal timing diagram of Fig. 2 output buffer 20.At first, phase when data load, output buffer 20 receives the aanalogvoltage that front stage circuits is exported.At this moment, working bias voltage VBPOS, VBNOS can switch to the accurate position of normal bias voltage respectively, and clamp circuit 24 is come into operation, and avoid the phenomenon of the voltage quasi position generation voltage overshoot of output terminals A VF.Then, when the voltage quasi position of output terminals A VF reaches stable state, control unit 25 can switch to working bias voltage VBPOS, VBNOS respectively power supply supply voltage VDDA and ground voltage GNDA, come positive closing transistor POS2 and NOS2, make that no any electric current flows through on the path of transistor POS1, POS2, NOS1, NOS2.Thus, after output voltage reached stable state, the leakage current that the embodiment of the invention can be avoided clamp circuit 24 impacted the bias state and the integral operation Amplifier Gain of output stage.
In embodiments of the present invention, control unit 25 can judge whether output voltage reaches stable state by following dual mode, but is not limited thereto.Wherein a kind of mode is after output buffer 20 receives input voltage one Preset Time, judges that the accurate position of output voltage has reached stable state; And another kind of mode is after output buffer 20 receives input voltage, and is different by the accurate potential difference of detecting output terminals A VF and positive input terminal AVP, judges whether the accurate position of output voltage reaches stable state.
For instance, please refer to Fig. 4, Fig. 4 is an embodiment schematic diagram of Fig. 1 control unit 25.For the sake of clarity, the input stage 21 of Fig. 1, output bias circuit 22, output stage 23 and clamp circuit 24 are with an operational amplifier 41 expressions.As shown in Figure 4, control unit 25 includes circuits for triggering 252 and a timer 254.Circuits for triggering 252 are used for when output buffer 20 receives input voltage, and phase when for example entering data load produces a triggering signal T1.Timer 2 54 is coupled to circuits for triggering 252, then is used for calculating a Preset Time according to triggering signal T1, judges for control unit 25 whether the accurate position of output voltage has reached stable state.Thus, control unit 25 can switch to power supply supply voltage VDDA and ground voltage GNDA respectively with working bias voltage VBPOS, VBNOS, to close the running of clamp circuit 24 after Preset Time.
Please refer to Fig. 5, Fig. 5 is another embodiment schematic diagram of Fig. 5 control unit 25.Similarly, the input stage 21 of Fig. 1, output bias circuit 22, output stage 23 and clamp circuit 24 are also with an operational amplifier 51 expressions.As shown in Figure 5, control unit 25 includes a voltage detection circuit 256 and a comparing unit 258.Voltage detection circuit 256 is coupled to positive input terminal AVP and output terminals A VF, is used for detecting the voltage quasi position of positive input terminal AVP and output terminals A VF.Comparing unit 258 is coupled to voltage detection circuit 256, is used in the accurate potential difference of output terminals A VF and positive input terminal AVP differently during less than a default value, judges that the accurate position of output voltage has reached stable state.Thus, control unit 25 can switch to power supply supply voltage VDDA and ground voltage GNDA respectively with working bias voltage VBPOS, VBNOS, to close the running of clamp circuit 24 after output voltage reaches stable state.
Therefore, pass through the foregoing description, the present invention can solve that clamp circuit can't cut out in some cases fully and the problem that influences operational amplifier system deviation voltage makes circuit characteristic more stable, but additionally do not increase operational amplifier current drain and unit are cost.
Please refer to Fig. 6, Fig. 6 is the schematic diagram that a voltage overshoot of the embodiment of the invention suppresses flow process 60.It is operating processes of above-mentioned output buffer 20 that voltage overshoot suppresses flow process 60, and it includes the following step:
Step 600: beginning.
Step 610: when receiving input voltage, open the running of clamp circuit 24.
Step 620: begin to export output voltage.
Step 630: when the accurate position of output voltage reaches stable state, close the running of clamp circuit 24
Step 640: finish.
In sum, the present invention adds clamp circuit in output buffer, and by suitable FREQUENCY CONTROL, solve simultaneously under lower powered application, more and more stronger voltage overshoot phenomenon that causes of its output stage driving force and the inhibition system deviation voltage that it changed, but additionally do not increase operational amplifier current drain and area cost.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (17)
1. output buffer that can suppress voltage overshoot is characterized in that including:
One input stage includes a positive input terminal and a negative input end, and this positive input terminal is used for receiving an input voltage, and this input stage produces a current signal according to this input voltage;
One output bias circuit is coupled to this input stage, is used for producing a dynamic biasing according to this current signal;
One output stage is coupled to this input stage and this output bias circuit, includes:
One output, back coupling is coupled to this negative input end; And
At least one output transistor is coupled to this output bias circuit and this output, is used for according to this dynamic biasing, provides a drive current to this output, to produce an output voltage;
One clamp circuit, be coupled to this input stage, this output bias circuit and this output, be used for when the accurate position of this output voltage exceeds a preset range, drawing electric current from this output, so that this current signal is compensated, make this dynamic biasing reply a default accurate position; And
One control unit is coupled to this clamp circuit, is used for starting this clamp circuit when this output buffer receives this input voltage, and when the accurate position of this output voltage reaches a stable state, closes the running of this clamp circuit.
2. output buffer as claimed in claim 1 is characterized in that this control unit after this output buffer receives this input voltage one Preset Time, judges that the accurate position of this output voltage reaches this stable state.
3. output buffer as claimed in claim 2 is characterized in that this control unit includes: circuits for triggering are used for producing a triggering signal when this output buffer receives this input voltage; And
One timer is coupled to this circuits for triggering, is used for calculating this Preset Time according to this triggering signal.
4. output buffer as claimed in claim 1, it is characterized in that this control unit is after this output buffer receives this input voltage, different by the accurate potential difference of detecting this output and this positive input terminal, judge whether the accurate position of this output voltage reaches this stable state.
5. output buffer as claimed in claim 4 is characterized in that this control unit includes:
One voltage detection circuit is coupled to this positive input terminal and this output, is used for detecting the voltage quasi position of this positive input terminal and this output; And a comparing unit, be coupled to this voltage detection circuit, be used in the accurate potential difference of this output and this positive input terminal differently during less than a default value, judge that the accurate position of this output voltage reaches this stable state.
6. output buffer as claimed in claim 1 is characterized in that this clamp circuit includes:
One first MOS (metal-oxide-semiconductor) transistor includes one source pole and is coupled to this output, and a gate is coupled to a working bias voltage, and a drain; And
One second MOS (metal-oxide-semiconductor) transistor includes this drain that one source pole is coupled to this first MOS (metal-oxide-semiconductor) transistor, and a gate is coupled to this bias generating circuit and this at least one output transistor, and a drain is coupled to this gate;
Wherein, the accurate position of this working bias voltage is switched by this control unit.
7. output buffer as claimed in claim 6, it is characterized in that this control unit is when this output buffer receives this input voltage, this working bias voltage is switched to one first accurate position, this clamp circuit is come into operation, and when the voltage quasi position of this output reaches this stable state, this working bias voltage is switched to one second accurate position, to close the running of this clamp circuit.
8. output buffer as claimed in claim 7, it is characterized in that this first MOS (metal-oxide-semiconductor) transistor and this second MOS (metal-oxide-semiconductor) transistor are all P type MOS (metal-oxide-semiconductor) transistor, be used for the accurate position strangulation of this output voltage is preset under the accurate position of high voltage one, and this second accurate position is that a power supply is supplied voltage.
9. output buffer as claimed in claim 7, it is characterized in that this first MOS (metal-oxide-semiconductor) transistor and this second MOS (metal-oxide-semiconductor) transistor are all N type MOS (metal-oxide-semiconductor) transistor, be used for the accurate position strangulation of this output voltage is preset on the accurate position of low-voltage one, and this second accurate position is a ground voltage.
10. output buffer as claimed in claim 1 is characterized in that this input stage is the differential input level of a tool track to track input range.
11. output buffer as claimed in claim 10, it is right to reaching the differential input of a P type metal-oxide-semiconductor (MOS) to it is characterized in that this input stage includes the differential input of a N type metal-oxide-semiconductor (MOS).
12. output buffer as claimed in claim 1 is characterized in that this output bias circuit includes a pair of CMOS (Complementary Metal Oxide Semiconductor) transistor that connects in the head-to-tail mode.
13. output buffer as claimed in claim 1 is characterized in that this at least one output transistor forms an AB class output stage.
14. one kind is used for the method that an output buffer suppresses voltage overshoot, this output buffer includes an input stage, an output stage and a clamp circuit, this input stage is according to an input voltage, produce a current signal, this output stage produces an output voltage according to this current signal, and this clamp circuit is coupled to this input stage and this output stage, be used for this output voltage strangulation within a preset range, it is characterized in that this method includes:
When receiving this input voltage, start the running of this clamp circuit;
Begin to export this output voltage; And
When the accurate position of this output voltage reaches a stable state, close the running of this clamp circuit.
15. method as claimed in claim 14 is characterized in that closing the step of this clamp circuit when the accurate position of this output voltage reaches this stable state, includes:
After receiving this input voltage one Preset Time, judge that the accurate position of this output voltage reaches this stable state.
16. method as claimed in claim 14 is characterized in that closing the step of this clamp circuit when the accurate position of this output voltage reaches this stable state, includes:
After receiving this input voltage, different by the accurate potential difference of detecting this output voltage and this input voltage, judge whether the accurate position of this output voltage reaches this stable state.
17. method as claimed in claim 16 is characterized in that judging whether the accurate position of this output voltage reaches the step of this stable state, includes:
Different during in the accurate potential difference of this output voltage and this input voltage less than a default value, judge that the accurate position of this output voltage reaches this stable state.
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| CN 201010132147 CN102195578B (en) | 2010-03-09 | 2010-03-09 | Output buffer circuit and method capable of inhibiting voltage overshoot |
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| CN 201010132147 CN102195578B (en) | 2010-03-09 | 2010-03-09 | Output buffer circuit and method capable of inhibiting voltage overshoot |
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| CN102195578B CN102195578B (en) | 2013-11-06 |
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| CN105811958A (en) * | 2015-08-31 | 2016-07-27 | 威盛电子股份有限公司 | Output buffer device |
| CN106341092A (en) * | 2016-08-18 | 2017-01-18 | 苏州源智宇电子科技有限公司 | Low-voltage and low-power-consumption operational amplifier |
| CN106972836A (en) * | 2015-12-18 | 2017-07-21 | 台湾积体电路制造股份有限公司 | Semiconductor devices and circuit protection method |
| CN109660220A (en) * | 2018-12-19 | 2019-04-19 | 四川长虹电器股份有限公司 | Amplifier output signal clamp voltage control circuit |
| CN109917842A (en) * | 2019-04-16 | 2019-06-21 | 卓捷创芯科技（深圳）有限公司 | A kind of metastable clamper feedback start-up circuit of elimination automatic biasing band-gap reference degeneracy |
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| CN109660220A (en) * | 2018-12-19 | 2019-04-19 | 四川长虹电器股份有限公司 | Amplifier output signal clamp voltage control circuit |
| CN109917842A (en) * | 2019-04-16 | 2019-06-21 | 卓捷创芯科技（深圳）有限公司 | A kind of metastable clamper feedback start-up circuit of elimination automatic biasing band-gap reference degeneracy |
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| CN102195578B (en) | 2013-11-06 |
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