CN111884505A

CN111884505A - Level conversion circuit with ultra-wide voltage range

Info

Publication number: CN111884505A
Application number: CN202010831511.3A
Authority: CN
Inventors: 李柯烨; 李爱夫; 胡封林
Original assignee: Hunan Central Core Valley Technology Co ltd
Current assignee: Hunan Central Core Valley Technology Co ltd
Priority date: 2020-08-18
Filing date: 2020-08-18
Publication date: 2020-11-03

Abstract

The invention discloses a level conversion circuit with an ultra-wide voltage range, which comprises a transistor MP1 and a transistor MN1, wherein the gate of the transistor MP1 is connected with the gate and the input end EN of the transistor MN1, the source of the transistor MP1 is connected with a power supply VCC, the drain of the transistor MP1 is connected with the drain of the transistor MN1, the gate of the transistor MP2, the gate of the transistor MN2 and the gate of the transistor MN5, and the drain of the transistor MP2 is connected with the drain of the transistor MN2 and the gate of the transistor MN 4.

Description

Level conversion circuit with ultra-wide voltage range

Technical Field

The invention relates to the technical field of level conversion, in particular to a level conversion circuit with an ultra-wide voltage range.

Background

The level shifter is a voltage conversion device, the level shift is divided into one-way shift and two-way shift, and also includes single power supply and double power supply shift, the double power supply shift adopts double track scheme to satisfy the performance requirements of all aspects. In the design of new generation electronic circuits, with the introduction of low voltage logic, the problem of inconsistent input/output logic often occurs inside the system, thereby increasing the complexity of the system design. For example: when a 1.8V digital circuit communicates with an analog circuit operating at 3.3V, the problem of two-level conversion needs to be solved first, and a level shifter is needed.

The existing level shifter circuit has the disadvantages of complex structure, limited input voltage range and narrow application range.

Disclosure of Invention

The present invention is directed to a level shift circuit with an ultra-wide voltage range, so as to solve the problems mentioned in the background art.

In order to achieve the purpose, the invention provides the following technical scheme:

a level conversion circuit with an ultra-wide voltage range comprises a transistor MP1 and a transistor MN1, wherein the gate of the transistor MP1 is connected with the gate of the transistor MN1 and an input end EN, the source of the transistor MP1 is connected with a power supply VCC, the drain of the transistor MP1 is connected with the drain of the transistor MN1, the gate of the transistor MP2, the gate of the transistor MN2 and the gate of the transistor MN5, the drain of the transistor MP2 is connected with the drain of the transistor MN2 and the gate of the transistor MN4, the drain of the transistor MN4 is connected with the drain of the transistor MP4, the gate of the transistor MP4 is connected with the drain of the transistor MP4 and the gate of the transistor MN4, the drain of the transistor MP4 is connected with the drain of the transistor MN4, the gate of the transistor MP4 and the gate of the transistor MN4 are connected with the drain of the transistor MP4, the drain of the transistor MP8 is connected to the drain of the transistor MN8 and the output terminal OUT, the source of the transistor MP1 is connected to the power source VCC, the source of the transistor MN1 is grounded, the source of the transistor MP2 is connected to the power source VCC, the source of the transistor MN2 is grounded, the source of the transistor MP4 is connected to the power source VCC, the source of the transistor MN4 is grounded, the source of the transistor MP5 is connected to the power source VCC, the source of the transistor MN5 is grounded, the source of the transistor MP6 is connected to the power source VCC, the source of the transistor MN6 is grounded, the source of the transistor MP7 is connected to the power source VCC, the source of the transistor MN7 is grounded, the source of the transistor MP 85.

As a further technical scheme of the invention: the transistor MP1 and the transistor MN1 form a first inverter; the transistor MP2 and the transistor MN3 constitute a second inverter.

As a further technical scheme of the invention: the transistors MP4 and MP5 are cross-coupled and the transistors MN4 and MN5 are a first-pole level conversion circuit.

As a further technical scheme of the invention: the transistor MN6, the transistor MN7 are cross-coupled and a second pole level conversion circuit of the transistor MP6 and the transistor MP7 is provided.

As a further technical scheme of the invention: the transistor MP8 and the transistor MN9 form a third inverter.

As a further technical scheme of the invention: the transistors MP1, MP2, MP4, MP5, MP6, MP7 and MP8 are P-type enhancement mode field effect transistors.

As a further technical scheme of the invention: the transistor MN1, the transistor MN2, the transistor MN4, the transistor MN5, the transistor MN6, the transistor MN7 and the transistor MN8 are all N-type enhancement mode field effect transistors.

Compared with the prior art, the invention has the beneficial effects that: the level conversion circuit with the ultra-wide voltage range adopts a plurality of transistors to form the level conversion circuit and a plurality of inverters, and can complete level conversion with the ultra-wide voltage (positive and negative voltages).

Drawings

Fig. 1 is a schematic diagram of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, embodiment 1: a level conversion circuit with an ultra-wide voltage range comprises a transistor MP1 and a transistor MN1, wherein the gate of the transistor MP1 is connected with the gate of the transistor MN1 and an input end EN, the source of the transistor MP1 is connected with a power supply VCC, the drain of the transistor MP1 is connected with the drain of the transistor MN1, the gate of the transistor MP2, the gate of the transistor MN2 and the gate of the transistor MN5, the drain of the transistor MP2 is connected with the drain of the transistor MN2 and the gate of the transistor MN4, the drain of the transistor MN4 is connected with the drain of the transistor MP4, the gate of the transistor MP4 is connected with the drain of the transistor MP4 and the gate of the transistor MN4, the drain of the transistor MP4 is connected with the drain of the transistor MN4, the gate of the transistor MP4 and the gate of the transistor MN4 are connected with the drain of the transistor MP4, the drain of the transistor MP8 is connected to the drain of the transistor MN8 and the output terminal OUT, the source of the transistor MP1 is connected to the power source VCC, the source of the transistor MN1 is grounded, the source of the transistor MP2 is connected to the power source VCC, the source of the transistor MN2 is grounded, the source of the transistor MP4 is connected to the power source VCC, the source of the transistor MN4 is grounded, the source of the transistor MP5 is connected to the power source VCC, the source of the transistor MN5 is grounded, the source of the transistor MP6 is connected to the power source VCC, the source of the transistor MN6 is grounded, the source of the transistor MP7 is connected to the power source VCC, the source of the transistor MN7 is grounded, the source of the transistor MP 85.

The transistor MP1 and the transistor MN1 form a first inverter; the transistor MP2 and the transistor MN3 constitute a second inverter. The transistor MP4, the transistor MP5 are cross-coupled and the transistor MN4, the transistor MN5 are a first pole level conversion circuit. The transistor MN6, the transistor MN7 are cross-coupled and the transistor MP6, the transistor MP7 are set as a second pole level conversion circuit. The transistor MP8 and the transistor MN9 constitute a third inverter.

In the circuit, V + is a positive power supply at a high-voltage side, V-is a negative power supply, VCC is a positive power supply at a low-voltage side, and GND is a reference zero level; the logic level of the low voltage may output a strong "0" with reference to a zero level through the first and second inverters; translating the logic level on the VCC and GND voltage rails to the voltage rails of V + and GND through a first level conversion circuit; the logic level of the V + and GND voltage rails is translated to the voltage rails of V + and V-through a second level conversion circuit; and finally, the output is output by a third inverter and is the V + and V-voltage track logic level. When VCC is not equal to V + and GND is not equal to V-; what is done is (VCC and GND) to (V + and V-) level conversion; when VCC is not equal to V + and GND is V-; what is done is (VCC and GND) to (V + and GND) level conversion; when VCC is V +, GND is not equal to V-; what is done is (VCC and GND) to (VCC and V-) level conversion; when VCC is V +, GND is not equal to V-; what is done is (VCC and GND) to (VCC and GND) level conversion;

as can be seen from the above, the level shift circuit can perform level shift in an ultra-wide voltage (positive and negative voltage) range.

In embodiment 2, on the basis of embodiment 1, the transistor used in the design may be a transistor, such as a triode, an MOS transistor, or a field effect transistor, and may be selected and used flexibly.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. A level conversion circuit with an ultra-wide voltage range comprises a transistor MP1 and a transistor MN1, and is characterized in that the gate of the transistor MP1 is connected with the gate of a transistor MN1 and an input end EN, the source of the transistor MP1 is connected with a power supply VCC, the drain of a transistor MP1 is connected with the drain of a transistor MN1, the gate of a transistor MP2, the gate of a transistor MN2 and the gate of a transistor MN5, the drain of a transistor MP2 is connected with the drain of the transistor MN2 and the gate of the transistor MN4, the drain of the transistor MN4 is connected with the drain of the transistor MP4, the gate of the transistor MP4 and the gate of the transistor MP4, the drain of the transistor MP4 is connected with the drain of the transistor MN4, the gate of the transistor MP4 and the gate of the transistor MN4, the drain of the transistor MP8 is connected to the drain of the transistor MN8 and the output terminal OUT, the source of the transistor MP1 is connected to the power source VCC, the source of the transistor MN1 is grounded, the source of the transistor MP2 is connected to the power source VCC, the source of the transistor MN2 is grounded, the source of the transistor MP4 is connected to the power source VCC, the source of the transistor MN4 is grounded, the source of the transistor MP5 is connected to the power source VCC, the source of the transistor MN5 is grounded, the source of the transistor MP6 is connected to the power source VCC, the source of the transistor MN6 is grounded, the source of the transistor MP7 is connected to the power source VCC, the source of the transistor MN7 is grounded, the source of the transistor MP 85.

2. The ultra-wide voltage range level shifter circuit of claim 1, wherein the transistor MP1 and the transistor MN1 form a first inverter; the transistor MP2 and the transistor MN3 constitute a second inverter.

3. A ultra-wide voltage range level shifter circuit as claimed in claim 1, wherein said transistors MP4, MP5 are cross-coupled and a first pole level shifter circuit of the group of transistors MN4, MN 5.

4. A ultra-wide voltage range level shifter circuit as claimed in claim 1, wherein said transistor MN6, transistor MN7 are cross-coupled and a second pole of the group of transistors MP6, MP7 is a level shifter circuit.

5. The ultra-wide voltage range level shifter circuit of claim 3, wherein the transistor MP8 and the transistor MN9 form a third inverter.

6. A ultra-wide voltage range level shifter circuit as recited in claim 3, wherein said transistor MP1, transistor MP2, transistor MP4, transistor MP5, transistor MP6, transistor MP7, and transistor MP8 are P-type enhancement mode fets.

7. A ultra-wide voltage range level shifter circuit as claimed in claim 3, wherein said transistor MN1, MN2, MN4, MN5, MN6, MN7 and MN8 are N-type enhancement mode fets.